CN201444313U - High-speed image acquisition functional sorter based on FPGA - Google Patents
High-speed image acquisition functional sorter based on FPGA Download PDFInfo
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- CN201444313U CN201444313U CN 200820157951 CN200820157951U CN201444313U CN 201444313 U CN201444313 U CN 201444313U CN 200820157951 CN200820157951 CN 200820157951 CN 200820157951 U CN200820157951 U CN 200820157951U CN 201444313 U CN201444313 U CN 201444313U
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Abstract
A high-speed image acquisition functional sorter based on FPGA belongs to important devices of sorters, and is characterized in that the functional sorter adopts a three-passage double-sampling AD work mode, utilizes a USB to transmit image data and utilizes the FPGA to process and control image signals. The three-passage double-sampling AD portion comprises a CIS sensor, an AD9822 and an ispXPLD_LC5512MV, the portion utilizing the USB to transmit image data comprises an ispXPLD-LC5512MV and a CY7C68012A, and the intelligent paper currency discriminating sorter can achieve high-speed sorting of 900 pages per minute and has multiple sorting functions such as sorting old and new paper currencies, sides and editions of the paper currencies and the like. The high-speed image acquisition functional sorter based on FPGA can acquire images of the paper currencies through the FPGA faster and complete image treatment and identification faster, thereby treating more paper currencies in a certain time, leading quality of acquired images to be higher, and enabling discrimination of the paper currencies to be more accurate, and providing a reliable guarantee for properties of the sorter.
Description
Technical field
The utility model patent belongs to the finance device technical field.
Background technology
At present, extensively using in sorting, the false distinguishing of bank note, their function has: the number of the true and false of identification note, the Currency Type of checking bank note, the various bank note of calculating.Wherein difficult point shows the sorting of bank note again, wherein have again new and old sorting, pros and cons to sorting, top and bottom to sorting, face amount sorting, version sorting etc.
Because bank note has the two sides, the newness degree on two sides may be different, the image of singly adopting one side may cause certain error to the sorting effect, the appearance of the product of this patent, can be with the better effects if of sorting coin, feasible function is more powerful, the sorting better effects if, more stable, be the desirable utensil of financial institution's office.
The utility model content
In order to increase work efficiency, satisfy the needs of financial office automation, portability, the utility model patent provides based on FPGA high-speed image sampling function cleaning-sorting machine.Comprise based on FPGA high-speed image sampling function cleaning-sorting machine: adopt the two sampling of triple channel AD mode of operation, adopt USB to image data transmission with adopt processing and the control of FPGA picture signal.
The two sampling of described triple channel AD part comprises CIS sensor, AD9822, ispXPLD_LC5512MV.
Described USB comprises ispXPLD_LC5512MV, CY7C68013A to the image data transmission part.
The utility model is based on FPGA high-speed image sampling function cleaning-sorting machine, it is characterized in that, the two sampling of described employing triple channel AD mode of operation, when the voltage that collection CIS sensor transmissions is come, the AD9822 three-channel voltage of red, green and blue of sampling simultaneously, two signal controlling that the sampled point of two samplings that each is relevant is produced by ispXPLD_LC5512MV, the negative edge of a signal is to the sampling of the datum in the CMOS waveform, and the negative edge of another signal is to the data level sampling;
The utility model is based on FPGA high-speed image sampling function cleaning-sorting machine, it is characterized in that, described employing USB is to image data transmission, in order to increase the speed of USB transmission digital video signal, adopt USB the fast reading and writing pattern configurations clock-control register of USB, adopt accesses data memory at full speed, clock frequency is 24MHz, USB links to each other with PC, produces signal by ispXPLD_LC5512MV, image is preserved for PC in hard disk image data transmission on the following jumping edge of signal;
Described in the utility model based on FPGA high-speed image sampling function cleaning-sorting machine, it is characterized in that, described employing FPGA is to the processing and the control of picture signal, gathering the data of coming in is three-channel data, only the high eight-bit data of storage two passages wherein reach the data compression effect, and there are two different address fields respectively in two logical data, after not stored data line, produce a look-at-me two segment datas are pieced together group.And with complete image data storage in RAM.
The utility model is based on FPGA high-speed image sampling function cleaning-sorting machine, and simple in structure clear, speed is fast, and good stability is convenient to operation and maintenance.
Description of drawings
Fig. 1 CIS sensor synoptic diagram
Fig. 2 is based on FPGA high-speed image sampling circuit board synoptic diagram
Fig. 3 is based on FPGA high-speed image sampling principle of work synoptic diagram
Embodiment
Further specify the embodiment of the utility model patent below in conjunction with accompanying drawing.
As shown in Figure 1, CIS sensor synoptic diagram, long is 232mm, and wide is 18mm, and connector is the pin mouth of CIS sensor.
As shown in Figure 2, based on FPGA high-speed image sampling circuit board synoptic diagram, CIS slot 1, AD9822 modulus conversion chip 2, ispXPLD_LC5512MV logic chip 3, the USB chip 4 of CY7C68013A, USB chip crystal oscillator 5, USB interface 6,75723 power supply chips 7, AMS1117 power supply chip 8, logic chip crystal oscillator 9, power supply slot 10, resistance 11, resistance 12.
Fig. 3 is based on FPGA high-speed image sampling principle of work synoptic diagram, when it is images acquired, and the working condition of each parts.
Claims (4)
1. based on FPGA high-speed image sampling function cleaning-sorting machine, it is characterized in that, adopt the two sampling of triple channel AD mode of operations, adopt USB to image data transmission with adopt processing and the control of FPGA picture signal, the two sampling of described triple channel AD part comprises CIS sensor, AD9822, ispXPLD_LC5512MV.Described USB comprises ispXPLD_LC5512MV, CY7C68013A to the image data transmission part.
2. according to claim 1 based on FPGA high-speed image sampling function cleaning-sorting machine, it is characterized in that, the two sampling of described employing triple channel AD mode of operation, when the voltage that collection CIS sensor transmissions is come, the AD9822 three-channel voltage of red, green and blue of sampling simultaneously, two signal controlling that the sampled point of two samplings that each is relevant is produced by ispXPLD_LC5512MV, the negative edge of a signal is to the sampling of the datum in the CMOS waveform, and the negative edge of another signal is to the data level sampling.
3. according to claim 1 based on FPGA high-speed image sampling function cleaning-sorting machine, it is characterized in that, described high speed algorithm based on the usb communication agreement transmits view data, in order to increase the speed of USB transmission digital video signal, adopt USB the fast reading and writing pattern configurations clock-control register of USB, adopt accesses data memory at full speed, clock frequency is 24MHz, ispxPLD_LC5512MV utilizes the high speed edge algorithms to find the valid data edge of banknote image, and utilize USB to produce the intramarginal data, USB links to each other with PC, and PC is preserved image in hard disk.
4. according to claim 1 based on FPGA high-speed image sampling function cleaning-sorting machine, it is characterized in that, described employing FPGA carries out two-sided channel compensation collection to picture signal, utilize the characteristic image data of AD9822 to gather simultaneously by two ends, the left and right sides, for pulling speed faster, only store the high eight-bit data of two passages wherein, reach the effect of data compression, when gathering each point data, utilize backoff algorithm to remove the interference that binary channels is gathered simultaneously, there are two different address fields respectively in the data of two passages, behind the intact data line of every storage, produce a look-at-me two segment datas pieced together group, and with complete image data storage in RAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 200820157951 CN201444313U (en) | 2008-12-26 | 2008-12-26 | High-speed image acquisition functional sorter based on FPGA |
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| CN 200820157951 CN201444313U (en) | 2008-12-26 | 2008-12-26 | High-speed image acquisition functional sorter based on FPGA |
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| CN201444313U true CN201444313U (en) | 2010-04-28 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625056A (en) * | 2012-03-30 | 2012-08-01 | 广东正业科技股份有限公司 | FPGA (Field-Programmable Gate Array)-based CIS (Contact Image Sensor) image acquisition system and acquisition method thereof |
| CN103617674A (en) * | 2013-10-23 | 2014-03-05 | 东方通信股份有限公司 | Bill discharging machine core capable of identifying crown word number, and crown word number identification method thereof |
| CN104104820A (en) * | 2014-07-03 | 2014-10-15 | 宁波术有电子科技有限公司 | Low-power image acquisition device and realization method thereof |
| CN104103119A (en) * | 2014-07-03 | 2014-10-15 | 宁波术有电子科技有限公司 | High-speed paper money serial number recognition system and realizing method thereof |
| WO2015003485A1 (en) * | 2013-07-08 | 2015-01-15 | 广州中智融通金融科技有限公司 | Image compensation correction method and banknote recognition and detection device |
| CN110844508A (en) * | 2019-11-18 | 2020-02-28 | 中科微至智能制造科技江苏有限公司 | Parcel transportation control method and system |
-
2008
- 2008-12-26 CN CN 200820157951 patent/CN201444313U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625056A (en) * | 2012-03-30 | 2012-08-01 | 广东正业科技股份有限公司 | FPGA (Field-Programmable Gate Array)-based CIS (Contact Image Sensor) image acquisition system and acquisition method thereof |
| WO2015003485A1 (en) * | 2013-07-08 | 2015-01-15 | 广州中智融通金融科技有限公司 | Image compensation correction method and banknote recognition and detection device |
| AU2014289868B2 (en) * | 2013-07-08 | 2016-06-09 | Grg Banking Equipment Co., Ltd. | Image compensation correction method and banknote recognition and detection device |
| US9685022B2 (en) | 2013-07-08 | 2017-06-20 | Grg Banking Equipment Co., Ltd. | Image compensation correction method and banknote recognition and detection device |
| CN103617674A (en) * | 2013-10-23 | 2014-03-05 | 东方通信股份有限公司 | Bill discharging machine core capable of identifying crown word number, and crown word number identification method thereof |
| CN103617674B (en) * | 2013-10-23 | 2015-09-02 | 东方通信股份有限公司 | Cash-out movement and the crown word number identification method thereof of crown word number can be identified |
| CN104104820A (en) * | 2014-07-03 | 2014-10-15 | 宁波术有电子科技有限公司 | Low-power image acquisition device and realization method thereof |
| CN104103119A (en) * | 2014-07-03 | 2014-10-15 | 宁波术有电子科技有限公司 | High-speed paper money serial number recognition system and realizing method thereof |
| CN104104820B (en) * | 2014-07-03 | 2017-03-22 | 宁波术有电子科技有限公司 | Realization method of low-power image acquisition device |
| CN110844508A (en) * | 2019-11-18 | 2020-02-28 | 中科微至智能制造科技江苏有限公司 | Parcel transportation control method and system |
| CN110844508B (en) * | 2019-11-18 | 2021-03-02 | 中科微至智能制造科技江苏股份有限公司 | Parcel transportation control method and system |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHANGHAI GUAO ELECTRONIC TECHNOLOGY CO., LTD. Free format text: FORMER NAME: SHANGHAI GUAO ELECTRONIC MACHINERY CO. LTD. |
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| CP01 | Change in the name or title of a patent holder |
Address after: 200333 Shanghai city Putuo District Tong Pu Lu Lane 1225 No. 6 Patentee after: Shanghai Guao Electronic Machinery Co., Ltd. Address before: 200333 Shanghai city Putuo District Tong Pu Lu Lane 1225 No. 6 Patentee before: Shanghai Guao Electronic Machinery Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100428 Termination date: 20141226 |
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| EXPY | Termination of patent right or utility model |