CN201421840Y - Low-stress chip bump package structure - Google Patents
Low-stress chip bump package structure Download PDFInfo
- Publication number
- CN201421840Y CN201421840Y CN 200920045055 CN200920045055U CN201421840Y CN 201421840 Y CN201421840 Y CN 201421840Y CN 200920045055 CN200920045055 CN 200920045055 CN 200920045055 U CN200920045055 U CN 200920045055U CN 201421840 Y CN201421840 Y CN 201421840Y
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- Prior art keywords
- chip
- stress
- bump
- buffer layer
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The utility model relates to a low-stress chip bump package structure, belonging to chip package the technical field. The structure comprises a chip body (1), a chip electrode (2), a chip surface passivation layer (3), under-bump stress buffer layers (4), a contact electrode (5) and solder bumps (6), wherein the solder bumps (6) are arranged on the stress buffer layer. The low-stress chip bump package structure is characterized in that the under-bump stress buffer layers (4) are separated from each other with discontinuity. The utility model has the beneficial effects that the under-bump stress buffer layers are separated from each other, the stress buffer layers are only arranged below the pump, and the stress buffer layers are discontinuous, therefore, the stress of the whole chip is reduced, the chip stress distribution is dispersed, the reliability performance of the bump structure is improved, the problem of current leakage is improved, and the practicability of the technique processing is improved. Further, the chips with different sizes can use a same mask plate commonly, thereby saving the cost.
Description
(1) technical field
The utility model relates to a kind of low stress chip bump encapsulating structure.Belong to the chip encapsulation technology field.
(2) background technology
In numerous novel chip encapsulation technologies, the tool novelty of Wafer-Level Packaging Technology, caught people's attention most, be that encapsulation technology obtains the revolutionary sign of breaking through.Wafer-Level Packaging Technology is a processing object with the disk, simultaneously numerous chips is encapsulated, wears out, tests on disk, cuts into individual devices at last.It makes package dimension be decreased to the size of IC chip, and production cost descends significantly.The advantage of Wafer-Level Packaging Technology makes one great pay close attention to and obtain rapidly huge development and application widely occur just being subjected to.In portable products such as mobile phone, generally adopt the device such as EPROM, IPD (integrated passive devices), analog chip of wafer level packaging type.Adopt the device class of wafer level packaging to be on the increase, Wafer-Level Packaging Technology is a new technology that is developing rapidly.For the applicability that improves wafer level packaging and enlarge its range of application, people are are researching and developing various new techniques and are solving the problem that occurs in the industrialization process simultaneously, and present situation, application and the development carried out Wafer-Level Packaging Technology are studied.
Wafer level packaging has the advantage of many uniquenesses: 1. encapsulation process efficient height, and it is made with the mass production processes of disk form; 2. the advantage that has Flip-Chip Using is promptly light, thin, short, little; 3. wafer level packaging production facility expense is low, can make full use of the manufacturing equipment of disk, need not invest and build packing producing line in addition; 4. the chip design of wafer level packaging and package design can be unified to consider, carry out simultaneously that this will improve design efficiency, reduce design cost; 5. wafer level packaging from chip manufacturing, be encapsulated into the whole process that product mails to the user, intermediate link significantly reduces, the cycle shortens a lot, this will cause the reduction of cost; 6. the number of chips on the cost of wafer level packaging and each disk is closely related, and the chip-count on the disk is many more, and the cost of wafer level packaging is also low more.Wafer level packaging is the low-cost package of size minimum.Wafer-Level Packaging Technology is a batch process chip encapsulation technology truly.The advantage of wafer level packaging is that it is a kind of more wafer-level package of Small Scale Integration (CSP) technology that is applicable to, owing to adopt parallel encapsulation and Electronic Testing Technology at wafer level, significantly reduces chip area when improving output.Because adopting parallel work-flow to carry out chip at wafer level connects, therefore can reduce the cost of each I/O greatly.In addition, adopt the wafer level test program of simplifying further to reduce cost.Utilize wafer level packaging can realize the packaging and testing of chip at wafer level.
Current most typical wafer level chip bump technology is, adopt PI or BCB as stress-buffer layer, Cu adopts sputtering method deposit salient point bottom metal layers (UBM) as the line metal that distributes again, with planting ball or silk screen print method deposit soldering paste and refluxing, form the soldered ball solder bumps.
The characteristics of bump process all are the coverings of the thin fully stress buffer on the entire chip surface at present, cause allowing the puzzled problem of industry: the one, disk surfaces stress, along with increasing of chip functions, chip size is also in continuous increase, chip surface stress increases the weight of for chip reliability effect in use, and the covering fully of stress-buffer layer, the stress that acts on chip surface can't discharge, and has reduced chip reliability in use; The 2nd, in wafer level packaging technology, the difficult corrosion of metal causes metal residual to have leakage problem easily on the stress-buffer layer; On the other hand, the different chip of chip size must be processed mask plate separately, and processing charges is higher.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and can reduce entire chip stress, improves leakage problem in the technology, cost-effective low stress chip bump encapsulating structure.
The purpose of this utility model is achieved in that a kind of low stress chip bump encapsulating structure, comprise under chip body, chip electrode, chip surface passivation layer, the salient point solder bump on stress-buffer layer, contact electrode and the stress-buffer layer, stress-buffer layer is separated discontinuous mutually under the described salient point.
The beneficial effects of the utility model are:
The utility model is by separating stress-buffer layer under the salient point mutually, only under salient point, stress-buffer layer is arranged, stress-buffer layer is discontinuous, can reduce entire chip stress, the dispersed chip stress distribution has improved the unfailing performance of bump structure, improve leakage problem in the technology, improved the practicality of processes, and the chip of different size can shared same mask plate, save cost.
(4) description of drawings
Fig. 1 is the vertical view of the utility model low stress chip bump encapsulating structure.
Fig. 2 is the A-A cut-away view of Fig. 1.
Among the figure: solder bump 6 on stress-buffer layer 4, contact electrode 5, the stress-buffer layer under chip body 1, chip electrode 2, chip surface passivation layer 3, the salient point.
(5) embodiment
Referring to Fig. 1～2, the utility model low stress chip bump encapsulating structure, comprise under chip body 1, chip electrode 2, chip surface passivation layer 3, the salient point solder bump 6 on stress-buffer layer 4, contact electrode 5 and the stress-buffer layer, stress-buffer layer 4 is separated discontinuous mutually under the described salient point.
Stress-buffer layer 4 is an insulating polymeric material under the described salient point, as polyimides, epoxy resin etc.
Claims (4)
1, a kind of low stress chip bump encapsulating structure, comprise under chip body (1), chip electrode (2), chip surface passivation layer (3), the salient point solder bump (6) on stress-buffer layer (4), contact electrode (5) and the stress-buffer layer, it is characterized in that: stress-buffer layer under the described salient point (4) is separated discontinuous mutually.
2, a kind of low stress chip bump encapsulating structure according to claim 1, it is characterized in that: stress-buffer layer under the described salient point (4) is an insulating polymeric material.
3, a kind of low stress chip bump encapsulating structure according to claim 2, it is characterized in that: described insulating polymeric material is polyimides or epoxy resin.
4, a kind of low stress chip bump encapsulating structure according to claim 1 is characterized in that: solder bump on the described stress-buffer layer (6) comprises the formed salient point of soldered ball and soldering paste backflow back.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920045055 CN201421840Y (en) | 2009-05-26 | 2009-05-26 | Low-stress chip bump package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920045055 CN201421840Y (en) | 2009-05-26 | 2009-05-26 | Low-stress chip bump package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201421840Y true CN201421840Y (en) | 2010-03-10 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200920045055 Expired - Lifetime CN201421840Y (en) | 2009-05-26 | 2009-05-26 | Low-stress chip bump package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201421840Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569232A (en) * | 2012-01-13 | 2012-07-11 | 中国科学院上海微系统与信息技术研究所 | Wafer-level chip size package stress buffering structure |
| CN105047631A (en) * | 2015-08-28 | 2015-11-11 | 江苏纳沛斯半导体有限公司 | Copper-nickel-gold integrated circuit (IC) packaged convex block structure |
| CN109509724A (en) * | 2017-09-15 | 2019-03-22 | 财团法人工业技术研究院 | Semiconductor packaging structure |
-
2009
- 2009-05-26 CN CN 200920045055 patent/CN201421840Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569232A (en) * | 2012-01-13 | 2012-07-11 | 中国科学院上海微系统与信息技术研究所 | Wafer-level chip size package stress buffering structure |
| CN105047631A (en) * | 2015-08-28 | 2015-11-11 | 江苏纳沛斯半导体有限公司 | Copper-nickel-gold integrated circuit (IC) packaged convex block structure |
| CN109509724A (en) * | 2017-09-15 | 2019-03-22 | 财团法人工业技术研究院 | Semiconductor packaging structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100310 |