CN201392828Y - Packaging structure for control chip - Google Patents
Packaging structure for control chip Download PDFInfo
- Publication number
- CN201392828Y CN201392828Y CN200920147554U CN200920147554U CN201392828Y CN 201392828 Y CN201392828 Y CN 201392828Y CN 200920147554 U CN200920147554 U CN 200920147554U CN 200920147554 U CN200920147554 U CN 200920147554U CN 201392828 Y CN201392828 Y CN 201392828Y
- Authority
- CN
- China
- Prior art keywords
- control chip
- pins
- encapsulating structure
- pin
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Abstract
The utility model discloses a packaging structure for a control chip. The packaging structure comprises a leading wire frame, a plurality of pins, the control chip and a package body. The pins comprise a first group of pins and a second group of pins; and the first group of pins is connected with the leading wire frame and comprises at least two pins. The control chip is clung to the leading wire frame and provided with a plurality of contact pads which are correspondingly and electrically connected with the pins. The package body covers the control chip, and at least partially covers the leading wire frame and the pins,, so that part of the pins is exposed outside the package body. Under the condition without increasing the packaging cost, the heat dissipation capability and the packaging density of the packaging structure are effectively improved. The utility model discloses another packaging structure for the control chip provided with at least one opening; when the control chip is packaged with a larger leading wire frame, the packaging structure can reinforce the packaging intensity of the package body and the leading wire frame through the openings.
Description
Technical field
The utility model relates to a kind of encapsulating structure, relates in particular to a kind of encapsulating structure of control chip.
Background technology
Generally speaking, semiconductor manufacture flow path can be divided into the disk manufacturing of FEOL and the encapsulation of last part technology.After chip is finished in the disk manufacturing of process FEOL, then carry out the encapsulation of chip.The function of encapsulation is that the chip circuit with the FEOL manufacturing is connected with external pin and coats, to bring into play the function of chip.The main purpose of encapsulation is the protection chip, avoids contacting with air and the infringement of aqueous vapor; The chip cooling path is provided, avoids chip temperature too high; Provide and transmit the pin of signal and power supply between chip and circuit board and the chip sufficient mechanical strength is provided, make easily crisp chip can carry out subsequent treatment.Common encapsulation kenel has dual in-line package (DIP, Dual Inline Package), little outline packages (SOP, Small OutlinePackage), four side pin flat packaging (QFP, Quad Flat Package), BGA Package (BGA, Ball Grid Array) etc.
The development of electronic product in recent years makes integrated circuit move towards high capacity, miniaturization, high speed.Therefore, encapsulation technology has faced the packaging density that improves on substrate, makes encapsulating structure miniaturization more, slimming, and improves the specification requirement that the requirement of the heat-sinking capability of encapsulating structure greatly improves.
Please refer to Fig. 1, the schematic diagram for the encapsulating structure of the little outline packages (SOP-8) of existing 8 pins comprises packaging body 10, lead frame 20, chip 30 and pin (Lead) #1～8.Chip 30 sticks together on the lead frame 20, by lametta, with the circuit on the chip and lead frame 20 and corresponding pin connection.
The utility model then utilizes the adjustment of lead frame structure and above-mentioned empty pin, under encapsulation board that does not influence encapsulation factory and encapsulation flow process, promptly need not increase under the packaging cost, improves the heat-sinking capability and the packaging density of encapsulating structure effectively.
The utility model content
The utility model utilization has the contact mat that power consumption is bigger in empty pin unnecessary in the encapsulating structure and the control chip now and electrically connects, so the heat energy that this control chip produces makes encapsulating structure that preferable heat-sinking capability be arranged by a plurality of pins heat radiations.
For reaching above-mentioned purpose, the utility model provides a kind of control chip encapsulating structure, it is characterized in that, comprises:
One lead frame;
A plurality of pins, these a plurality of pins comprise one first group of pin and one second group of pin, and this first group of pin is connected and comprises at least two pins with this lead frame;
One control chip is attached to this lead frame, and this control chip has a plurality of contact mats, and wherein these a plurality of contact mats are electrically connected to this a plurality of pins accordingly; And
One packaging body covers this control chip and covers this lead frame and this a plurality of pins to small part, makes these a plurality of pins for partly being exposed to outside this packaging body.
Above-mentioned control chip encapsulating structure, wherein, wherein at least two pins are connected to each other in this second group of pin.
Above-mentioned control chip encapsulating structure, wherein, wherein these at least two pins connected to one another are coupled to an input power supply in this second group of pin.
Above-mentioned control chip encapsulating structure, wherein, wherein this lead frame has at least one perforate.
Above-mentioned control chip encapsulating structure, wherein, wherein these a plurality of pins all electrically connect with this control chip.
Above-mentioned control chip encapsulating structure, wherein, wherein at least one pin has extension area in this second group of pin.
Above-mentioned control chip encapsulating structure, wherein, wherein this lead frame is exposed to outside this packaging body for part.
Above-mentioned control chip encapsulating structure, wherein, wherein this control chip encapsulating structure is little outline packages structure, small outline transistor encapsulating structure or double plane non-leaded package.
Above-mentioned control chip encapsulating structure, wherein, wherein these a plurality of pins all electrically connect with this control chip.
In addition, in order to increase the package strength of packaging body, the utility model also provides a kind of control chip encapsulating structure, it is characterized in that, comprises:
One lead frame has at least one perforate;
A plurality of pins, wherein at least two pins are connected to each other;
One control chip is attached to this lead frame, and this control chip has a plurality of contact mats, and wherein these a plurality of contact mats are electrically connected to this a plurality of pins accordingly; And
One packaging body covers this control chip and covers this lead frame, this at least one perforate and this a plurality of pins to small part, makes these a plurality of pins for partly being exposed to outside this packaging body.
Above-mentioned control chip encapsulating structure, wherein, wherein these a plurality of pins comprise one first group of pin and one second group of pin, and this first group of pin is connected with this lead frame, and this first group of pin comprises at least two pins connected to one another.
Above-mentioned control chip encapsulating structure, wherein, wherein these at least two pins connected to one another in these a plurality of pins are coupled to an input power supply.
Above-mentioned control chip encapsulating structure, wherein, wherein these at least two pins connected to one another in these a plurality of pins are connected with this lead frame.
Above-mentioned control chip encapsulating structure, wherein, wherein at least one pin has extension area in this second group of pin.
Above-mentioned control chip encapsulating structure, wherein, wherein this lead frame is exposed to outside this packaging body for part.
Above-mentioned control chip encapsulating structure, wherein, wherein this control chip encapsulating structure is little outline packages structure, small outline transistor encapsulating structure or double plane non-leaded package.
Above-mentioned control chip encapsulating structure, wherein, wherein these a plurality of pins all electrically connect with this control chip.
So, effect of the present utility model is, utilizes the adjustment and the described empty pin of lead frame structure, under encapsulation board that does not influence encapsulation factory and encapsulation flow process, promptly need not increase under the packaging cost, improves the heat-sinking capability and the packaging density of encapsulating structure effectively.In addition, when control chip needed bigger lead frame to encapsulate, encapsulating structure of the present utility model can be strengthened the package strength of packaging body and lead frame by those perforates, so encapsulating structure of the present utility model can provide preferable packaging density.
Below in conjunction with the drawings and specific embodiments the utility model is described in detail, but not as to qualification of the present utility model.
Description of drawings
Fig. 1 is the schematic diagram of encapsulating structure of the little outline packages (SOP-8) of existing 8 pins;
Fig. 2 A is the control chip encapsulating structure schematic diagram according to one first preferred embodiment of the present utility model;
Fig. 2 B is the control chip encapsulating structure schematic diagram according to one second preferred embodiment of the present utility model;
Fig. 2 C is the generalized section of the encapsulating structure of Fig. 2 B illustrated embodiment;
Fig. 3 is the schematic diagram according to DIP-8 encapsulating structure of the present utility model.
Wherein, Reference numeral
Prior art:
The utility model:
Packaging body 110,210
Lead frame 120,220
Perforate 124,224
Control chip 130,230
Pin PIN1～PIN8, PIN1 '～PIN8 '
Contact mat 132
Contact mat EN
Contact mat VDD
Embodiment
Below in conjunction with accompanying drawing structural principle of the present utility model and operation principle are done concrete description:
Please refer to Fig. 2 A, be control chip encapsulating structure schematic diagram according to one first preferred embodiment of the present utility model.This encapsulating structure comprises packaging body 110, lead frame 120, control chip 130 and pin PIN1～PIN8.Control chip 130 sticks together on the lead frame 120, by lametta, with the contact mat on the control chip 130 with and the electric connection of corresponding pin.Pin PIN4～PIN6 is connected to each other, or optionally is connected with this lead frame 120 those pins PIN4～PIN6 is connected to each other, and other pin PIN1～PIN3, PIN7～PIN8 then separate with this lead frame 120.Control chip 130 is attached on this lead frame 120 by elargol, and this control chip 130 has a plurality of contact mats, and wherein these a plurality of contact mats are electrically connected to those pins PIN1～PIN8 accordingly.This packaging body 110 covers this control chip 130 and this lead frames 120, and covers those pins PIN1～PIN8 to small part, the part of those pins PIN1～PIN8 is exposed to outside this packaging body 110, for being connected with other electronic building brick of outside.
Existing encapsulating structure only dispels the heat by the part pin, and also not good by the effect of packaging body heat radiation, so whole radiating effect and bad.In the present embodiment, one contact mat 132 of this control chip 130 is connected with three pin PIN4～PIN6 simultaneously, therefore compared to existing encapsulating structure, the heat that this control chip 130 is produced can be dispelled the heat by the part that more (or even whole) pin PIN1～PIN8 is exposed to outside this packaging body 110, so preferable radiating effect is arranged.And the contact mat that the big electric current of need can be passed through (for example :) or be connected to pin PIN4～PIN6 connected to one another near the contact mat 132 of hot spot region (being the bigger zone of power consumption) in order to the contact mat that couples ground, in order to the contact mat that couples the input power supply etc., make the path of heat radiation shorter, more can further improve the effect of encapsulating structure heat radiation.
Then please refer to Fig. 2 B, be control chip encapsulating structure schematic diagram according to one second preferred embodiment of the present utility model.This encapsulating structure comprises packaging body 110, lead frame 120, control chip 130 and pin PIN1～PIN8.Compared to the embodiment shown in Fig. 2 A, this lead frame 120 has at least one perforate 124, can increase the area coverage of 120 of 110 pairs of these lead frames of this packaging body by those perforates 124, and the package strength of 120 of this packaging body 110 and this lead frames is increased.When the chip area of this control chip 130 need place larger area lead frame 120 to encapsulate greatly, excessive lead frame 120 can cause the decline of package strength, therefore can promote the package strength of encapsulating structure by these perforates 124, therefore, encapsulating structure of the present utility model can be applied to the encapsulation of bigger control chip compared to existing encapsulating structure.In addition, the pin PIN1～PIN8 of present embodiment can be divided into first group of pin and second group of pin.This first group of pin can comprise at least two pins, the pin PIN4～PIN6 in the present embodiment for example, and be connected with lead frame 120.Second group of pin pin PIN1～PIN3 and PIN7～PIN8 for separating with lead frame 120.And the part pin PIN1～PIN2 of second group of pin is connected to each other, and with this control chip 130 in electrically connect to increase its radiating effect in order to contact mat VDD with the input supply coupling.In addition, the current potential that can also import power supply in order to the contact mat EN of activation is as enable signal, so the activation contact mat EN in the present embodiment also can be electrically connected to pin PIN1～PIN2, so by pin and with reaching good heat radiation.
In addition, compared to the embodiment shown in Fig. 2 A, pin PIN3, the PIN7 of present embodiment have extension area 122, and those extension areas 122 can be in order to increase the area that can go between, so can bear more number of leads, and those extension areas 122 after encapsulation, will be packaged in this packaging body 110 in.
Come again, please refer to Fig. 2 C, be the generalized section of the encapsulating structure of Fig. 2 B illustrated embodiment.The part surface 120A of this lead frame 120 is exposed to outside this dress body 110 of envelope, so, can increase the radiating effect of encapsulating structure by the exposed surface 120A of this lead frame 120.
The foregoing description is the example explanation with the packing forms of SOP, but actual application is not limited thereto, for example: small outline transistor (SOT belongs to a kind of of SOP), double plane do not have pin (DFN, Dual FlatNo-Lead), dual in-line package (DIP) etc. and encapsulate and all can.Below be the example explanation with DFN-8.
Please refer to Fig. 3, be schematic diagram according to DIP-8 encapsulating structure of the present utility model.This encapsulating structure comprises packaging body 210, lead frame 220, control chip 230 and pin PIN1 '～PIN8 '.Lead frame 220 has at least one perforate 224, with the contact area of increase with packaging body 210.Control chip 230 sticks together on the lead frame 220, and by lametta, the pin that the contact mat on the control chip 230 is corresponding with it electrically connects.Pin PIN4 '～PIN6 ' is connected to each other and is connected to lead frame 220 and connects, and other pin PIN1 '～PIN3 ', PIN7 '～PIN8 ' then separates with this lead frame 220, and wherein pin PIN1 ', PIN2 ' also are connected to each other.Control chip 230 is attached on this lead frame 220 by elargol, and this control chip 230 has a plurality of contact mats, and wherein these a plurality of contact mats are electrically connected to those pins PIN1 '～PIN8 ' accordingly.This packaging body 210 covers this control chip 230 and this lead frame 220, and cover those pins PIN1 '～PIN8 ' to small part, the part of those pins PIN1 '～PIN8 ' is exposed to outside this packaging body 210, for being connected with other electronic building brick of outside.
By pin PIN1 ' connected to one another, PIN2 ' and pin PIN4 '～PIN6 ', make whole pin PIN1 '～PIN8 ' not have empty pin and can all be used for the heat radiation.In addition, can increase the area coverage of 120 of 110 pairs of these lead frames of this packaging body by perforate 224, promote the package strength of encapsulating structure, therefore, encapsulating structure of the present utility model can be applied to the encapsulation of bigger control chip compared to existing encapsulating structure.
Certainly; the utility model also can have other various embodiments; under the situation that does not deviate from the utility model spirit and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the utility model.
Claims (17)
1. a control chip encapsulating structure is characterized in that, comprises:
One lead frame;
A plurality of pins, these a plurality of pins comprise one first group of pin and one second group of pin, and this first group of pin is connected and comprises at least two pins with this lead frame;
One control chip is attached to this lead frame, and this control chip has a plurality of contact mats, and wherein these a plurality of contact mats are electrically connected to this a plurality of pins accordingly; And
One packaging body covers this control chip and covers this lead frame and this a plurality of pins to small part, makes these a plurality of pins for partly being exposed to outside this packaging body.
2. control chip encapsulating structure according to claim 1 is characterized in that, wherein at least two pins are connected to each other in this second group of pin.
3. control chip encapsulating structure according to claim 2 is characterized in that, wherein these at least two pins connected to one another are coupled to an input power supply in this second group of pin.
4. control chip encapsulating structure according to claim 1 is characterized in that wherein this lead frame has at least one perforate.
5. control chip encapsulating structure according to claim 1 is characterized in that, wherein these a plurality of pins all electrically connect with this control chip.
6. control chip encapsulating structure according to claim 2 is characterized in that, wherein at least one pin has extension area in this second group of pin.
7. control chip encapsulating structure according to claim 1 is characterized in that, wherein this lead frame is exposed to outside this packaging body for part.
8. control chip encapsulating structure according to claim 1 is characterized in that, wherein this control chip encapsulating structure is little outline packages structure, small outline transistor encapsulating structure or double plane non-leaded package.
9. control chip encapsulating structure according to claim 1 is characterized in that, wherein these a plurality of pins all electrically connect with this control chip.
10. a control chip encapsulating structure is characterized in that, comprises:
One lead frame has at least one perforate;
A plurality of pins, wherein at least two pins are connected to each other;
One control chip is attached to this lead frame, and this control chip has a plurality of contact mats, and wherein these a plurality of contact mats are electrically connected to this a plurality of pins accordingly; And
One packaging body covers this control chip and covers this lead frame, this at least one perforate and this a plurality of pins to small part, makes these a plurality of pins for partly being exposed to outside this packaging body.
11. control chip encapsulating structure according to claim 10, it is characterized in that, wherein these a plurality of pins comprise one first group of pin and one second group of pin, and this first group of pin is connected with this lead frame, and this first group of pin comprises at least two pins connected to one another.
12. control chip encapsulating structure according to claim 11 is characterized in that, wherein these at least two pins connected to one another in these a plurality of pins are coupled to an input power supply.
13. control chip encapsulating structure according to claim 11 is characterized in that, wherein these at least two pins connected to one another in these a plurality of pins are connected with this lead frame.
14. control chip encapsulating structure according to claim 10 is characterized in that, wherein at least one pin has extension area in this second group of pin.
15. control chip encapsulating structure according to claim 10 is characterized in that, wherein this lead frame is exposed to outside this packaging body for part.
16. control chip encapsulating structure according to claim 10 is characterized in that, wherein this control chip encapsulating structure is little outline packages structure, small outline transistor encapsulating structure or double plane non-leaded package.
17. control chip encapsulating structure according to claim 10 is characterized in that, wherein these a plurality of pins all electrically connect with this control chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200920147554U CN201392828Y (en) | 2009-04-03 | 2009-04-03 | Packaging structure for control chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200920147554U CN201392828Y (en) | 2009-04-03 | 2009-04-03 | Packaging structure for control chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201392828Y true CN201392828Y (en) | 2010-01-27 |
Family
ID=41599649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200920147554U Expired - Fee Related CN201392828Y (en) | 2009-04-03 | 2009-04-03 | Packaging structure for control chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201392828Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104766920A (en) * | 2015-01-26 | 2015-07-08 | 广州华微电子有限公司 | SOP8 package lead frame of high-power LED driving chip |
| CN105789167A (en) * | 2016-03-15 | 2016-07-20 | 昂宝电子（上海）有限公司 | Integrated circuit chip packaging device and lead frame |
| CN106611753A (en) * | 2015-10-26 | 2017-05-03 | 无锡华润矽科微电子有限公司 | Chip packaging frame and chip packaging structure |
-
2009
- 2009-04-03 CN CN200920147554U patent/CN201392828Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104766920A (en) * | 2015-01-26 | 2015-07-08 | 广州华微电子有限公司 | SOP8 package lead frame of high-power LED driving chip |
| CN106611753A (en) * | 2015-10-26 | 2017-05-03 | 无锡华润矽科微电子有限公司 | Chip packaging frame and chip packaging structure |
| CN105789167A (en) * | 2016-03-15 | 2016-07-20 | 昂宝电子（上海）有限公司 | Integrated circuit chip packaging device and lead frame |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100127 Termination date: 20140403 |