CN201369789Y - Multiple-path video image acquisition device based on ARM embedded processor - Google Patents
Multiple-path video image acquisition device based on ARM embedded processor Download PDFInfo
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- CN201369789Y CN201369789Y CNU2009201266153U CN200920126615U CN201369789Y CN 201369789 Y CN201369789 Y CN 201369789Y CN U2009201266153 U CNU2009201266153 U CN U2009201266153U CN 200920126615 U CN200920126615 U CN 200920126615U CN 201369789 Y CN201369789 Y CN 201369789Y
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Abstract
The utility model relates to the video image acquisition and processing technology, in particular to a multiple-path video image acquisition device. An embedded processor and FPGA are designed into a multiple-path video image acquisition device, so as to realize real-time acquisition to multiple-path video image signals at the same time. A video acquisition circuit leads video image signals shot by a camera to be input to an A/D converting circuit in a corresponding video acquisition circuit, multiple-path video signals are respectively guided in an FPGA circuit of a main controller, so as to realize real-time processing to video image acquisition, and the processed data is stored in an SDRAM memorizer. The multiple-path video image acquisition device can realize real-time detection and monitoring to actions against rules of motor vehicles in urban road traffic, and realize a multiple-path video image acquisition which has low cost and stable and reliable performances and can be suitable for various complex environments, and can meet application requirements of different video image acquisition.
Description
Technical field
The utility model relates to video image acquisition and treatment technology, is applied to intelligent transportation system ITS (Intelligent Transport System, intelligent transportation system).
Background technology
In the traffic scene the real-time detection of vehicle object be most important in the ITS system also be basic functions, the correctness of detection is directly connected to the correctness of intelligent transportation control and administrative decision.Usually, the vision signal that is collected by gamma camera is analog signal, and it is directly transmitted, stores and handles relatively difficulty.Therefore, analog video signal must be converted to digital signal, just can give full play to strong, the fireballing characteristics of computer process ability, and realize reliable transmission, storage and the processing of video signal in actual applications.Realize IMAQ and processing with hardware, development difficulty is big, cost is high.At present, that most of video images are handled employing is DSP (Digital Signal Processor, digital signal processor) processor, have among the DSP as the C6000 of TI company series specially at multimedia processor, though DSP has very strong image-capable, its cost is unusual costliness also.Use at requiring not to be that strict especially video image is handled,, can select a kind ofly promptly can satisfy the solution that application requirements can farthest reduce cost again from project angle.
Summary of the invention
Technical problem to be solved in the utility model is, in handling, adopts the intelligent transportation system video image dsp processor defect of high cost at prior art, adopt and a kind ofly in engineering is used, use comparatively wide industrial level flush bonding processor AT91RM9200, and cooperate field programmable gate array (FPGA) and SAA7113 video a/d change-over circuit cheaply, designed a kind of multi-channel video picture signal harvester, promptly satisfied the requirement of real time image collection, simultaneously reduce cost again, realized the application requirements of multi-channel video IMAQ.
The following technical scheme of the concrete employing of the utility model: adopt the master controller of AT91RM9200 flush bonding processor and FPGA channeling video image acquisition device, realize simultaneously the multi-channel video picture signal being gathered in real time.The multiway images video acquisition device comprises: flush bonding processor AT91RM9200, master controller FPGA, video capture circuit SAA7113, RCA converting interface, gate FPGA (95144XL), SDRAM (Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory), video camera.Video camera links to each other with video capture circuit by the RCA converting interface, the video signal source of camera acquisition is input to carries out the A/D conversion in the corresponding video capture circuit, the video signal source can be that CCD (Charge Couple Device, charge coupled device) video camera also can be other video image sensors or analog video signal source.Video signal is CVBS (CompositeVideo Broadcast Signal, a composite video broadcast singal) analog signal.A/D change-over circuit in the video capture circuit is finished the conversion of CVBS video analog signal to digital signal.The output of a plurality of video capture circuits connects gate FPGA, and the output of gate FPGA connects master controller FPGA input.Master controller FPGA is with I
2C (Inter-Integrated Circuit, internal integrated circuit) mode disposes video capture processor SAA7113, and the video data format that makes its output is (4:2:2) form of YUV (YCrCb, brightness and aberration); Then, again multi-channel video signal is carried out multiselect one control, and respectively the video data of exporting is imported among the master controller FPGA, master controller FPGA realizes the real-time processing to vedio data, the storage after will being handled by flush bonding processor is in the SDRAM memory.Master controller FPGA by flush bonding processor to be configured from string mode, employing can realize multi-channel video IMAQ and the application requirements that satisfies various different video image real-time acquisitions based on the Control Software and the bsp driver interface of flush type LINUX operating system.
This device is a kind of multi-channel video image-pickup method and the device based on ARM (Advanced RISC Machine) flush bonding processor that designs for the act of violating regulations that detects and monitor motor vehicles in the urban highway traffic scene in real time.From the angle of practical engineering application, promptly can satisfy the requirement of urban highway traffic on-site supervision, can farthest reduce cost again.
Description of drawings
Fig. 1 is the system principle diagram of multi-channel video harvester
Fig. 2 is the video image acquisition circuit connection diagram
Fig. 3 is to dispose FPGA interface circuit figure from string mode
Fig. 4 is from string mode configuration FPGA flow chart
Fig. 5 is a vedio data capture program flow chart
Embodiment
Followingly enforcement of the present utility model is specifically described with reference to accompanying drawing and instantiation:
Fig. 1 is the system principle diagram based on the multi-channel video harvester of ARM flush bonding processor.This multiway images video acquisition device comprises: ARM flush bonding processor AT91RM9200, programmable array master controller FPGA (XC2S100), video image acquisition circuit SAA7113, RCA converting interface, gate FPGA (95144XL), SDRAM memory, video camera, serial line interface UART, network interface NET, adopt Control Software and bsp driver interface based on flush type LINUX operating system.
Video camera links to each other with video capture circuit by the RCA converting interface, the video signal source of its collection is input to finishes the CVBS video analog signal in the corresponding SAA7113 video capture circuit and change to the A/D of digital signal, by master controller FPGA with I
2The C mode disposes video capture circuit SAA7113, and the video data format that makes its output is YUV (4:2:2) form; The output of a plurality of video capture circuits (SAA7113) is connected to gate FPGA, and gate FPGA carries out multiselect one control to multi-channel video signal, and the multi-channel video acquired signal is sent into respectively among the master controller FPGA; Master controller FPGA to be configured from string mode, realizes the real-time processing to the multi-channel video view data by flush bonding processor (AT91RM9200); At last, the storage after will being handled by flush bonding processor is in memory storage SDRAM; Employing realizes multi-channel video IMAQ and the application requirements that satisfies various different video IMAQs based on the Control Software and the bsp driver interface of flush type LINUX operating system.
As master controller, built-in Linux is as operating system with flush bonding processor (AT91RM9200) and FPGA (XC2S100) for this device.After the system start-up, dispose master controller FPGA and video capture circuit automatically, flush bonding processor obtains view data by the video acquisition driver from master controller FPGA, and view data is handled, and finally obtains the DID of high-quality.
Fig. 2 is the video image acquisition circuit connection diagram.I
2The C bus is the universal serial bus that is made of data/address bus SDA and clock SCL, can transmit and receive data.During initialization, video capture circuit SAA7113 passes through I
2The C bus is configured its internal register.Two ports of data/address bus SDA and clock SCL are connected to two I/O mouths of XC2S100.The data of the 8bit of video signal output pin VP7-VPO select 1 circuit to be sent to 8 I/O mouths of master controller fpga chip by 4, and finish the parallel transmission of vedio data, master controller FPGA can adopt from string, main string, from also, main also, the JTAG isotype is configured it.This device adopts and from string mode master controller FPGA is configured, and (PB14～PB18) simulation is configured from string pattern to use the PIO mouth by flush bonding processor.
Fig. 3 is with the interface circuit figure from string mode configuration master controller FPGA (XC2S100).
In this circuit connection diagram, main pin function is as follows:
M[2:0]: configuration mode is selected.Port M2, M1, M0 all connect and draw resistance, i.e. M[2:0]: being provided with 111 is from string pattern; CCLK: configurable clock generator port: microprocessor PB14 port provides the clock source by this CCLK to FPGA circuit (XC2S100), and is effective at rising edge; DIN: the series arrangement data-in port connects microprocessor port PB17; DOUT: the serial data output port is used for daisy-chained configuration; PROG_B: connect microprocessor port PB18, low level asynchronous reset FPGA internal logic, inner configurable, after Memory resetted fully, this pin indication high level when this pin when being high, could dispose FPGA; INIT_B: connect microprocessor port PB15, during to the high level saltus step, configuration mode, i.e. M[2:0 sample by low level] value determine configuration mode; If configuration error occurs, INIT_B will present low level in the layoutprocedure; DONE: connect microprocessor port PB16: be low level when resetting, if configuration successful then is a high level.Port PROG_B, INIT_B, DONE connect pull-up resistor.
Fig. 4 is for realizing the flow chart of configuration master controller FPGA (XC2S100).
Put PROG_B=1, put PROG_B=0, judge whether INIT_B equals 1, as be not equal to 1, return and continue to judge, as equal 1, get the configuration data parallel seriesization to DIN, if data have been got, judge that whether DONE is 1, then disposes as DONE=1 and finishes, otherwise reconfigure.
Fig. 5 is vedio data collecting flowchart figure.
Under (SuSE) Linux OS, the collecting flowchart of vedio data is as follows: the driver of gathering vedio data stream is added in the linux kernel, processor controls obtains view data by device driver control of video Acquisition Circuit, and device drives is called SAA7113.At first, establishment N (N=1,2 ..., 16) and individual new file; Open N device driver; The size definition of filebuf (buffer) is: the 352*288*2 byte; From drive file, read 352*288*2 byte data, the data among the buffer are written in N the new file of creating to buffer.Reads image data from the SDRAM of XC2S100FPGA, the data that read are YUV values of video image YUV (4:2:2) form.Therefore, a width of cloth resolution is that the image data amount of 352*288 is the 352*288*2 byte.Like this, cooperate hardware circuit just to realize real-time collection based on the vedio data acquisition controlling software of ARM flush bonding processor to vedio data.
This device is that the act of violating regulations for motor vehicles in the urban highway traffic detects and monitor a kind of multi-channel video image collecting device based on the ARM flush bonding processor that designs in real time, realize with low cost, stable performance, reliable can realize multi-channel video IMAQ and the application requirements that satisfies various different video IMAQs.
Claims (3)
1, based on the multi-channel video image collecting device of ARM flush bonding processor, comprise: flush bonding processor AT91RM9200, master controller FPGA XC2S100, video capture circuit SAA7113, RCA converting interface, memory, gate FPGA 95144XL, it is characterized in that, camera acquisition video signal source, be input to corresponding video capture circuit by the RCA converting interface, and finish the A/D conversion; The output of a plurality of video capture circuits connects gate, and the output of gate connects the input of master controller FPGA; Flush bonding processor passes through master controller FPGA with I
2C bus mode configuration video capture circuit, the video data format that makes its output is a yuv format, gate carries out multiselect one control to multi-channel video signal, and the vision signal with output imports among the master controller FPGA respectively, realizes the real-time processing to the video signal image data; At last, the storage after will being handled by flush bonding processor is in SDRAM.
2, multi-channel video image collecting device according to claim 1 is characterized in that I
2The data/address bus port of C bus and clock port are connected respectively to the input/output end port of master controller FPGA XC2S100, and the data of video capture circuit output select 1 circuit to be sent to the input/output end port of master controller FPGA by 4.
3, multi-channel video image collecting device according to claim 1 is characterized in that, described master controller FPGA port M2, M1, M0 all connect and draw resistance, are configured to from string mode by flush bonding processor.
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2009201266153U CN201369789Y (en) | 2009-03-13 | 2009-03-13 | Multiple-path video image acquisition device based on ARM embedded processor |
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| CNU2009201266153U CN201369789Y (en) | 2009-03-13 | 2009-03-13 | Multiple-path video image acquisition device based on ARM embedded processor |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103974040A (en) * | 2014-05-09 | 2014-08-06 | 哈尔滨水星电子科技有限公司 | Panoramic digital image sensor with shared interface and establishing method |
| CN104129336A (en) * | 2014-08-25 | 2014-11-05 | 国家电网公司 | Reminding device based on FPGA (Field Programmable Gate Array) for recognizing change of traffic light |
| CN104243931A (en) * | 2014-09-29 | 2014-12-24 | 唐子贤 | ARM (random access memory) camera interface based video collection displaying system |
| CN104461428A (en) * | 2014-12-04 | 2015-03-25 | 四川川大智胜软件股份有限公司 | Multi-channel DVI (digital Visual Interface) image fusion correction control host |
| CN107370975A (en) * | 2016-05-12 | 2017-11-21 | 北京同步科技有限公司 | Multichannel dynamic recording system and method |
| CN108162977A (en) * | 2017-11-25 | 2018-06-15 | 深圳市元征科技股份有限公司 | Driving assistance system and control method |
| CN112055151A (en) * | 2019-06-06 | 2020-12-08 | Tcl新技术（惠州）有限公司 | Law enforcement instrument mode switching method and system and readable storage medium |
-
2009
- 2009-03-13 CN CNU2009201266153U patent/CN201369789Y/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103974040A (en) * | 2014-05-09 | 2014-08-06 | 哈尔滨水星电子科技有限公司 | Panoramic digital image sensor with shared interface and establishing method |
| CN104129336A (en) * | 2014-08-25 | 2014-11-05 | 国家电网公司 | Reminding device based on FPGA (Field Programmable Gate Array) for recognizing change of traffic light |
| CN104243931A (en) * | 2014-09-29 | 2014-12-24 | 唐子贤 | ARM (random access memory) camera interface based video collection displaying system |
| CN104461428A (en) * | 2014-12-04 | 2015-03-25 | 四川川大智胜软件股份有限公司 | Multi-channel DVI (digital Visual Interface) image fusion correction control host |
| CN104461428B (en) * | 2014-12-04 | 2017-08-01 | 四川川大智胜软件股份有限公司 | Multichannel DVI image co-registration Corrective control main frames |
| CN107370975A (en) * | 2016-05-12 | 2017-11-21 | 北京同步科技有限公司 | Multichannel dynamic recording system and method |
| CN108162977A (en) * | 2017-11-25 | 2018-06-15 | 深圳市元征科技股份有限公司 | Driving assistance system and control method |
| CN112055151A (en) * | 2019-06-06 | 2020-12-08 | Tcl新技术（惠州）有限公司 | Law enforcement instrument mode switching method and system and readable storage medium |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091223 Termination date: 20140313 |