CN201348649Y - PCB testing circuit - Google Patents

PCB testing circuit Download PDF

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Publication number
CN201348649Y
CN201348649Y CNU2009201136130U CN200920113613U CN201348649Y CN 201348649 Y CN201348649 Y CN 201348649Y CN U2009201136130 U CNU2009201136130 U CN U2009201136130U CN 200920113613 U CN200920113613 U CN 200920113613U CN 201348649 Y CN201348649 Y CN 201348649Y
Authority
CN
China
Prior art keywords
power supply
electric capacity
pcb board
utility
model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNU2009201136130U
Other languages
Chinese (zh)
Inventor
张文军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CNU2009201136130U priority Critical patent/CN201348649Y/en
Application granted granted Critical
Publication of CN201348649Y publication Critical patent/CN201348649Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model discloses a PCB testing circuit, which includes a power supply, a capacitor and two testing terminals; one end of the power supply is connected with one end of the capacitor; the other end of the capacitor is connected with one testing terminal; the other end of the power supply is connected with the other testing terminal; and the two testing terminals are connected with two ends of an element on a PCB. The testing precision can be improved.

Description

A kind of pcb board test circuit
Technical field
The utility model relates to a kind of pcb board test circuit.
Background technology
The pcb board test, the internal resistance of element under test is not of uniform size, and for the bigger element of internal resistance, measuring accuracy guarantees that easily the element that internal resistance is less is difficult to guarantee measuring accuracy.
The utility model content
The purpose of this utility model is to provide a kind of pcb board test circuit, improves measuring accuracy.
The utility model provides a kind of pcb board test circuit, comprise power supply, electric capacity and two calibrating terminals, one end of described power supply links to each other with an end of electric capacity, the other end of described electric capacity links to each other with a calibrating terminal, the other end of described power supply links to each other with another calibrating terminal, and described two calibrating terminals link to each other with element two ends on the pcb board respectively.
Description of drawings
Fig. 1 is the structural representation of the utility model pcb board test circuit.
Embodiment
Below in conjunction with accompanying drawing the embodiment of the utility model embodiment is done further and to be elaborated.
See also Fig. 1, a kind of pcb board test circuit, comprise power supply 1, electric capacity 2 and two calibrating terminals 3,4, one end of power supply 1 links to each other with an end of electric capacity 2, the other end of electric capacity 2 links to each other with a calibrating terminal 3, the other end of power supply 1 links to each other with another calibrating terminal 4, and two calibrating terminals link to each other with element two ends on the pcb board respectively.
Element internal resistance on pcb board hour, electric capacity plays the effect of current buffering to element; On the other hand, electric capacity is high-impedance component, can improve the measuring accuracy of internal resistance than small components.
It will be appreciated by those skilled in the art that accompanying drawing is the synoptic diagram of a preferred embodiment, the module in the accompanying drawing might not be that enforcement the utility model is necessary.It will be appreciated by those skilled in the art that the module in the device among the embodiment can be distributed in the device of embodiment according to the embodiment description, also can carry out respective change and be arranged in the one or more devices that are different from present embodiment.The module of the foregoing description can be merged into a module, also can further split into a plurality of submodules.
The above only is an embodiment of the present utility model; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.

Claims (1)

1, a kind of pcb board test circuit, it is characterized in that, comprise power supply, electric capacity and two calibrating terminals, one end of described power supply links to each other with an end of electric capacity, the other end of described electric capacity links to each other with a calibrating terminal, the other end of described power supply links to each other with another calibrating terminal, and described two calibrating terminals link to each other with element two ends on the pcb board respectively.
CNU2009201136130U 2009-02-10 2009-02-10 PCB testing circuit Expired - Fee Related CN201348649Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2009201136130U CN201348649Y (en) 2009-02-10 2009-02-10 PCB testing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2009201136130U CN201348649Y (en) 2009-02-10 2009-02-10 PCB testing circuit

Publications (1)

Publication Number Publication Date
CN201348649Y true CN201348649Y (en) 2009-11-18

Family

ID=41368117

Family Applications (1)

Application Number Title Priority Date Filing Date
CNU2009201136130U Expired - Fee Related CN201348649Y (en) 2009-02-10 2009-02-10 PCB testing circuit

Country Status (1)

Country Link
CN (1) CN201348649Y (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091118

Termination date: 20120210