CN201319594Y - Communication network power equalizer - Google Patents
Communication network power equalizer Download PDFInfo
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- CN201319594Y CN201319594Y CNU2008201618529U CN200820161852U CN201319594Y CN 201319594 Y CN201319594 Y CN 201319594Y CN U2008201618529 U CNU2008201618529 U CN U2008201618529U CN 200820161852 U CN200820161852 U CN 200820161852U CN 201319594 Y CN201319594 Y CN 201319594Y
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Abstract
The utility model discloses a communication network power equalizer, wherein the product adopts a micro-strip form, the basic principle of a duplexer and the topological structure, therefore, the power of radio-frequency signals in different frequencies can be adjusted, so that the output signals can achieve the power balance state. The power equalizer has the main characteristics of low cost, less loss, small volume, light weight and simple use, which solves the problem that powers are different when different systems reaches an antenna in the network optimization.
Description
Technical field
The utility model relates to a kind of communication network power equalizer, belongs to network optimization product, specifically is the radiofrequency signal of different frequency is carried out power adjustments, makes output signal reach the device of power-balance state.
Background technology
Existing communication network optimize project, when doing the signal covering, because in order to save cost and to reduce the space, the unlike signal system transmissions tends to use mixer, makes multiple signals merge into one road signal and transmits, but because different system signal, frequency differs greatly, in transmission course loss different, cause when arriving the antenna transmitting terminal, power difference is excessive, and signal is disturbed.Present stage and since the C net incorporate into telecommunications all, telecommunications is being strengthened the network optimization, power is excessive then to the interference maximum of C net system, so need a kind of device regulate power.
Summary of the invention
In order to solve the problem that the unlike signal transmitting power differs greatly more easily, the utility model provides a kind of communication network power equalizer that adopts little band forms, its utilization duplexer basic principle, and employing topological structure, can carry out power adjustments to the radiofrequency signal of different frequency, make output signal reach the state of power-balance.
In order to solve the utility model product technology problem, adopt following scheme:
The utility model product adopts half lumped circuit, according to specification requirement, realizes the effect of communication network power equalizer in conjunction with the topological structure of duplexer design principle and practicality.
It mainly comprises the microwave board that the circuit elements device is installed, and the circuit on the microwave board constitutes: port Port1 and microstrip line TRL1 link; Microstrip line TRL1 is divided into two-way,
One tunnel elder generation and air core coil L6 parallel with one another, interdigital capacitor C01 connects, connect microstrip line TRL3 afterwards successively, air core coil L5, microstrip line TRL4, Chip-R R1, microstrip line TRL5, air core coil L1 and microstrip line TRL6, connect air core coil L2 parallel with one another and interdigital capacitor C02 again, air core coil L6 in parallel connection, pass through SMD patch capacitor C11 ground connection between interdigital capacitor C01 and the microstrip line TRL3, between air core coil L5 and microstrip line TRL4, pass through SMD patch capacitor C10 ground connection, between microstrip line TRL4 and Chip-R R1, pass through Chip-R R2 ground connection, between Chip-R R1 and microstrip line TRL5, pass through Chip-R R3 ground connection, at microstrip line TRL5, between the air core coil L1 by SMD patch capacitor C1 ground connection, between microstrip line TRL6 and air core coil L2 parallel with one another and interdigital capacitor C02 by SMD patch capacitor C3 ground connection;
Another road connects SMD patch capacitor C12 successively, microstrip line TRL7, SMD patch capacitor C15, microstrip line TRL8, SMD patch capacitor C13, microstrip line TRL10, SMD patch capacitor C4, microstrip line TRL12, SMD patch capacitor C6, microstrip line TRL13, SMD patch capacitor C8, between SMD patch capacitor C12 and microstrip line TRL7, pass through air core coil L8 and SMD patch capacitor C14 ground connection, between SMD patch capacitor C15 and microstrip line TRL8, pass through air core coil L7 and SMD patch capacitor C16 ground connection, microstrip line TRL9 in parallel between SMD patch capacitor C13 and the microstrip line TRL10, microstrip line TRL11 in parallel between microstrip line TRL10 and SMD patch capacitor C4, at microstrip line TRL12, by air core coil L3 and SMD patch capacitor C5 ground connection, between microstrip line TRL13 and SMD patch capacitor C8, pass through air core coil L4 and SMD patch capacitor C7 ground connection between the SMD patch capacitor C6;
Two-way merges the back and is connected with microstrip line TRL2; Microstrip line TRL2 is connected with port Port2.
The operation principle of the utility model product is: input signal enters a mixer from a port earlier, is divided into two paths of signals, and one tunnel frequency is 400-960MHz, and one tunnel frequency is 1700-2500MHz.Frequency be 400-960MHz this on the way, again by ∏ type attenuator, carry out power adjustments, and then and frequency be that the road signal of 1700-2500MHz enters another mixer, signal merges the back and exports from the another port.Because in whole system, the signal transmission attenuation in the 1700-2500MHz frequency is greater than signal in the 400-960MHz frequency, reaches the 400-960MHz signal of decaying with the utility model product, thereby reaches the effect of two paths of signals balance.Wherein two mixer principles are the same, can regard two filters as, first mixer is when signal is imported, signal can walk abreast simultaneously by two filters, make the signal of one tunnel output, 400 ~ 960MHz, wherein loss power is no more than 0.5dB, and 1700 ~ 2500MHz signal power loss of output surpasses 30dB; The signal of another road output 1700 ~ 3500MHz, wherein loss power is no more than 0.5dB, and 400 ~ 960MHz signal power loss of output surpasses 30dB, thereby reaches the effect of separation signal.Then a mixer is then opposite with first mixer effect, composition from after signal, remerging is one tunnel output.
The utility model product is little, in light weight except inserting loss, and is beyond volume is little, because decay scalable, replacing when carrying out network optimization distribution, significantly reduce the unbalanced problem of power in actual engineering, easy to use flexible.
Description of drawings
Fig. 1 is circuit theory diagrams of the present utility model;
Fig. 2 is a fundamental block diagram of the present utility model;
Fig. 3 is certainly around inductance profile figure;
Embodiment
The utility model product adopts half lumped circuit, according to specification requirement, realizes the effect of communication network power equalizer in conjunction with the topological structure of duplexer design principle and practicality.As shown in Figure 1, comprise two ports, a port Port1 (1), a port Port2 (2).One of them port Port1 (1) and microstrip line TRL1 (3) link; Microstrip line TRL1 (3) is divided into two-way, and one the tunnel is connected with air core coil L6 (5), interdigital capacitor C01 (4), and one the tunnel is connected with SMD patch capacitor C12 (21); Wherein one road air core coil L6 (5), interdigital capacitor C01 (4) are connected with SMD patch capacitor C11 (6), microstrip line TRL3 (7); Microstrip line TRL3 (7) is connected with air core coil L5 (8); Air core coil L5 (8) is connected with SMD patch capacitor C10 (9), microstrip line TRL4 (10); Microstrip line TRL4 (10) is connected with Chip-R R2 (11), Chip-R R1 (12); Chip-R R1 (12) is connected with Chip-R R3 (13), microstrip line TRL5 (14); Microstrip line TRL5 (14) is connected with SMD patch capacitor C1 (15), air core coil L1 (16); Air core coil L1 (16) is connected with microstrip line TRL6 (17); Microstrip line TRL6 (17) is connected with SMD patch capacitor C3 (18), air core coil L2 (19), interdigital capacitor C02 (20); Wherein SMD patch capacitor C11 (6), C10 (9), C1 (15), C3 (18) all join with printed board ground with the other end of Chip-R R2 (11), R3 (13).Another road SMD patch capacitor C12 (21) is connected with microstrip line TRL7 (24), air core coil L8 (22); Air core coil L8 (22) is connected with SMD patch capacitor C14 (23); Microstrip line TRL7 (24) is connected with SMD patch capacitor C15 (25); SMD patch capacitor C15 (25) is connected with microstrip line TRL8 (28), air core coil L7 (26); Air core coil L7 (26) is connected with SMD patch capacitor C16 (27); Microstrip line TRL8 (28) is connected with SMD patch capacitor C13 (29); SMD patch capacitor C13 (29) is connected with microstrip line TRL9 (30), microstrip line TRL10 (31); Microstrip line TRL10 (31) is connected with microstrip line TRL11 (32), SMD patch capacitor C4 (33); SMD patch capacitor C4 (33) is connected with microstrip line TRL12 (34); Microstrip line TRL12 (34) is connected with air core coil L3 (35), SMD patch capacitor C6 (37); Air core coil L3 (35) and SMD patch capacitor C5 (36); SMD patch capacitor C6 (37) is connected with microstrip line TRL13 (38); Microstrip line TRL13 (38) is connected with air core coil L4 (39), SMD patch capacitor C8 (41); Air core coil L4 (39) is connected with SMD patch capacitor C7 (40); The air core coil L2 (19) of the SMD patch capacitor C8 (41) and the first via, interdigital capacitor C02 (20) merge the back and are connected with microstrip line TRL2 (42); Microstrip line TRL2 (42) is connected with port Port2 (2).Wherein the other end of SMD patch capacitor C14 (23), C16 (27), C5 (36), C7 (40) all joins with printed board ground.
The operation principle of the utility model product is: input signal enters a mixer from a port Port1 (1) or Port2 (2) earlier, is divided into two paths of signals, and one tunnel frequency is 400-960MHz, and one tunnel frequency is 1700-2500MHz.Frequency be 400-960MHz this on the way, again by ∏ type attenuator, carry out power adjustments, and then and frequency be that the road signal of 1700-2500MHz enters another mixer, signal merges the back from another port output Port2 (2) or Port1 (1).Because in whole system, the signal transmission attenuation in the 1700-2500MHz frequency is greater than signal in the 400-960MHz frequency, reaches the 400-960MHz signal of decaying with the utility model product, thereby reaches the effect of two paths of signals balance.Wherein two mixer principles are the same, can regard two filters as, first mixer is when signal is imported, signal can walk abreast simultaneously by two filters, make the signal of one tunnel output, 400 ~ 960MHz, wherein loss power is no more than 0.5dB, and 1700 ~ 2500MHz signal power loss of output surpasses 30dB; The signal of another road output 1700 ~ 3500MHz, wherein loss power is no more than 0.5dB, and 400 ~ 960MHz signal power loss of output surpasses 30dB, thereby reaches the effect of separation signal.Then a mixer is then opposite with first mixer effect, composition from after signal, remerging is one tunnel output.See Fig. 2.
When the utility model product used in example, the thick dielectric constant of microwave board employing F4B-2 type 1mm was 2.55 copper coated foil plate.SMD patch capacitor C1 (15), C3 (18), C4 (33), C5 (36), C6 (37), C7 (40), C8 (41), C10 (9), C11 (6), C12 (21), C13 (29), C14 (23), C15 (25), C16 (27) appearance value are respectively 2.2PF, 3.3PF, 1.8PF, 4PF, 1.5PF, 2.4PF, 2.7PF, 2.2PF, 3.3PF, 1.8PF, 2.7PF, 2.4PF, 1.5PF, 4PF.Interdigital capacitor C01 (4), the interdigital number of C02 (20) are 4, refer to that the long 3mm of being, finger beam are that 0.3mm, finger gap 0.3mm, Interdigital Space are 0.3mm.Air core coil L1 (16), L2 (19), L3 (35), L4 (39), L5 (39), L4 (8), L6 (5), L7 (26), L8 (22) are the winding by hand inductance
The diameter of seeing Fig. 3 inductance is D, and length is L, and the number of turn is N, and diameter of wire is d.(unit: millimeter)
L1(16)、L5(39)：D＝1.5 L＝2.7 N＝3 d＝0.5
L2(10)、L6(5)：D＝1.5 L＝3 N＝3 d＝0.5
L3(16)、L7(26)：D＝1.5 L＝1.5 N＝2 d＝0.5
L4(21)、L8(22)：D＝1.5 L＝2.8 N＝3 d＝0.5
Microstrip line TRL1 (3), TRL2 (42) long for 8mm, wide be 2mm, TRL3 (7) is that one section line is divided into two sections parallel lines, one section line length is 2.5mm, widely is 1.7mm, two sections parallel line lengths be 3.5mm, wide be 1mm, the 1.7mm of being separated by.Microstrip line TRL4 (10), the wide 2mm of TRL5 (14), long be 3.5mm, TRL6 (17) is that two sections parallel lines are merged into one section line, two sections parallel line lengths be 3.5mm, wide for 1mm, the 1.7mm of being separated by, intersect the back long for 2.5mm, widely be 1.7mm.TRL7 (24), TRL13 (38) long for 2.5mm, wide be 2.5mm.TRL8 (28), TRL12 (34) long for 2.5mm, wide be 1.8mm.TRL9 (30), TRL11 (32) are made up of two joints respectively, and be long for 1.8mm, wide microstrip line for 1.8mm are 0.4mm, wide for the microstrip line of 1.2mm is connected to main line TRL10 (31) by length, length be 11mm, wide be 1.2mm.
Whole microwave board is screwed on metallic cavity, profile such as Fig. 4.
1 is cavity; 2 is cover plate; 3 is microwave board; 4 is two hole flange SMA-Female joints; 5 is the sunk screw of M2.5*6; 6 is the button-headed screw of M2*4; 7 is the installing hole of R3.The joint core of two two hole flange SMA-Female joints is 0.5mm above microwave board all, and welds together with scolding tin.
The small and exquisite practical cost of whole profile is low, and through handling, makes cavity not have wedge angle, and is safe and reliable.According to optimizing Principles of Network, the index of the utility model product is:
Claims (4)
1, a kind of communication network power equalizer comprises the microwave board that the circuit elements device is installed, and it is characterized in that the circuit on the microwave board constitutes: port Port1 (1) and microstrip line TRL1 (3) link; Microstrip line TRL1 (3) is divided into two-way,
One tunnel elder generation and air core coil L6 (5) parallel with one another, interdigital capacitor C01 (4) connects, connect microstrip line TRL3 (7) afterwards successively, air core coil L5 (8), microstrip line TRL4 (10), Chip-R R1 (12), microstrip line TRL5 (14), air core coil L1 (16) and microstrip line TRL6 (17), connect air core coil L2 (19) parallel with one another and interdigital capacitor C02 (20) again, air core coil L6 (5) in parallel connection, pass through SMD patch capacitor C11 (6) ground connection between interdigital capacitor C01 (4) and the microstrip line TRL3 (7), between air core coil L5 (8) and microstrip line TRL4 (10), pass through SMD patch capacitor C10 (9) ground connection, between microstrip line TRL4 (10) and Chip-R R1 (12), pass through Chip-R R2 (11) ground connection, between Chip-R R1 (12) and microstrip line TRL5 (14), pass through Chip-R R3 (13) ground connection, in microstrip line TRL5 (14), by SMD patch capacitor C1 (15) ground connection, between microstrip line TRL6 (17) and air core coil L2 (19) parallel with one another and interdigital capacitor C02 (20), pass through SMD patch capacitor C3 (18) ground connection between the air core coil L1 (16);
Another road connects SMD patch capacitor C12 (21) successively, microstrip line TRL7 (24), SMD patch capacitor C15 (25), microstrip line TRL8 (28), SMD patch capacitor C13 (29), microstrip line TRL10 (31), SMD patch capacitor C4 (33), microstrip line TRL12 (34), SMD patch capacitor C6 (37), microstrip line TRL13 (38), SMD patch capacitor C8 (41), between SMD patch capacitor C12 (21) and microstrip line TRL7 (24), pass through air core coil L8 (22) and SMD patch capacitor C14 (23) ground connection, between SMD patch capacitor C15 (25) and microstrip line TRL8 (28), pass through air core coil L7 (26) and SMD patch capacitor C16 (27) ground connection, microstrip line TRL9 in parallel (30) between SMD patch capacitor C13 (29) and the microstrip line TRL10 (31), microstrip line TRL11 in parallel (32) between microstrip line TRL10 (31) and SMD patch capacitor C4 (33), in microstrip line TRL12 (34), by air core coil L3 (35) and SMD patch capacitor C5 (36) ground connection, between microstrip line TRL13 (38) and SMD patch capacitor C8 (41), pass through air core coil L4 (39) and SMD patch capacitor C7 (40) ground connection between the SMD patch capacitor C6 (37);
Two-way merges the back and is connected with microstrip line TRL2 (42); Microstrip line TRL2 (42) is connected with port Port2 (2).
2, communication network power equalizer according to claim 1 is characterized in that: the thick dielectric constant of microwave board employing F4B-2 type 1mm is 2.55 copper coated foil plate; SMD patch capacitor C1, C3, C4, C5, C6, C7, C8, C10, C11, C12, C13, C14, C15, C16 appearance value are respectively 2.2PF, 3.3PF, 1.8PF, 4PF, 1.5PF, 2.4PF, 2.7PF, 2.2PF, 3.3PF, 1.8PF, 2.7PF, 2.4PF, 1.5PF, 4PF; The interdigital number of interdigital capacitor C01, C02 is 4, refers to that the long 3mm of being, finger beam are that 0.3mm, finger gap 0.3mm, Interdigital Space are 0.3mm.
3, communication network power equalizer according to claim 1 and 2 is characterized in that: the diameter of air core coil is D, and length is L, and the number of turn is N, and diameter of wire is d, and unit is a millimeter, wherein:
L1、L5：D＝1.5 L＝2.7 N＝3 d＝0.5
L2、L6：D＝1.5 L＝3 N＝3 d＝0.5
L3、L7：D＝1.5 L＝1.5 N＝2 d＝0.5
L4、L8：D＝1.5 L＝2.8 N＝3 d＝0.5。
4, communication network power equalizer according to claim 1 and 2 is characterized in that:
Microstrip line TRL1, TRL2 long for 8mm, wide be 2mm;
Microstrip line TRL3 is that one section line is divided into two sections parallel lines, and one section line length is 2.5mm, widely is 1.7mm, and two sections parallel line lengths are 3.5mm, widely are 1mm, the 1.7mm of being separated by;
The wide 2mm of microstrip line TRL4, TRL5, length are 3.5mm;
Microstrip line TRL6 is that two sections parallel lines are merged into one section line, two sections parallel line lengths be 3.5mm, wide for 1mm, the 1.7mm of being separated by, intersect the back long for 2.5mm, widely be 1.7mm;
Microstrip line TRL7, TRL13 long for 2.5mm, wide be 2.5mm.TRL8, TRL12 long for 2.5mm, wide be 1.8mm;
Microstrip line TRL9, TRL11 are made up of two joints respectively, and be long for 1.8mm, wide microstrip line for 1.8mm are 0.4mm, wide for the microstrip line of 1.2mm is connected to main line TRL10 by length,
The microstrip line TRL10 of main line long for 11mm, wide be 1.2mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201618529U CN201319594Y (en) | 2008-10-23 | 2008-10-23 | Communication network power equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201618529U CN201319594Y (en) | 2008-10-23 | 2008-10-23 | Communication network power equalizer |
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| Publication Number | Publication Date |
|---|---|
| CN201319594Y true CN201319594Y (en) | 2009-09-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008201618529U Expired - Fee Related CN201319594Y (en) | 2008-10-23 | 2008-10-23 | Communication network power equalizer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364750A (en) * | 2011-10-14 | 2012-02-29 | 苏州市新诚氏电子有限公司 | Built-in attenuator structure |
-
2008
- 2008-10-23 CN CNU2008201618529U patent/CN201319594Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364750A (en) * | 2011-10-14 | 2012-02-29 | 苏州市新诚氏电子有限公司 | Built-in attenuator structure |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090930 Termination date: 20121023 |