CN201315585Y - BD-I receiver module - Google Patents
BD-I receiver module Download PDFInfo
- Publication number
- CN201315585Y CN201315585Y CNU2008201592266U CN200820159226U CN201315585Y CN 201315585 Y CN201315585 Y CN 201315585Y CN U2008201592266 U CNU2008201592266 U CN U2008201592266U CN 200820159226 U CN200820159226 U CN 200820159226U CN 201315585 Y CN201315585 Y CN 201315585Y
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- radio frequency
- radio
- frequency module
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Abstract
The utility model relates to a receiving module of a BD-I one-way time service receiver module. The receiving module comprises a circuit board, an FPGA module and a radio frequency module; and the radio frequency module is provided with a GPS signal radio frequency branch output interface. The receiving module adopts a single-chip FPGA to realize all the functions of base-band signal processing, data processing and management monitoring, has lower cost and is convenient for industrialized production; double-row and small-spacing connectors are arranged between the radio frequency module and the circuit board, so that the cost is low and the installation is convenient; the radio frequency module has the functions of GPS signal branch and feeding and direct current blocking, facilitates to quickly deploy the BD/GPS dual-modular redundancy time service system.
Description
Technical field
The present invention relates to receiver module of a kind of Big Dipper, be applied to satellite of the Big Dipper.
Background technology
Receiver of the Big Dipper generally includes antenna, feeder line, radio-frequency module, Base-Band Processing part.Big Dipper signal enters from exterior antenna, enters radio-frequency module by feeder line, and radio-frequency module is converted to intermediate-freuqncy signal with high-frequency signal, is handled by baseband portion again.Traditional way is: adopt dsp chip+FPGA to finish Base-Band Processing, wherein FPGA finishes AD conversion, carrier synchronization, acquiring pseudo code and tracking, demodulation, despreading, frame synchronization and Viterbi decoding; The data processing of then finishing DSP realizes the data processing function and the corresponding management controlled function of receiver.The problem that adopts this kind method to exist is to be difficult to make asic chip when industrialization is produced, so cost is difficult to reduce.The receiver module of Big Dipper Timing Receiver extensively adopts the paster connector to realize being connected of radio-frequency module and circuit board at present, and this paster connector costs an arm and a leg, and is not easy to install.Yet the existing Big Dipper receiver module of China adopts the DSP+FPGA hardware configuration mostly at present, and volume is bigger, and the cost height is unfavorable for industrialization.
Summary of the invention
The technical problem underlying that the present invention solves is to adopt monolithic FPGA to realize that all functions of Base-Band Processing, the largest benefit of monolithic FPGA structure are that to be convenient to ASIC integrated, realize industrialization; Adopt the mode of little spacing, double needle interface between interface and the interface, (for example double 10 needle interfaces of 1.27mm interface spacing) make the interface hypotelorism, and the length of whole interface reduces with interface is double because of spacing is little.Be convenient to install, connect reliably, and cost be low; Radio-frequency module has gps signal function along separate routes, and the signal that goes out uses for the GPS receiver along separate routes.
On circuit board 7, be provided with FPGA module 1, radio-frequency module 3, output interface 2, interface 8.Radio-frequency module 3 is a sealing metal box structure, includes gps signal radio frequency output interface 4, aerial signal input interface 5 and interface 6 along separate routes.Interface 6 on radio-frequency module is the socket of the double distribution of little spacing 1.27mm, and interface 8 is the contact pin of the double distribution of spacing 1.27mm on the module board, and the interface 6 of radio-frequency module is buckled on the interface 8 of circuit board, adopts the 2.5mm screw to fix.Interface 6 as radio-frequency module is a contact pin, and then the interface on the circuit board 8 is a socket.Interface 6 is corresponding plug connector with interface 8.
The invention has the advantages that: adopt monolithic FPGA to realize all functions of base band signal process, data processing, management and monitoring, cost is lower, is convenient to industrialization production; Adopt the connector of double 1.27mm between radio-frequency module and the circuit board, cost is low, is convenient to install; Radio-frequency module have gps signal along separate routes and feed every straight function, help disposing fast the Big Dipper/GPS dual mode system.
Description of drawings
Fig. 1 is the receiver module front view.
Fig. 2 is the receiver module right view.
Fig. 3 is the radio-frequency module front view.
Fig. 4 is a signal schematic diagram along separate routes.
Embodiment
The receiver module structure as shown in Figure 1.On circuit board 7, be provided with FPGA module 1, radio-frequency module 3, output interface 2, interface 8.Radio-frequency module 3 is a sealing metal box structure, includes gps signal radio frequency output interface 4, aerial signal input interface 5 and interface 6 along separate routes.Interface 6 on radio-frequency module is the socket of the double distribution of little spacing 1.27mm, and interface 8 is the contact pin of the double distribution of spacing 1.27mm on the module board, and the interface 6 of radio-frequency module is buckled on the interface 8 of circuit board, adopts the 2.5mm screw to fix.Interface 6 as radio-frequency module is a contact pin, and then the interface on the circuit board 8 is a socket.Interface 6 is corresponding plug connector with interface 8.Fig. 4 is a signal schematic diagram along separate routes, and received signal is divided into two-way, and one the tunnel directly sends, and another road is by illustrated resistance and electric capacity output.
Claims (4)
1, receiver module of the Big Dipper comprises circuit board (7), output interface (2), FPGA module (1) and radio-frequency module (3), it is characterized in that: circuit board (7) is provided with FPGA module (1), radio-frequency module (3), output interface (2), interface (8).
2, receiver module of the Big Dipper according to claim 1 is characterized in that: be provided with gps signal radio frequency output interface (4), aerial signal input interface (5) and interface (6) along separate routes on radio-frequency module (3).
3, receiver module of the Big Dipper according to claim 1 is characterized in that interface (6) and interface (8) are corresponding plug connector.
4, receiver module of the Big Dipper according to claim 2 is characterized in that interface (6) and interface (8) are double distribution, closely spaced connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201592266U CN201315585Y (en) | 2008-11-17 | 2008-11-17 | BD-I receiver module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201592266U CN201315585Y (en) | 2008-11-17 | 2008-11-17 | BD-I receiver module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201315585Y true CN201315585Y (en) | 2009-09-23 |
Family
ID=41127387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008201592266U Expired - Fee Related CN201315585Y (en) | 2008-11-17 | 2008-11-17 | BD-I receiver module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201315585Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571137A (en) * | 2012-02-14 | 2012-07-11 | 浙江大学 | Fully-digital direct sequence spread spectrum communication system and rapid pseudo code capturing method thereof |
| CN103023102A (en) * | 2012-11-26 | 2013-04-03 | 中国人民解放军国防科学技术大学 | Integrated power system for nano satellite |
| CN103968888A (en) * | 2013-02-06 | 2014-08-06 | 普适微芯科技（北京）有限公司 | Beidou navigation satellite system based grain situation monitoring system and operating method thereof |
| CN105137458A (en) * | 2015-07-24 | 2015-12-09 | 北京星地恒通信息科技有限公司 | Beidou-1 reception channel based on GPS radio frequency chip |
-
2008
- 2008-11-17 CN CNU2008201592266U patent/CN201315585Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571137A (en) * | 2012-02-14 | 2012-07-11 | 浙江大学 | Fully-digital direct sequence spread spectrum communication system and rapid pseudo code capturing method thereof |
| CN103023102A (en) * | 2012-11-26 | 2013-04-03 | 中国人民解放军国防科学技术大学 | Integrated power system for nano satellite |
| CN103968888A (en) * | 2013-02-06 | 2014-08-06 | 普适微芯科技（北京）有限公司 | Beidou navigation satellite system based grain situation monitoring system and operating method thereof |
| CN105137458A (en) * | 2015-07-24 | 2015-12-09 | 北京星地恒通信息科技有限公司 | Beidou-1 reception channel based on GPS radio frequency chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090923 Termination date: 20131117 |