CN201247066Y - Apparatus for rapidly extracting small signal - Google Patents
Apparatus for rapidly extracting small signal Download PDFInfo
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- CN201247066Y CN201247066Y CNU2008200132852U CN200820013285U CN201247066Y CN 201247066 Y CN201247066 Y CN 201247066Y CN U2008200132852 U CNU2008200132852 U CN U2008200132852U CN 200820013285 U CN200820013285 U CN 200820013285U CN 201247066 Y CN201247066 Y CN 201247066Y
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Abstract
The utility model relates to a quick extracting device of weak signals, which is provided with an analogue/digital converter which is used to sample primary target signals of mixed strong noise, a main control logic device which is used to receive sampling signals of the analogue/digital converter and is used to extract the sampling signals to calculate and obtain discretization target signals through utilizing original characteristic vectors which are extracted from big target signals or characteristic vectors which are circulated and updated, and a digital-analogue converter which is used to convert the discretization target signals which are output by the main control logic device and are extracted finally into analog signals to output. The quick extracting device has rapid extraction and strong practicability, can be used to extract the target signals which are submerged in noise rapidly to achieve the purpose of checking the target signals, a large-scale logic circuit is utilized to realize fast algorithm, and the quick extracting device is used in situations with few resources, rapid speed, low power consumption, and high requirements of real time performance.
Description
Technical field
The utility model relates to the Detection of Weak Signals technology, and specifically a kind of rapid extraction device of feeble signal can be applied to fields such as input, Target Recognition.
Background technology
It is more intense the energy of noise or interference to occur through regular meeting in engineering is used; sometimes can be comparable even echo signal all flooded with echo signal; be easy to cause information dropout or make mistakes if at this time extract, even echo signal may not extracted according to traditional detection method.In a lot of the application, require the position of real-time monitoring objective signal, if extracted echo signal by unusual complicated algorithm, but the delay of system is unacceptable, do not reach the purpose that real-time echo signal detects equally, at above situation, a kind of rapid extraction device of feeble signal has just had significance, and does not occur the rapid extraction device at this feeble signal at present as yet.
The utility model content
At the deficiencies in the prior art part, the technical problems to be solved in the utility model provides a kind of rapid extraction device of the feeble signal that the echo signal that is submerged in the noise can be extracted.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is:
The rapid extraction device of a kind of feeble signal of the utility model has:
Analog to digital converter is sampled to the original object signal of mixed very noisy;
The master control logic device, the sampled signal of reception analog to digital converter, the proper vector that original feature vector that utilization is extracted from the general objective signal or process circulation are upgraded is carried out the echo signal that rapid extraction calculates discretize to sampled signal;
Digital to analog converter converts the echo signal of the discretize of the last extraction of master control logic device output to simulating signal output.
Described master control logic device inside has with lower unit:
Analog to digital conversion steering logic unit, the sampled signal of reception analog to digital converter;
The rapid extraction unit carries out the echo signal rapid extraction with the signal of analog to digital conversion steering logic unit and proper vector computing unit input, removes very noisy, and the echo signal that obtains discretize exports digital to analog converter to by digital-to-analog conversion steering logic unit;
The proper vector computing unit, the echo signal that the original feature vector of extracting is reached the discretize of being exported by the amplitude limit smooth unit from the general objective signal is handled, and obtains new proper vector;
Digital-to-analog conversion steering logic unit converts the discretize echo signal of rapid extraction unit output to simulating signal and exports digital to analog converter to.
Described master control logic device inside also has the amplitude limit smooth unit, the echo signal with vibration to the output of rapid extraction unit is carried out amplitude limit and smoothing processing, obtain the echo signal of level and smooth discretize, export digital to analog converter to by digital-to-analog conversion steering logic unit.
Described rapid extraction unit has basic calculating module, cycle control module, accumulator module and counting module, and wherein the basic calculating module is carried out pointwise to the proper vector of the sampled signal of analog to digital converter and the input of proper vector computing unit and taken advantage of and add calculating; The cycle control module is carried out cycle control according to the numerical value of counting module to the basic calculating module; Accumulator module adds up to the result of calculation of basic calculating module and exports; Counting module adds up to the calculation times of basic calculating module.
Described master control logic device is FPGA or DSP.
The utlity model has following beneficial effect and advantage:
1. extract fast.The utility model utilizes the master control logic device that the weak target signal that is mixed with very noisy is extracted, carrying out pointwise by the basic calculating module of master control logic device inside takes advantage of and adds calculating, the echo signal rapid extraction that is submerged in the noise can be come out, reach the purpose that detects echo signal;
2. real-time.The extensive logical circuit of the utility model utilization is realized fast algorithm, few in resource, speed is fast, low in energy consumption, be adapted at the demanding occasion of real-time and use.
Description of drawings
Fig. 1 is the utility model structural representation;
Fig. 2 is the structural representation of rapid extraction unit in the utility model;
Fig. 3 is the utility model course of work process flow diagram.
Embodiment
As shown in Figure 1, 2, the utility model comprises with the lower part: analog to digital converter, the original signal of mixed very noisy is sampled; The master control logic device, the sampled signal of reception analog to digital converter, the proper vector that original feature vector that utilization is extracted from the general objective signal or process circulation are upgraded is carried out the echo signal that rapid extraction calculates discretize to sampled signal; Digital to analog converter converts the echo signal of the discretize of the last extraction of master control logic device output to simulating signal output.
Described master control logic device inside has with lower unit: analog to digital conversion steering logic unit, the sampled signal of reception analog to digital converter; The rapid extraction unit carries out the echo signal rapid extraction with the signal of analog to digital conversion steering logic unit and proper vector computing unit input, removes very noisy, and the echo signal that obtains discretize is by digital to analog converter output final goal signal; The proper vector computing unit, the echo signal that the original feature vector of extracting is reached the discretize of being exported by the amplitude limit smooth unit from the general objective signal is handled, and obtains new proper vector.Described master control logic device inside also has the amplitude limit smooth unit, and the echo signal with vibration of rapid extraction unit output is carried out amplitude limit and smoothing processing, obtains the echo signal of level and smooth discretize, by digital to analog converter output final goal signal.
Described rapid extraction unit has basic calculating module, cycle control module, accumulator module and counting module, and wherein the basic calculating module is carried out pointwise to the proper vector of the sampled signal of analog to digital converter and the input of proper vector computing unit and taken advantage of and add calculating; The cycle control module is carried out cycle control according to the numerical value of counting module to the basic calculating module; Accumulator module adds up to the result of calculation of basic calculating module; Counting module adds up to the calculation times of basic calculating module.
Above-mentioned master control logic device can be FPGA (field programmable gate array) or DSP (digital signal processor).
Principle of work of the present utility model is as follows: frequency, amplitude and phase place are three ingredients of signal, as long as these three character representations of signal (present embodiment is an example with the infrared sensor signal) are come out just can extract this signal, but sometimes can not obtain these three characteristic quantities simultaneously, can signal extraction be come out according to one of them or two characteristic quantities, the utility model is exactly to utilize the amplitude characteristic of signal or frequency characteristic that signal extraction is come out, (present embodiment adopts FPGA by extensive logical device, EP1C12) storage proper vector, along with constantly carrying out of signal sampling, the input that process sampling noiset and echo signal enter algorithm simultaneously, the data of proper vector and collection are calculated, echo signal just can have very high enlargement factor, the noise enlargement factor is but very little, like this data are carried out just cancelling noise signal fully of cutting process, reach the purpose of extracting signal, the amplitude of echo signal may change along with the time, as long as adjust proper vector in real time, just can adapt to the variation of echo signal.The core of whole algorithm is the basic calculating unit in the rapid extraction unit, is counting of proper vector and size is calculated in decision, and the utility model is realized quick computing by the design of basic calculating unit.
As shown in Figure 3, the course of work of the present utility model is as follows:
Original signal to mixed very noisy is sampled;
Above-mentioned sampled signal and proper vector are carried out rapid extraction, obtain removing the echo signal of the discretize of very noisy;
Adjust the value of proper vector according to the echo signal of discretize, obtain new proper vector, give to calculate next time and adopt;
Echo signal to above-mentioned vibration is carried out amplitude limit and smoothing processing;
By digital to analog converter output final goal signal.
Wherein above-mentioned rapid extraction may further comprise the steps: sampled signal and proper vector are carried out pointwise take advantage of and add calculating; Calculation times is added up; Carry out cycle control according to calculation times to taking advantage of to add to calculate.
Proper vector is got 256 points in the present embodiment, and 32 points are got in the basic calculating unit, and accumulative frequency is 256/32=8 so, and elementary cell is exported to the unit that adds up to result of calculation, adds up to obtain net result after 8 times.
Data by the pointwise multiply-add operation to m point, have obtained the result of calculation x (n) of basic calculating module in the computation process of basic calculating unit, and this basic calculating module has determined the quantity of logical block in the master control logic device of the present utility model.As the control core, recycling this basic calculating module has obtained the echo signal output y (n) of discretize at last with the basic calculating single module, and the round-robin number of times has determined time response of the present utility model.
The logical resource that takies and the response time of device are contradiction, can determine counting and cycle index of basic calculating module to reach best effect, the logical resource of consumes least, arranged the good response time again by test.
Claims (5)
1. the rapid extraction device of a feeble signal is characterized in that having:
Analog to digital converter is sampled to the original object signal of mixed very noisy;
The master control logic device, the sampled signal of reception analog to digital converter, the echo signal of output discretize;
Digital to analog converter converts the echo signal of the discretize of the last extraction of master control logic device output to simulating signal output.
2. by the rapid extraction device of the described feeble signal of claim 1, it is characterized in that: described master control logic device inside has with lower unit:
Analog to digital conversion steering logic unit, the sampled signal of reception analog to digital converter;
The rapid extraction unit carries out the echo signal rapid extraction with the signal of analog to digital conversion steering logic unit and proper vector computing unit input, removes very noisy, and the echo signal that obtains discretize exports digital to analog converter to by digital-to-analog conversion steering logic unit;
Proper vector computing unit, the original feature vector that reception is extracted from the general objective signal reach by the echo signal of the discretize of amplitude limit smooth unit output and handle, and export new proper vector;
Digital-to-analog conversion steering logic unit converts the discretize echo signal of rapid extraction unit output to simulating signal and exports digital to analog converter to.
3. press the rapid extraction device of the described feeble signal of claim 2, it is characterized in that: described master control logic device inside also has the amplitude limit smooth unit, the echo signal with vibration to the output of rapid extraction unit is carried out amplitude limit and smoothing processing, obtain the echo signal of level and smooth discretize, export digital to analog converter to by digital-to-analog conversion steering logic unit.
4. press the rapid extraction device of the described feeble signal of claim 2, it is characterized in that: described rapid extraction unit has basic calculating module, cycle control module, accumulator module and counting module, and wherein the basic calculating module proper vector that receives the sampled signal of analog to digital converter and the input of proper vector computing unit is carried out pointwise and taken advantage of and add calculating; The numerical value of cycle control module count pick up module carries out cycle control to the basic calculating module; The result of calculation of accumulator module reception basic calculating module adds up and exports; The calculation times that counting module receives the basic calculating module adds up.
5. by the rapid extraction device of the described feeble signal of claim 1, it is characterized in that: described master control logic device is FPGA or DSP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200132852U CN201247066Y (en) | 2008-06-04 | 2008-06-04 | Apparatus for rapidly extracting small signal |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2008200132852U CN201247066Y (en) | 2008-06-04 | 2008-06-04 | Apparatus for rapidly extracting small signal |
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| CN201247066Y true CN201247066Y (en) | 2009-05-27 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101598571B (en) * | 2008-06-04 | 2012-02-08 | 中国科学院沈阳自动化研究所 | Method and device for rapidly extracting feeble signal |
| CN102455239A (en) * | 2010-10-29 | 2012-05-16 | 中国科学院沈阳自动化研究所 | Method utilizing phase-locking amplifier to detect weak signals of dynamic balancer and device for method |
-
2008
- 2008-06-04 CN CNU2008200132852U patent/CN201247066Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101598571B (en) * | 2008-06-04 | 2012-02-08 | 中国科学院沈阳自动化研究所 | Method and device for rapidly extracting feeble signal |
| CN102455239A (en) * | 2010-10-29 | 2012-05-16 | 中国科学院沈阳自动化研究所 | Method utilizing phase-locking amplifier to detect weak signals of dynamic balancer and device for method |
| CN102455239B (en) * | 2010-10-29 | 2013-09-18 | 中国科学院沈阳自动化研究所 | Method utilizing phase-locking amplifier to detect weak signals of dynamic balancer and device for method |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090527 Termination date: 20100604 |