CN201238053Y - LED chip packaging structure with different arrangement interspace - Google Patents
LED chip packaging structure with different arrangement interspace Download PDFInfo
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- CN201238053Y CN201238053Y CNU2008201305539U CN200820130553U CN201238053Y CN 201238053 Y CN201238053 Y CN 201238053Y CN U2008201305539 U CNU2008201305539 U CN U2008201305539U CN 200820130553 U CN200820130553 U CN 200820130553U CN 201238053 Y CN201238053 Y CN 201238053Y
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- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 239000000084 colloidal system Substances 0.000 claims abstract description 96
- 238000005538 encapsulation Methods 0.000 claims description 43
- 239000011295 pitch Substances 0.000 claims description 27
- 238000012856 packing Methods 0.000 claims description 24
- 238000010276 construction Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000004020 luminiscence type Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000000741 silica gel Substances 0.000 claims description 3
- 229910002027 silica gel Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 17
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229920001342 Bakelite® Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000004637 bakelite Substances 0.000 description 3
- 230000005494 condensation Effects 0.000 description 3
- 238000009833 condensation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000016507 interphase Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Led Device Packages (AREA)
Abstract
The utility model relates to a light-emitting diode chip package structure with unequal arrangement spaces, which comprises a baseplate unit, a light-emitting unit and packaging colloid units. The baseplate unit is provided with a baseplate body, a positive conductive track and a negative conductive track, and the positive conductive track and the negative conductive track are respectively formed on the baseplate body. Moreover, the light-emitting unit is provided with a plurality of light-emitting diode chips electrically arranged on the baseplate unit, and each light-emitting diode chip is provided with a positive end and a negative end which are respectively connected with the positive conductive track and the negative conductive track. In addition, the spaces between the light-emitting diode chips are totally or partially unequal. The light-emitting diode chips are covered by the packaging colloid units. For example, the spaces between the light-emitting diode chips vary from sparse to dense, from dense to sparse, from sparse in the middle to dense outwardly or from dense in the middle to sparse outwardly, or alternate between sparse and dense. The utility model can effectively shorten the process time.
Description
Technical field
The utility model relates to a kind of LED encapsulation construction, relates in particular to a kind of LED encapsulation construction with different arrangement pitches.
Background technology
See also shown in Figure 1ly, it is the flow chart of traditional light emitter diode seal method.By in the flow chart as can be known, traditional light emitter diode seal method may further comprise the steps: at first, the light-emitting diode that provides a plurality of encapsulation to finish is asked for an interview step S100; Then, provide the strip substrate body, have positive conductive traces and negative pole conductive traces on it, ask for an interview step S102; At last, the light-emitting diode that each encapsulation is finished is arranged on this strip substrate body in regular turn, and the positive and negative positive and negative electrode conductive traces that extremely is electrically connected at this strip substrate body respectively of the light-emitting diode that each encapsulation is finished, ask for an interview step S104.
Yet, about above-mentioned traditional light emitter diode seal method, because the light-emitting diode that each encapsulation is finished must cut down from a monoblock LED package earlier, and then with surface adhering technology (SMT) technology, the light-emitting diode that each encapsulation is finished is arranged on this strip substrate body, therefore can't effectively shorten the process time.Moreover, because the encapsulating structure of traditional light-emitting diode does not have any protective device, therefore often cause unstable or other the unsettled situation generation of power supply.
Summary of the invention
Technical problem to be solved in the utility model is to provide a kind of LED encapsulation construction with different arrangement pitches.LED encapsulation construction of the present utility model has a plurality of light-emitting diode chip for backlight unit, and above-mentioned a plurality of light-emitting diode chip for backlight unit has complete difference or the different spacing of part each other, to meet different users's demand.
Moreover the utility model encapsulates directly by chip that (Chip On Board, COB) technology and utilize the mode of pressing mold (die mold) makes the utility model to shorten the process time effectively, thereby can produce in a large number.In addition, structural design of the present utility model more is applicable to various light sources, such as application such as backlight module, Decorating lamp strip, illuminator lamp or scanner light sources, is applied scope of the utility model and product.
In order to solve the problems of the technologies described above, according to wherein a kind of scheme of the present utility model, provide a kind of LED encapsulation construction with different arrangement pitches, it comprises: base board unit, luminescence unit, and packing colloid unit.Wherein base board unit has substrate body, reaches the positive conductive traces and the negative pole conductive traces that are formed at respectively on this substrate body.Moreover, this luminescence unit has a plurality of light-emitting diode chip for backlight unit that are arranged at electrically on this base board unit, each light-emitting diode chip for backlight unit has the positive conductive traces that is electrically connected at this base board unit respectively and the positive terminal and the negative pole end of negative pole conductive traces, and above-mentioned a plurality of light-emitting diode chip for backlight unit has complete difference or the different spacing of part each other.This packing colloid unit is covered on above-mentioned a plurality of light-emitting diode chip for backlight unit.
Therefore, above-mentioned a plurality of light-emitting diode chip for backlight unit have complete difference or the different spacing of part each other, for example following six kinds of execution modes:
First kind of execution mode: above-mentioned a plurality of light-emitting diode chip for backlight unit spacing each other is by dredging to close.
Second kind of execution mode: above-mentioned a plurality of light-emitting diode chip for backlight unit spacing each other by close to dredging.
The third execution mode: above-mentioned a plurality of light-emitting diode chip for backlight unit spacing is each other dredged peripheral close by the centre.
The 4th kind of execution mode: above-mentioned a plurality of light-emitting diode chip for backlight unit spacing is each other dredged to peripheral by the centre is close.
The 5th kind of execution mode: above-mentioned a plurality of light-emitting diode chip for backlight unit spacing each other is a density interphase.
The 6th kind of execution mode: above-mentioned a plurality of light-emitting diode chip for backlight unit spacing each other is between close lean phase.
Moreover the utility model is by the direct packaging technology of chip and utilize the mode of pressing mold, makes the utility model to shorten the process time effectively, thereby can produce in a large number.
In order further to understand the utility model is to reach technology, means and the effect that predetermined purpose is taked, see also following about detailed description of the present utility model and accompanying drawing, believe the purpose of this utility model, feature and characteristics, when obtaining thus deeply and concrete understanding, yet accompanying drawing is only for reference and explanation, is not to be used for the utility model is limited.
Description of drawings
Fig. 1 is the flow chart of traditional LED encapsulation method;
Fig. 2 A is the schematic diagram of first kind of arrangement mode of the utility model light-emitting diode chip for backlight unit;
Fig. 2 B is the schematic diagram of second kind of arrangement mode of the utility model light-emitting diode chip for backlight unit;
Fig. 2 C is the schematic diagram of the third arrangement mode of the utility model light-emitting diode chip for backlight unit;
Fig. 2 D is the schematic diagram of the 4th kind of arrangement mode of the utility model light-emitting diode chip for backlight unit;
Fig. 2 E is the schematic diagram of the 5th kind of arrangement mode of the utility model light-emitting diode chip for backlight unit;
Fig. 2 F is the schematic diagram of the 6th kind of arrangement mode of the utility model light-emitting diode chip for backlight unit;
Fig. 3 A to Fig. 3 C is respectively the encapsulation schematic flow sheet of first embodiment of the LED chip encapsulation method that the utlity model has different arrangement pitches;
Fig. 3 D is the 3-3 profile of Fig. 3 C;
Fig. 4 A to Fig. 4 B is respectively the part encapsulation schematic flow sheet of second embodiment of the LED chip encapsulation method that the utlity model has different arrangement pitches;
Fig. 4 C is the 3-3 profile of Fig. 4 B;
Fig. 5 A is the part encapsulation schematic flow sheet of the 3rd embodiment that the utlity model has the LED chip encapsulation method of different arrangement pitches;
Fig. 5 B is the 5-5 profile of Fig. 5 A;
Fig. 6 A to Fig. 6 B is respectively the part encapsulation schematic flow sheet of the 4th embodiment of the LED chip encapsulation method that the utlity model has different arrangement pitches;
Fig. 6 C is the 6-6 profile of Fig. 6 B;
Fig. 7 A to Fig. 7 B is respectively the part encapsulation schematic flow sheet of the 5th embodiment of the LED chip encapsulation method that the utlity model has different arrangement pitches;
Fig. 7 C is the 7-7 profile of Fig. 7 B;
Fig. 8 A to Fig. 8 B is respectively the part encapsulation schematic flow sheet of the 6th embodiment of the LED chip encapsulation method that the utlity model has different arrangement pitches;
Fig. 8 C is the 8-8 profile of Fig. 8 B;
Fig. 9 A to Fig. 9 B is respectively the part encapsulation schematic flow sheet of the 7th embodiment of the LED chip encapsulation method that the utlity model has different arrangement pitches; And
Fig. 9 C is the 9-9 profile of Fig. 9 B.
Wherein, description of reference numerals is as follows:
1 base board unit, 10 substrate body
The 10A metal level
10B bakelite layer
11 positive conductive traces
12 negative pole conductive traces
2 luminescence units, 20 light-emitting diode chip for backlight unit
201 positive terminals
202 negative pole ends
4a packing colloid unit
4b packing colloid unit 40b colloid cambered surface
41b colloid exiting surface
4c packing colloid unit 40c fluorescent colloid
4d packing colloid unit 40d fluorescent colloid
4e packing colloid unit 40e fluorescent colloid
4f packing colloid unit 40f fluorescent colloid
400f colloid cambered surface
401f colloid exiting surface
4g packing colloid unit 40g fluorescent colloid
400g colloid cambered surface
401g colloid exiting surface
The 5b frame unit
The 5e frame unit
The 5g frame unit
The L1 light-emitting diode chip for backlight unit
A1, a2, a3, a4, a5, a6, a7, a8 spacing
The L2 light-emitting diode chip for backlight unit
B1, b2, b3, b4, b5, b6, b7, b8 spacing
The L3 light-emitting diode chip for backlight unit
C1, c2, c3, c4, c5, c6, c7, c8 spacing
The L4 light-emitting diode chip for backlight unit
D1, d2, d3, d4, d5, d6, d7, d8 spacing
The L5 light-emitting diode chip for backlight unit
E1, e2, e3, e4, e5, e6, e7, e8 spacing
The L6 light-emitting diode chip for backlight unit
F1, f2, f3, f4, f5, f6, f7, f8 spacing
Embodiment
See also shown in Fig. 2 A to Fig. 2 F, its be respectively first kind, second kind of the utility model light-emitting diode chip for backlight unit, the third, the schematic diagram of the 4th kind, the 5th kind, the 6th kind arrangement mode.
By Fig. 2 A as can be known, above-mentioned a plurality of light-emitting diode chip for backlight unit L1 spacing (a1, a2, a3, a4, a5, a6, a7, a8) each other is to close (condensation) by thin (rarefaction).Therefore, above-mentioned a plurality of light-emitting diode chip for backlight unit L1 spacing each other be little by being discharged to greatly (a1〉a2〉a3 a4 a5 a6 a7 a8).
By Fig. 2 B as can be known, above-mentioned a plurality of light-emitting diode chip for backlight unit L2 spacing (b1, b2, b3, b4, b5, b6, b7, b8) each other is to dredging by close.Therefore, above-mentioned a plurality of light-emitting diode chip for backlight unit L2 spacing each other is little (b1＜b2＜b3＜b4＜b5＜b6＜b7＜b8) by being discharged to greatly.
By Fig. 2 C as can be known, above-mentioned a plurality of light-emitting diode chip for backlight unit L3 spacing (c1, c2, c3, c4, c5, c6, c7, c8) each other is thin to peripheral close by the centre.Therefore, above-mentioned a plurality of light-emitting diode chip for backlight unit L3 spacing each other be by broad in the middle be discharged to peripheral little (c4=c5〉c3=c6〉c2=c7 c1=c8).
By Fig. 2 D as can be known, above-mentioned a plurality of light-emitting diode chip for backlight unit L4 spacing (d1, d2, d3, d4, d5, d6, d7, d8) each other is to dredge to peripheral by the centre is close.Therefore, above-mentioned a plurality of light-emitting diode chip for backlight unit L4 spacing each other is to peripheral big (d4=d5＜d3=d6＜d2=d7＜d1=d8) by middle float.
By Fig. 2 E as can be known, above-mentioned a plurality of light-emitting diode chip for backlight unit L5 spacing (e1, e2, e3, e4, e5, e6, e7, e8) each other is that density (rarefaction and condensation) is alternate.Therefore, above-mentioned a plurality of light-emitting diode chip for backlight unit L5 spacing each other is big spacing and little spacing alternate each other (e1=e3=e5=e7〉e2=e4=e6=e8).
By Fig. 2 F as can be known, above-mentioned a plurality of light-emitting diode chip for backlight unit L6 spacing (f1, f2, f3, f4, f5, f6, f7, f8) each other is that close thin (condensation and rarefaction) is alternate.Therefore, above-mentioned a plurality of light-emitting diode chip for backlight unit L6 spacing each other to be small distance alternate each other with big distance (f1=f3=f5=f7＜f2=f4=f6=f8).
Though it is above-mentioned to carry out the arrangement of above-mentioned a plurality of light-emitting diode chip for backlight unit by the direct packaging technology of chip; but this describes non-in order to limit the utility model; the arrangement mode of every any relevant a plurality of light-emitting components; for example use surface adhesion type (Surface Mounted Device; SMD) light-emitting diode is the utility model category required for protection.
Below have seven embodiment, row's example mode of the light-emitting diode chip for backlight unit of these seven embodiment is that example describes with first kind of arrangement mode of above-mentioned Fig. 2 A.
Please cooperate shown in Fig. 3 A, first embodiment of the present utility model provides a kind of LED chip encapsulation method with different arrangement pitches, it comprises the following steps: it at first is step S200, base board unit 1 is provided, and wherein this base board unit has substrate body 10, reaches the positive conductive traces 11 and negative pole conductive traces 12 that are formed at respectively on this substrate body 10.
Moreover, according to designer's needs, this base board unit 1 can be printed circuit board (PCB), soft base plate (flexiblesubstrate), aluminium base (aluminum substrate), ceramic substrate (ceramic substrate) or copper base (copper substrate).In addition, this substrate body 10 comprises metal level 10A and is formed in bakelite layer (bakelite layer) 10B on this metal level 10A, and this positive conductive traces 11, negative pole conductive traces 12 can be aluminum steel road or silver-colored circuit.
Please cooperate shown in Fig. 3 B, first embodiment of the present utility model further comprises the following steps: step S202, luminescence unit 2 is set electrically on this substrate body 10, wherein this luminescence unit 2 has a plurality of light-emitting diode chip for backlight unit 20, and above-mentioned a plurality of light-emitting diode chip for backlight unit 20 spacing each other is by dredging to close, and wherein each light-emitting diode chip for backlight unit 20 has the positive conductive traces 11 that is electrically connected at this base board unit 1 respectively, the positive terminal 201 and the negative pole end 202 of negative pole conductive traces 12.
Please cooperate shown in Fig. 3 C and Fig. 3 D, first embodiment of the present utility model further comprises the following steps: step S206, covers packing colloid unit 4a on above-mentioned a plurality of light-emitting diode chip for backlight unit 20.Moreover, this packing colloid unit 4a is the strip fluorescent colloid (stripped fluorescent colloid) of corresponding above-mentioned a plurality of light-emitting diode chip for backlight unit 20, and this strip fluorescent colloid can be mixed or be mixed by epoxy resin and fluorescent material by silica gel and fluorescent material.
See also Fig. 4 A to Fig. 4 B, reach shown in Fig. 4 C, the step of the second embodiment front (can be considered step S300 to S304) is identical with the step S200 to S204 of first embodiment.That is step S300 is equal to the schematic view illustrating of Fig. 2 A of first embodiment; Step S302 and S304 are equal to the schematic view illustrating of Fig. 2 B of first embodiment.
See also shown in Fig. 4 A, after the step S304 of the utility model second embodiment, further comprise the following steps: step S306, cover packing colloid unit 4b on above-mentioned a plurality of light-emitting diode chip for backlight unit 20, and the upper surface of this packing colloid unit 4b and front surface have colloid cambered surface (colloid cambered surface) 40b and colloid exiting surface (colloid light-exiting surface) 41b respectively.Moreover this packing colloid unit 4b can be the strip fluorescent colloid of corresponding above-mentioned a plurality of light-emitting diode chip for backlight unit 20, so the upper surface of this strip fluorescent colloid and front surface are respectively this colloid cambered surface 40b and this colloid exiting surface 41b.
See also shown in Fig. 4 B and Fig. 4 C, the utility model second embodiment further comprises the following steps: step S308, by frame unit 5b, coat this packing colloid unit 4b and only expose the side surface (being this colloid exiting surface 41b) of this packing colloid unit 4b, and this frame unit 5b is light tight ccf layer.
See also shown in Fig. 5 A and Fig. 5 B, the step of the 3rd embodiment front (can be considered step S400 to S404) is identical with the step S200 to S204 of first embodiment.That is step S400 is equal to the schematic view illustrating of Fig. 2 A of first embodiment; Step S402 and S404 are equal to the schematic view illustrating of Fig. 2 B of first embodiment.
Moreover, cooperate shown in Fig. 5 A and Fig. 5 B, after the step S404 of the utility model the 3rd embodiment, further comprise the following steps: step S406, cover a plurality of fluorescent colloid 40c respectively on above-mentioned a plurality of light-emitting diode chip for backlight unit 20, wherein above-mentioned a plurality of fluorescent colloid 40c form packing colloid unit 4c.
See also Fig. 6 A to Fig. 6 B, reach shown in Fig. 6 C, the step of the 4th embodiment front (can be considered step S500 to S504) is identical with the step S200 to S204 of first embodiment.That is step S500 is equal to the schematic view illustrating of Fig. 2 A of first embodiment; Step S502 and S504 are equal to the schematic view illustrating of Fig. 2 B of first embodiment.
See also shown in Fig. 6 A, after the step S504 of the utility model the 4th embodiment, further comprise the following steps: step S506, cover a plurality of fluorescent colloid 40d respectively on above-mentioned a plurality of light-emitting diode chip for backlight unit 20, wherein above-mentioned a plurality of fluorescent colloid 40d form packing colloid unit 4d; Be step S508 then, frame unit with a plurality of ccf layer 50d 5d is provided, and each ccf layer 50d is used for only exposing around this corresponding fluorescent colloid 40d the upper surface of this corresponding fluorescent colloid 40d, and wherein above-mentioned a plurality of ccf layer 50d are a plurality of light tight ccf layers.
See also Fig. 7 A to Fig. 7 B, reach shown in Fig. 7 C, the step of the 5th embodiment front (can be considered step S600 to S604) is identical with the step S200 to S204 of first embodiment.That is step S600 is equal to the schematic view illustrating of Fig. 2 A of first embodiment; Step S602 and S604 are equal to the schematic view illustrating of Fig. 2 B of first embodiment.
See also shown in Fig. 7 A, after the step S604 of the utility model the 5th embodiment, further comprise the following steps: step S606, cover a plurality of fluorescent colloid 40e respectively on above-mentioned a plurality of light-emitting diode chip for backlight unit 20, wherein above-mentioned a plurality of fluorescent colloid 40e form packing colloid unit 4e; Be step S608 then, by frame unit 5e, come only to expose around above-mentioned a plurality of fluorescent colloid 40e the upper surface of above-mentioned a plurality of fluorescent colloid 40e, wherein this frame unit 5e is light tight ccf layer.
See also Fig. 8 A to Fig. 8 B, reach shown in Fig. 8 C, the step of the 6th embodiment front (can be considered step S700 to S704) is identical with the step S200 to S204 of first embodiment.That is step S700 is equal to the schematic view illustrating of Fig. 2 A of first embodiment; Step S702 and S704 are equal to the schematic view illustrating of Fig. 2 B of first embodiment.
See also shown in Fig. 8 A, after the step S704 of the utility model the 6th embodiment, further comprise the following steps: step S706, cover a plurality of fluorescent colloid 40f respectively on above-mentioned a plurality of light-emitting diode chip for backlight unit 20, and the upper surface of each fluorescent colloid 40f and front surface have colloid cambered surface 400f and colloid exiting surface 401f respectively.Moreover above-mentioned a plurality of fluorescent colloid 40f are combined into packing colloid unit 4f.
See also shown in Fig. 8 B and Fig. 8 C, the utility model the 6th embodiment further comprises the following steps: step S708, frame unit with a plurality of ccf layer 50f 5f is provided, and each ccf layer 50f is used to coat this corresponding fluorescent colloid 40f and the side surface that only exposes this corresponding fluorescent colloid 40f, and wherein above-mentioned a plurality of ccf layer 50f are a plurality of light tight ccf layers.
See also Fig. 9 A to Fig. 9 B, reach shown in Fig. 9 C, the step of the 7th embodiment front (can be considered step S800 to S804) is identical with the step S200 to S204 of first embodiment.That is step S800 is equal to the schematic view illustrating of Fig. 2 A of first embodiment; Step S802 and S804 are equal to the schematic view illustrating of Fig. 2 B of first embodiment.
See also shown in Fig. 9 A, after the step S804 of the utility model the 7th embodiment, further comprise the following steps: step S806, cover a plurality of fluorescent colloid 40g respectively on above-mentioned a plurality of light-emitting diode chip for backlight unit 20, and the upper surface of each fluorescent colloid 40g and front surface have colloid cambered surface 400g and colloid exiting surface 401g respectively.Moreover above-mentioned a plurality of fluorescent colloid 40g are combined into packing colloid unit 4g.
See also shown in Fig. 9 B and Fig. 9 C, the utility model the 7th embodiment further comprises the following steps: step S808, by frame unit 5g, coat above-mentioned a plurality of fluorescent colloid 40g and only expose the side surface of above-mentioned a plurality of fluorescent colloid 40g, wherein this frame unit 5g is light tight ccf layer.
In sum, LED encapsulation construction of the present utility model has a plurality of light-emitting diode chip for backlight unit, and above-mentioned a plurality of light-emitting diode chip for backlight unit has complete difference or the different spacing of part each other, thereby can meet different users's demand.
Moreover the utility model is by the direct packaging technology of chip and utilize the mode of pressing mold (die mold), makes the utility model to shorten its process time effectively, thereby can produce in a large number.In addition, structural design of the present utility model more is applicable to various light sources, such as application such as backlight module, Decorating lamp strip, illuminator lamp or scanner light sources, is applied scope of the utility model and product.
Yet the above, only be the detailed description and the accompanying drawing of the specific embodiment of one of the utility model the best, but feature of the present utility model is not limited thereto, more than detailed description is not in order to restriction the utility model with accompanying drawing, all scopes of the present utility model should be as the criterion with claims, all embodiment that meets the spirit variation similar of the utility model claim scope with it, all should be contained in the category of the present utility model, any those skilled in the art are in field of the present utility model, and the variation that can expect easily or modification all can be encompassed in following claim of the present utility model.
Claims (15)
1, a kind of LED encapsulation construction with different arrangement pitches is characterized in that, comprising:
Base board unit, it has substrate body, reaches the positive conductive traces and the negative pole conductive traces that are formed at respectively on this substrate body;
Luminescence unit, it has a plurality of light-emitting diode chip for backlight unit that are arranged at electrically on this base board unit, each light-emitting diode chip for backlight unit has the positive conductive traces that is electrically connected at this base board unit respectively and the positive terminal and the negative pole end of negative pole conductive traces, and described a plurality of light-emitting diode chip for backlight unit has complete difference or the different spacing of part each other; And
The packing colloid unit, it is covered on described a plurality of light-emitting diode chip for backlight unit.
2, the LED encapsulation construction with different arrangement pitches as claimed in claim 1 is characterized in that: described a plurality of light-emitting diode chip for backlight unit spacing each other is by dredging to close.
3, the LED encapsulation construction with different arrangement pitches as claimed in claim 1 is characterized in that: described a plurality of light-emitting diode chip for backlight unit spacing each other by close to dredging.
4, the LED encapsulation construction with different arrangement pitches as claimed in claim 1 is characterized in that: described a plurality of light-emitting diode chip for backlight unit spacing is each other dredged peripheral close by the centre.
5, the LED encapsulation construction with different arrangement pitches as claimed in claim 1 is characterized in that: described a plurality of light-emitting diode chip for backlight unit spacing is each other dredged to peripheral by the centre is close.
6, the LED encapsulation construction with different arrangement pitches as claimed in claim 1 is characterized in that: described a plurality of light-emitting diode chip for backlight unit spacing each other is between density or close lean phase.
7, the LED encapsulation construction with different arrangement pitches as claimed in claim 1 is characterized in that: the strip fluorescent colloid that this packing colloid unit is corresponding described a plurality of light-emitting diode chip for backlight unit.
8, the LED encapsulation construction with different arrangement pitches as claimed in claim 7 is characterized in that: this strip fluorescent colloid is mixed by silica gel and fluorescent material or is mixed by epoxy resin and fluorescent material.
9, the LED encapsulation construction with different arrangement pitches as claimed in claim 7, it is characterized in that, further comprise: frame unit, it is used to coat this strip fluorescent colloid and the side surface that only exposes this strip fluorescent colloid, wherein the upper surface of this strip fluorescent colloid and front surface have colloid cambered surface and colloid exiting surface respectively, and this frame unit is light tight ccf layer.
10, the LED encapsulation construction with different arrangement pitches as claimed in claim 1, it is characterized in that: this packing colloid unit has the fluorescent colloid of a plurality of corresponding described a plurality of light-emitting diode chip for backlight unit.
11, the LED encapsulation construction with different arrangement pitches as claimed in claim 10 is characterized in that: each fluorescent colloid is mixed by silica gel and fluorescent material or is mixed by epoxy resin and fluorescent material.
12, the LED encapsulation construction with different arrangement pitches as claimed in claim 10, it is characterized in that, further comprise: frame unit, it has a plurality of ccf layers, and each ccf layer is used for only exposing around this corresponding fluorescent colloid the upper surface of this corresponding fluorescent colloid, and wherein said a plurality of ccf layers are a plurality of light tight ccf layers.
13, the LED encapsulation construction with different arrangement pitches as claimed in claim 10, it is characterized in that, further comprise: frame unit, it is used for only exposing around described a plurality of fluorescent colloids the upper surface of described a plurality of fluorescent colloids, and wherein this frame unit is light tight ccf layer.
14, the LED encapsulation construction with different arrangement pitches as claimed in claim 10, it is characterized in that, further comprise: frame unit, it has a plurality of ccf layers, and each ccf layer is used to coat this corresponding fluorescent colloid and the side surface that only exposes this corresponding fluorescent colloid, wherein the upper surface of each fluorescent colloid and front surface have colloid cambered surface and colloid exiting surface respectively, and described a plurality of ccf layer is a plurality of light tight ccf layers.
15, the LED encapsulation construction with different arrangement pitches as claimed in claim 10, it is characterized in that, further comprise: frame unit, it is used to coat described a plurality of fluorescent colloid and the side surface that only exposes described a plurality of fluorescent colloids, wherein the upper surface of each fluorescent colloid and front surface have colloid cambered surface and colloid exiting surface respectively, and this frame unit is light tight ccf layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201305539U CN201238053Y (en) | 2008-07-16 | 2008-07-16 | LED chip packaging structure with different arrangement interspace |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201305539U CN201238053Y (en) | 2008-07-16 | 2008-07-16 | LED chip packaging structure with different arrangement interspace |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201238053Y true CN201238053Y (en) | 2009-05-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008201305539U Expired - Fee Related CN201238053Y (en) | 2008-07-16 | 2008-07-16 | LED chip packaging structure with different arrangement interspace |
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| Country | Link |
|---|---|
| CN (1) | CN201238053Y (en) |
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2008
- 2008-07-16 CN CNU2008201305539U patent/CN201238053Y/en not_active Expired - Fee Related
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Granted publication date: 20090513 Termination date: 20120716 |