CN201226564Y - Analogue output apparatus supporting various video compression standard - Google Patents
Analogue output apparatus supporting various video compression standard Download PDFInfo
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- CN201226564Y CN201226564Y CNU2008200073731U CN200820007373U CN201226564Y CN 201226564 Y CN201226564 Y CN 201226564Y CN U2008200073731 U CNU2008200073731 U CN U2008200073731U CN 200820007373 U CN200820007373 U CN 200820007373U CN 201226564 Y CN201226564 Y CN 201226564Y
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Abstract
The utility model relates to an analog output device supporting multiple video compression standards, which comprises a high-speed data channel, a video processing unit with DRAM and a digital/analogue conversion circuit, and is characterized in that the high-speed data channel transmits bus-in high-bandwidth continuous digital video data to the video processing unit with the DRAM through the high-speed data bus; the video processing unit with the DRAM receives and stores the digital video signal flows, acquires multi-path digital video signals by separate reduction, and respectively processes the signals and outputs to the corresponding D/A conversion circuits; the multi-path D/A conversion circuits respectively output analog video signals. The utility model has the advantages of simple structure and capable of supporting analog outputs of various video compression standards.
Description
Technical field
The utility model belongs to a kind of video output device, is specifically related to a kind of analog video output device of supporting the various video compression standard.
Background technology
The simulation export technique of various video compression standard is widely used in the Surveillance center in large scale digital video system fields such as video monitoring, long-distance education, remote automation management, and the large scale digital video system has obtained deep application in industries such as bank, traffic, electric power, telecommunications, supervision of the cities.At present can finish functions such as video compression, video storage, centralized management and remote transmission according to different application demands.
It is very many to be applied in digital supervision industry video image compression algorithm at present, for the large scale digital video system, because the compression device that multi-channel video adopts respectively is that a plurality of producers provide.Therefore to concentrate on video wall in Surveillance center and show that just have some technical issues that need to address, general processing method has following two kinds now:
A kind of method is an application model block diagram as shown in Figure 1: for each video standard dedicated decoders is set, switch to realize concentrating on the video wall by video matrix then and show respectively, this pattern need be to the decoder of the equipment configuration special use of each producer, multi-channel video to output switches the concentrated video wall demonstration of realization by video matrix, its shortcoming is that the multiple decoder of configuration causes system complex, the cost height, but also to join video matrix, control also very complicated.
Second method is an application model block diagram as shown in Figure 2, adopts multiple pc machine decoding technique, directly the output of PC display is connected to video wall, and Fig. 2 represents the formation block diagram of this kind application model.Video decode adopts software mode, directly shows on the PC display.The shortcoming of this mode is to need multiple computers when for video wall a plurality of display being arranged, and is with high costs.Also need to join switching matrix simultaneously, structure and control are also very complicated.
Summary of the invention
The technical problems to be solved in the utility model provides a kind of simple in structure, the analogue output unit that can support the various video compression standard.
The technical scheme that addresses the above problem is: the utility model comprises: video processing unit and the multi-channel A/D change-over circuit of high-speed data channel, band DRAM is characterized in that:
Described high-speed data channel, the digital of digital video data that the high bandwidth of bus input is continuous is transferred to the video processing unit of described band DRAM by high speed data bus;
The video processing unit of described band DRAM receives, stores above-mentioned digital video signal stream, obtains the multipath digital video signal by separating reduction, and corresponding described D/A change-over circuit is handled and outputed to these signals respectively;
Described multi-channel A/D change-over circuit is exported the corresponding simulating vision signal respectively.
The continuous digital of digital video data of above-mentioned high bandwidth is to adopt the decoding software decoding at other general processors (for example PC CPU), be provided with the decoding software to various compression algorithms on this general processor, each road compressed video generates yuv data by decoding software decoding reduction back.Again decoded yuv data is transferred to the video processing unit of band DRAM by the utility model high-speed data channel, DRAM is used for receiving, store above-mentioned data, video processing unit obtains the multipath digital video signal by separating with these reductions of data, corresponding D/A change-over circuit is handled and outputed to these signals respectively, each road D/A change-over circuit output is directly exported analog signal respectively, on TV or display, show, owing in video processing unit, can finish selection, so the utility model needn't be provided with the matrix switch unit by software to outputting video signal.
The utlity model has the advantage of simulation output simple in structure, as can to support the various video compression standard.
Description of drawings
Fig. 1 is the formation block diagram of dedicated decoders of the prior art;
Fig. 2 is the formation block diagram of PC decoding technique of the prior art;
Fig. 3 is a The general frame of the present utility model;
Fig. 4 is the utility model example structure schematic block diagram;
Embodiment
With reference to the accompanying drawings, the utility model is further described:
Fig. 4 is the embodiment block diagram that the utility model embodiment adopts the video decode card of PCI-Express interface.
Described high-speed data channel is connected with described video processing unit by the PCI-Express interface unit on the integrated circuit board.
Decoded yuv data is transferred to integrated circuit board by PCI-Express, PCI-Express device on the integrated circuit board is connected with the video processing unit of band DRAM by PCI, PCI-Express interface of this example connects the video processing unit of two band DRAM, each video processing unit is provided with the two-path video signal output part, respectively with corresponding D/A change-over circuit connection.
This device can be by the decoded high bandwidth continuous numeral (video data that be reduced into yuv data of PCI-Express bus reception from the general decoding processor, the DRAM of video processing unit is used for receiving, storing above-mentioned data, video processing unit is handled and is changed data, then isolated digital video signal is outputed to corresponding D/A converter respectively, each road D/A converter converts digital video signal to analog signal, the output analog video signal can directly show on TV or display.
PCI-Express interface on each integrated circuit board can connect the video processing unit of two band DRAM, owing to adopted the PCI-Express bussing technique, a PC can be installed a plurality of integrated circuit boards, increases the quantity that connects video processing unit, supports a plurality of display work.
Owing to the utlity model has above-mentioned functions, can receive the vision signal of the different video compression standard that multichannel decoded by general processor simultaneously, and each corresponding road video analog signal of output, self needn't be provided with the decoding device to different compression standard vision signals, also the matrix commutation circuit needn't be set, so have simple in structure and can support the advantage of various video compression standard simulation output.
This routine video processing unit adopts the TMS320DM64x series DSP, also can adopt PNX-1500 series DSP, PNX-1700 series DSP, PNX-1000 series DSP or PNX-1900 series DSP etc.
The above; it only is preferred embodiment of the present utility model; be not that the utility model is done any pro forma restriction; every foundation technical spirit of the present utility model all still belongs to the protection range of technical solutions of the utility model to any simple modification, equivalent variations and modification that above embodiment did.
Claims (4)
1, a kind of analogue output unit of supporting the various video compression standard comprises: video processing unit and the multichannel D/A change-over circuit of high-speed data channel, band DRAM is characterized in that:
Described high-speed data channel, the digital of digital video data that the high bandwidth of bus input is continuous is transferred to the video processing unit of described band DRAM by high speed data bus;
The video processing unit of described band DRAM receives, stores above-mentioned digital video signal stream, obtains the multipath digital video signal by separating reduction, and corresponding described D/A change-over circuit is handled and outputed to these signals respectively;
Described multichannel D/A change-over circuit is exported the corresponding simulating vision signal respectively.
2, the analogue output unit of support various video compression standard according to claim 1, it is characterized in that: described high-speed data channel is transferred to video processing unit with the continuous digital of digital video data of high bandwidth of the yuv data form after the decoding reduction of bus input by high speed data bus.
3, the analogue output unit of support various video compression standard according to claim 1 is characterized in that: described high-speed data channel is connected with described video processing unit by the PCI-Express interface unit on the integrated circuit board.
4, according to the analogue output unit of the described support various video of the arbitrary claim of claim 1-3 compression standard, it is characterized in that: described video processing unit is the TMS320DM64x series DSP, or PNX-1500 series DSP, or PNX-1700 series DSP, or PNX-1000 series DSP, or PNX-1900 series DSP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200073731U CN201226564Y (en) | 2008-03-27 | 2008-03-27 | Analogue output apparatus supporting various video compression standard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200073731U CN201226564Y (en) | 2008-03-27 | 2008-03-27 | Analogue output apparatus supporting various video compression standard |
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| Publication Number | Publication Date |
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| CN201226564Y true CN201226564Y (en) | 2009-04-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008200073731U Expired - Lifetime CN201226564Y (en) | 2008-03-27 | 2008-03-27 | Analogue output apparatus supporting various video compression standard |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104010137A (en) * | 2014-06-16 | 2014-08-27 | 李思超 | Method and device for splicing high-definition network videos and displaying high-definition network videos on wall |
-
2008
- 2008-03-27 CN CNU2008200073731U patent/CN201226564Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104010137A (en) * | 2014-06-16 | 2014-08-27 | 李思超 | Method and device for splicing high-definition network videos and displaying high-definition network videos on wall |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Analogue output apparatus supporting various video compression standard Effective date of registration: 20100925 Granted publication date: 20090422 Pledgee: Zhongguancun Beijing science and technology Company limited by guarantee Pledgor: Beijing Hanbanggaoke Digital Technology Co.,Ltd. Registration number: 2010990000896 |
|
| C56 | Change in the name or address of the patentee |
Owner name: BEIJING HANBANG TECHNOLOGY CORP., LTD. Free format text: FORMER NAME: BEIJING HANBANGGAOKE DIGITAL TECHNOLOGY CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 100080 Beijing City, Haidian District Zhongguancun South Street No. 8 Patentee after: Beijing Hanbang Gaoke Digital Technology Co., Ltd. Address before: 100080 Beijing City, Haidian District Zhongguancun South Street No. 8 Patentee before: Beijing Hanbanggaoke Digital Technology Co.,Ltd. |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20120116 Granted publication date: 20090422 Pledgee: Zhongguancun Beijing science and technology Company limited by guarantee Pledgor: Beijing Hanbanggaoke Digital Technology Co.,Ltd. Registration number: 2010990000896 |
|
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 100089 Beijing City, Haidian District Changchun Road No. 11 Building No. 4 room 1-12 on the south side of the podium Patentee after: Beijing Hanbang Gaoke Digital Technology Co., Ltd. Address before: 100080 Beijing City, Haidian District Zhongguancun South Street No. 8 Patentee before: Beijing Hanbang Gaoke Digital Technology Co., Ltd. |
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| CX01 | Expiry of patent term |
Granted publication date: 20090422 |
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| CX01 | Expiry of patent term |