CN201166830Y - Computer keyboard - Google Patents

Abstract

The utility model discloses a computer keyboard which comprises an MCU chip with the USB communication function, peripheral components corresponding to the MCU chip and a PCB board of a PS2 port keyboard, wherein the MCU chip and the corresponding peripheral components are welded with the PCB board. The computer keyboard allows the MCU chip of a USB keyboard to be welded with the original PCB board of the PS2 keyboard, thereby achieving the energy-saving effect.

Description

Computer keyboard

Technical Field

The utility model relates to a calculate the key dish, in particular to calculate key dish with MCU chip that has inside clock generator.

Technical Field

With the popularization and application of computers, computer keyboards become indispensable devices, and PS2 keyboards are widely used nowadays. Meanwhile, with the popularization of a large number of Personal Computers (PCs) supporting Universal Serial Bus (USB), USB has become a standard interface for PCs. At the host (host) end, the newly introduced PC supports almost 100% USB; at the peripheral end, devices using USB interfaces are increasing, so USB keyboards are also widely used. The USB interface has the advantages of hot plug, unified standard, capability of connecting various devices and the like. Therefore, USB keyboards are also becoming the focus of attention.

For any type of keyboard, a keyboard MCU (micro controller unit) chip is included to control the scanning of the keyboard, etc., and the peripheral components corresponding thereto, which are then soldered to a keyboard PCB (printed circuit board) to form a complete keyboard. Fig. 1 shows a keyboard structure of the PS2 interface. Including an MCU core, ROM, and an oscillator for providing a clock. The MCU core reads the instruction set in the ROM to scan the keyboard array, and the clock of the MCU core is provided by the oscillator. As can be seen: the oscillator comprises an amplifier inside the chip, the input and output of the amplifier are electrically connected to two points of a PAD (A, B) on the chip, when the amplifier is welded with a PCB, the amplifier is respectively welded on two PIN (PINs) of OSCI and OSCO, then the OSCI and OSCO are respectively connected by a capacitor, the other end of the capacitor is connected to the ground, and the structure provides a clock through an external crystal oscillator; those skilled in the art will appreciate that a PS2 keyboard may also provide a clock through an RC oscillator, as shown in fig. 2: the oscillator comprises a ring oscillator with a bias control end inside a chip, wherein the bias control end of the ring oscillator is connected to a PAD (PAD) B point of the chip, when a PCB is welded, the ring oscillator is welded to a PIN (PIN) of OSCO, the OSCO is connected with a bias control resistor (R) to the ground, the oscillation frequency can be adjusted by adjusting the resistor, and the clock frequency provided by the RC oscillator is relatively low in precision.

For the USB keyboard of the prior art, an external crystal oscillator must be used as a clock source because of the high requirement for clock accuracy. The MCU chip also comprises a USB SIE (serial interface engine) for realizing the USB function, and the D + and D-ends of the USB SIE are respectively connected with two output ends of clk and data of the MCU core so as to output DP _ clk and DM _ data. The MCU core is connected with the ROM. For the USB keyboard, because the requirement on the clock precision is high, an external crystal oscillator must be used as a clock source; in addition, an LDO (linear regulator) circuit unit is required to provide a power supply, here 3.3V. Since the LDO needs a PAD electrically connected to an external capacitor to ground, compared to the PCB of the PS2 keyboard, the PCB of the existing USB keyboard needs to add a PIN for the PAD. So that an additional PCB needs to be provided if it is constructed in accordance with the design.

As described above, since the MCU of the USB interface is structurally different from the MCU of the PS2 interface, if the USB keyboard is used, the PCB of the USB keyboard corresponding to the MCU needs to be manufactured again, which obviously causes a waste of resources, and the cost of the USB keyboard is increased accordingly.

SUMMERY OF THE UTILITY MODEL

In order to achieve the above object, the utility model provides a computer keyboard, including a MCU chip that has USB communication function, corresponding peripheral components and parts with it, a PS2 interface keyboard PCB board, MCU chip and corresponding peripheral components and parts with it weld on the PCB board.

Wherein,

the MCU chip comprises an MCU kernel, an internal clock generator for providing a clock, an SIE for realizing the communication between the keyboard and the USB, a ROM for storing instructions and an LDO for supplying power to the MCU chip;

the DATA end and the CLK end of the MCU kernel are respectively connected with the SIE end and the D + end and the D-end of the clock generator;

the DATA and CLK ends of the MCU chip are welded to the CLK and DATA pins of the PCB, the output end of the LDO is welded to an LDO output pin on the PCB, and then the LDO output pin is connected with a capacitor and grounded.

Wherein,

the MCU chip comprises an MCU kernel, an external crystal oscillator for providing a clock, an SIE for realizing the communication between the keyboard and the USB, a ROM for storing instructions and an LDO for supplying power to the MCU chip;

the DATA and CLK ends of the MCU core are respectively connected with the D + and D-ends of the SIE, the DATA and CLK ends of the MCU are welded on the CLK and DATA pins of the PCB, and the LDO is not led out to lead the PCB but is directly connected with a capacitor to be grounded in the MCU chip.

Wherein,

the MCU chip comprises an MCU kernel, an internal clock generator for providing a clock, an SIE for realizing the communication between the keyboard and the USB, a ROM for storing instructions and an LDO for supplying power to the MCU chip;

the DATA and CLK ends of the MCU core are respectively connected with the SIE end and the D + and D-ends of the clock generator, the DATA and CLK ends of the MCU are welded on the CLK and DATA pins of the PCB, and the LDO is not welded on the PCB by leading out a lead, but is directly connected with a capacitor to be grounded in the MCU chip.

The utility model discloses a calculate the keyboard and can make the MCU chip of USB keyboard weld to the PCB board of original PS2 keyboard on, reach the effect of saving the resource.

Other features, objects and effects of the present invention will become more apparent and understood from the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.

Drawings

FIG. 1 is a first keyboard structure diagram of a PS2 interface of the prior art;

FIG. 2 is a diagram of a second keyboard configuration of the prior art PS2 interface;

FIG. 3 is a diagram of a keyboard structure with a USB interface having an internal clock generator;

FIG. 4 is a schematic diagram of the MCU circuit with the internal clock generator of the present invention;

FIG. 5 is a block diagram showing the structure of a pulse train generating apparatus;

FIG. 6 is a block diagram of a high frequency clock generator;

FIG. 7 is a circuit schematic of an inverter chain;

FIG. 8 is a block diagram of a bandgap reference source;

FIG. 9 is a diagram of a USB waveform monitor;

FIG. 10 shows the SYNC domain structure and the time durations represented by C1 and C2;

FIG. 11 is a block diagram of the pulse generator;

fig. 12, 13 and 14 show pulse sequences generated according to the number of high frequency cycles recorded by C1 and C2 under three different conditions when the USB bus is not flipped;

FIG. 15 shows a pulse sequence generated according to the number of high frequency cycles recorded by C1 and C2 when the USB bus is flipped;

fig. 16 shows a pulse sequence output from the counter 3.

Throughout the above drawings, the same reference numerals indicate the same, similar or corresponding features or functions.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Example one

The utility model discloses the MCU chip of one of them embodiment is through changing external oscillator into the inside clock generator of high accuracy to can not use two PINs of OSCI and OSCO, thereby can reach the effect that the MCU chip can PS2, USB interface PCB board simultaneously under the condition of not modifying PCB.

Fig. 3 shows a structure diagram of the USB keyboard of the present embodiment, and parts that are the same as those in the prior art are not described again. It can be seen that the use of an internal clock generator makes available two PADs on the PCB of the original PS2 keyboard, so that the output of the LDO can be soldered to one of the PADs a or B.

The utility model discloses an internal clock generator, including following three parts, as shown in FIG. 4: a high frequency clock generator; a USB waveform monitor; a pulse generator.

The USB waveform monitor is used for identifying a correct synchronous area and recording the number of high-frequency clock pulses in the synchronous area; the pulse generator finally generates a pulse sequence depending on the number of recorded high frequency clock cycles.

As shown in fig. 5, the high-frequency clock generator is a ring oscillator, and includes: an inverter chain and a bandgap reference source. The inverter chain is composed of an odd number of adjustable current inverters, and the inverter chain is composed of 11 adjustable current inverters in the embodiment, as shown in fig. 6; the bandgap reference source also includes an adjuster, as shown in fig. 7, for adjusting the accuracy of the reference source to within ± 10%. The output clock of the high frequency clock generator is preferably larger than 50MHz, i.e. the period Th is smaller than 20 ns.

The USB waveform monitor is shown in fig. 8 and includes: SYNC (synchronization) region identifier, counter 1 and counter 2.

Because the USB transmission data uses differential mode serial signals (D +, D-) as carriers to transmit binary codes to transmit signals, a data packet is used as the most basic complete information unit and contains a series of data information, and the data packet contains a plurality of fields. The data packet transmitted by USB is first transmitted with a SYNC (Synchronization Sequence field) used for synchronizing the local clock with the input signal, which represents the start of a packet and is located at the beginning of each packet. The structure of SYNC includes logic K, J two states, two data states being two logic levels, which are typically used to exchange differential data in a system. In the logic K state, the logic level value of D + is greater than that of D-, and in the logic J state, the logic level value of D + is less than that of D-, as shown in FIG. 9. The D +, D-signals in the SYNC field are sampled with a high frequency clock generated by a high frequency clock generator, and 2 count values C1, C2 are determined from the signals in the K, J two states, as shown in fig. 9. When the K state starts (D-descending delay is intersected with D + ascending delay), the counter 1 and the counter 2 simultaneously start counting, and when the K state ends (D-ascending delay is intersected with D + descending delay), the counter 1 stops counting, and the counting value is C1; when the next J state ends (D-fall delay intersects D + rise delay), counter 2 stops counting, counting at C2.

The SYNC (SYNC) region identifier monitors the signal for a rollover using a high frequency clock, and when it detects six consecutive upsets in the signal, it assumes that the USB is delivering the correct SYNC region, and then delivers the correct C1 and C2 to the pulse generator.

Thus, C1 recorded by counter 1 is the number of high frequency clock cycles in one K state; the counter 2 records C2 as the number of high frequency clock cycles in one K state and one J state.

It can be understood by those skilled in the art that, when identifying the SYNC region, the clock for sampling K, J two state regions may also use a frequency-divided clock of the high-frequency clock, and the frequency-divided clock can be obtained by adding a frequency divider to the output of the high-frequency clock, which is not described in detail.

The time length represented by C1 is T1 ═ 667ns (since the USB clock frequency is 1.5MHz, the corresponding cycle length is about 667ns), and the time length represented by C2 is T2 ═ 2T1 ═ 1.334 ms. Counter 2 counts a possible error that does not exceed one high frequency clock period, Th, for sampling. When the high frequency clock used for sampling is 50MHz, Th is 20ns, then C2 may produce no more than a percentage of errors

I.e. not more than 1.5%. When the sampling clock frequency is higher, the sampling period is shorter and the error is smaller.

The pulse generator generates a pulse train using the count values C1, C2, as shown in fig. 10. The pulse generator comprises two counters, counter 3 and counter 4. The count value C1 is input to the counter 3, and the count value C2 is input to the counter 4. Two counters determine the period of the pulse sequence according to the number of high-frequency periods recorded by C1 and C2, respectively

Tp1＝C1×Th，Tp2＝C2×Th。

According to the change of the USB state, the generated pulse sequence has the following conditions:

USB non-turnover

In the case of Tp2 being 2 × Tp1, i.e., C2 being 2 × C1, the generated pulse sequence is as shown in fig. 11. The counter 3 generates a time Delay of 1 at the beginning of the pulse sequence according to the value of C1, and then generates 3 or more than 3 pulses, in the figure, for example, 4 pulses are generated, then a time Delay of 2 is generated, the lengths of both Delay1 and Delay2 are greater than Th, and then the counter 3 is cleared to zero and starts counting again. The time length represented by the count value C1 is taken as a scale, that is, the length of Delay1+ Delay2+4 pulses is equal to Tp1, when the counter 3 counts to C1, the counter is cleared, counting is restarted, and the generated pulse sequence is the same as the previous pulse sequence. When the count value of the counter 4 reaches C2, the counters 3 and 4 are cleared at the same time, and are counted again.

In case two, Tp2 > 2 × Tp1, i.e., C2 > 2 × C1, the generated pulse sequence is as shown in FIG. 12. When the counter 3 counts to C1, clearing and restarting counting and generating a second pulse sequence; when the counter 3 counts twice to C1 and starts counting for the third time, a pulse is generated, and when the length of the pulse is Δ t, the counter 4 also counts to C2, and the pulse sequence is generated by clearing the pulse sequence together with the counter 4 and restarting counting regardless of whether the counting of the counter 3 is completed.

Case three, Tp2 < 2 × Tp1, i.e., C2 < 2 × C1, generates a pulse sequence, as shown in fig. 13. At the beginning of the second count, the counter 3 does not complete, but at this time the counter 4 has counted C2, so regardless of whether the count of the counter 3 is complete, the counter 4 is cleared and the count is restarted together with the counter 3 and the next pulse train is generated.

USB has a flip

In case four, as shown in fig. 14, when the USB is flipped, the counter 3 and the counter 4 are cleared and restart counting regardless of whether the counting is completed this time. After USB rollover, the counter 3 and the counter 4 count normally as described above before the next rollover.

As shown in fig. 15, the pulse train output from the counter 3 is set such that a time Td1 represented by a period from the counter 3 counting to n is nTh, which is Delay1, then 3 or more pulses are generated (4 pulses are generated in the figure as an example), and then, until the counter 3 counts to C1, which is Delay 2.

The pulse sequence generated by the internal clock generator is transmitted to the host for synchronization with the host.

As described above, with the present invention, the two outputs D +, D-of the internal clock generator are connected to DP _ clk and DM _ clk, so that no external crystal oscillator is needed to provide the clock signal, therefore, the PINs of OSCI and OSCO on the PCB of PS2 can be eliminated, connecting the LDO output to one of the PINs and then connecting the capacitor to ground. That is, the MCU chip that can achieve a USB keyboard is compatible with the PCB board of PS 2.

Example two

The utility model discloses a MCU chip of second embodiment can also change into the built-in electric capacity ground connection of chip through the external lead wire with the LDO of increase and connect electric capacity ground connection, also can realize using the PCB board of PS2 just can reach the keyboard of USB function. This solution is shown in fig. 16.

As can be seen from the figure, even if an external crystal oscillator is still used as a clock source (of course, the internal clock generator in the first embodiment is also available), the number of PINs used can be saved, and thus the PCB compatibility effect is achieved.

The above description is only a preferred embodiment of the present invention, and those skilled in the art will understand that other internal clock generators may be used as the internal clock source. It should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should be regarded as the protection scope of the present invention.

Claims (4)

1. A computer keyboard comprises an MCU chip with a USB communication function, peripheral components corresponding to the MCU chip and a PS2 interface keyboard PCB, wherein the MCU chip and the peripheral components corresponding to the MCU chip are welded on the PCB.

2. The keyboard of claim 1, wherein:

the MCU chip comprises an MCU kernel, an internal clock generator for providing a clock, an SIE for realizing the communication between the keyboard and the USB, a ROM for storing instructions and an LDO for supplying power to the MCU chip;

the DATA end and the CLK end of the MCU kernel are respectively connected with the SIE end and the D + end and the D-end of the clock generator;

the DATA and CLK ends of the MCU chip are welded to the CLK and DATA pins of the PCB, the output end of the LDO is welded to an LDO output pin on the PCB, and then the LDO output pin is connected with a capacitor and grounded.

3. The keyboard of claim 1, wherein:

the MCU chip comprises an MCU kernel, an external crystal oscillator for providing a clock, an SIE for realizing the communication between the keyboard and the USB, a ROM for storing instructions and an LDO for supplying power to the MCU chip;

the DATA and CLK ends of the MCU core are respectively connected with the D + and D-ends of the SIE, the DATA and CLK ends of the MCU are welded on the CLK and DATA pins of the PCB, and the LDO is not led out to lead the PCB but is directly connected with a capacitor to be grounded in the MCU chip.

4. The keyboard of claim 1, wherein:

the MCU chip comprises an MCU kernel, an internal clock generator for providing a clock, an SIE for realizing the communication between the keyboard and the USB, a ROM for storing instructions and an LDO for supplying power to the MCU chip;

the DATA and CLK ends of the MCU core are respectively connected with the SIE end and the D + and D-ends of the clock generator, the DATA and CLK ends of the MCU are welded on the CLK and DATA pins of the PCB, and the LDO is not welded on the PCB by leading out a lead, but is directly connected with a capacitor to be grounded in the MCU chip.

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