CN201150055Y - A/D converter capable of dynamically collocating self-restruction assembly line - Google Patents
A/D converter capable of dynamically collocating self-restruction assembly line Download PDFInfo
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- CN201150055Y CN201150055Y CNU2007200888263U CN200720088826U CN201150055Y CN 201150055 Y CN201150055 Y CN 201150055Y CN U2007200888263 U CNU2007200888263 U CN U2007200888263U CN 200720088826 U CN200720088826 U CN 200720088826U CN 201150055 Y CN201150055 Y CN 201150055Y
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Abstract
The utility model discloses a converter which can dynamically configure the mode number of the self-restructure streamline. The converter comprises a restructure configuration control circuit, a sampling and holding circuit, a controllable streamline circuit and a time delaying and correcting circuit. The controllable streamline circuit comprises a converter with six to eleven stages, configures and reconstructs the resolution factor digit according to control signals from the restructure configuration control circuit, performs quantification to the voltage magnitude sent from the sampling and holding circuit through grading, and outputs the digital signal of the corresponding digit to be transmitted to the time delaying and correcting circuit. The sampling frequency range and the resolution factor digit of a mode number converter is automatically configured and restructured through the restructure control signal according to the frequency range of the input signal and the requirement on application occasions, to turn off the unused module automatically; when the input signals are respectively positioned at different frequency ranges and obey different protocols, the converter can replace a plurality of traditional mode number converters to convert analog signals into digital signals, therefore, the reusability of the circuit is enhanced, and the converter is favorable for reducing the chip area and the power consumption.
Description
Technical field
The utility model belongs to technical field of integrated circuits, is specifically related to a kind of self-reconstruction assembly line A/D converter capable of dynamic configuration, and it is particularly useful for the communications field.
Background technology
Analog to digital converter is widely used in instrument, input and processing, image processing, multimedia and field such as communicate by letter, and can see its figure in nearly all electronic product relevant with analog signal.Different fields is to the performance requirement difference of analog to digital converter, so the structure of analog to digital converter is also corresponding different.For the design of analog to digital converter, speed, precision and power consumption are the main Several Factors of considering; But this three also conditions each other, and exists compromise between them.Because the pipeline organization analog to digital converter has obtained well compromise at aspects such as chip area, speed, precision, power consumption and design efficiencies, therefore the analog to digital converter speed and the higher communications field of required precision are being obtained using widely.
Present most production line analog-digital converter all is with constant sample frequency and constant resolution work, also promptly under certain specific incoming frequency situation with a kind of constant pattern work; There is the application scenario of multiple frequency range input signal in this for those, just needs multiple sample frequency and the different analog to digital converter of resolution to be used accordingly.For example in the WLAN (wireless local area network) application, there are different consensus standards such as IEEE 802.11a, IEEE 802.11b, IEEE 802.11g etc., the input signal frequency range that they allowed, modulation technique, data transmission rate etc. all exist very big difference, and correspondingly the requirement to analog to digital converter sample frequency and resolution also all is different; For compatible these standards, standard transceiver more than also just correspondingly needs a plurality of different analog to digital converters.As Alireza Shirvani, Derek Cheung, Randy Tsang, Shafiq Jamal, ThomasCho, Xiaodong Jin, " A dual-band triple-mode SoC for 802.11a/b/gEmbedded WLAN in 90nm CMOS " (the 90nm CMOS two waveband triplex mode Soc chip that is used for 802.11a/b/g embedded radio local area network (LAN)) that Yonghua Song etc. delivers on IEEE 2006Custom Intergrated CircuitsConference (CICC), it has adopted two analog to digital converters at 2.4GHz and two different frequency range scopes of 5GHz.Though adopt two analog to digital converters can well solve the compatibling problem of 2.4GHz and 5GHz frequency band signals, this has also brought problem: not only cause the increase of chip area, and will not cause the power consumption that there is no need simultaneously in data transmission rate; When increasing, not two, but when a plurality of, just need the more analog to digital converter of more number that this will cause the increase of SOC chip area and the increase of power consumption along with the frequency range number.
Summary of the invention
The purpose of this utility model is for a kind of self-reconstruction assembly line A/D converter capable of dynamic configuration is provided, this analog to digital converter can be according to the frequency range of input signal and the difference of application scenario, dynamically configuration and the size of reconstruct analog to digital converter sample frequency and the figure place of resolution can reduce power consumption simultaneously.
The self-reconstruction assembly line A/D converter capable of dynamic configuration that the utility model provides is characterized in that: it comprises reconstruct configuration control circuit, first sampling hold circuit, controlled flow line circuit and delay correction circuit;
Reconstruct configuration control circuit carries out dynamic-configuration and reconstruct according to the reconstruct control signal and the clock signal that receive to the sample frequency size and the resolution figure place of production line analog-digital converter, produce one group of non-overlapping clock signal and one group of control signal, and send first sampling hold circuit, controlled flow line circuit and delay correction circuit respectively to;
First sampling hold circuit receives the analog signal to be converted of outside input, the non-overlapping clock signal of utilizing reconstruct configuration control circuit to provide, to the input analog signal sampling to be converted and keep half period, and give controlled flow line circuit with the magnitude of voltage that keeps, first sampling hold circuit is in work or off state according to the control signal that reconstruct configuration control circuit provides;
Controlled flow line circuit comprises i-1 level transducer, it is according to the control signal from reconstruct configuration control circuit, the resolution figure place is configured and reconstruct, and the magnitude of voltage of first sampling hold circuit being sent here according to the resolution figure place after the configuration reconstruct carries out scalar quantization, export the digital signal of corresponding figure place, and send delay correction circuit to;
Delay correction circuit receives from the non-overlapping clock signal of reconstruct configuration control circuit and from the digital signal of controlled flow line circuit, the digital signal of the band redundant digit of transducers at different levels output in the controlled flow line circuit is delayed time and proofreaied and correct, export the digital signal of one group of corresponding figure place.
The utlity model has very big dynamic-configuration from reconstruct, so-called dynamic-configuration is meant that sample frequency size of the present utility model and resolution figure place can automatically be configured under the effect of reconstruct control signal; So-called be meant that from reconstruct resolution figure place of the present utility model can dispose the control signal that control circuit produces by reconstruct and selectively be reconstructed, and can reduce power consumption.Superiority of the present utility model just is, can make the analog signal that severally is in the different frequency range scope, follows different protocol standards use same analog to digital converter just can be converted into digital signal, and sample frequency size and resolution figure place can dynamically dispose and reconstruct by the reconstruct configuration control signal, after this external whole analog-to-digital conversion is finished, can also automatically turn-off analog to digital converter by the reconstruct configuration control signal, to reduce power consumption.Under a plurality of input band range applications occasions, the utility model is compared with the implementation of an analog to digital converter with each frequency range, can reduce SoC area of chip and power consumption effectively.
Description of drawings
Fig. 1 is the structural representation of the utility model self-reconstruction assembly line A/D converter capable of dynamic configuration;
Fig. 2 is the structural representation of reconstruct configuration control circuit among Fig. 1;
Fig. 3 is the structural representation of single-stage converter among Fig. 1;
Fig. 4 is the application example figure of the utility model self-reconstruction assembly line A/D converter capable of dynamic configuration.
Embodiment
Below in conjunction with accompanying drawing and example the utility model is described in further detail.
The sample frequency of self-reconstruction assembly line A/D converter capable of dynamic configuration and resolution figure place can be according to the frequency range of input signal and application scenario different, C1 dynamically disposes and reconstruct by the reconstruct control signal.As shown in Figure 1, the utility model analog to digital converter comprises reconstruct configuration control circuit 1, first sampling hold circuit 2, controlled flow line circuit 3 and delay correction circuit 4.This analog to digital converter is at first under the effect of reconstruct control signal C1, produce sample frequency and the clock signal of one group of non-overlapping clock signal in conjunction with clock signal C 2 by reconstruct configuration control circuit 1 as whole analog to digital converter, produce one group of control signal simultaneously and come resolution figure place (6～i position analog to digital converter, wherein i can get 12,11,7 equivalences) be configured and reconstruct, first sampling hold circuit 2 is sampled according to the analog signal C3 of the sample frequency that is disposed to input afterwards, and give controlled flow line circuit 3 with its sampled result, controlled flow line circuit 3 is changed the input analog signal according to clock signal after the configuration reconstruct and resolution figure place, its transformation result produces the digital signal D1 output of corresponding figure place after delay correction circuit 4 is delayed time alignment and figure adjustment.Below the each several part module in the self-reconstruction assembly line A/D converter capable of dynamic configuration is described in further detail.
The input signal of reconstruct configuration control circuit 1 is reconstruct control signal C1 and the clock signal C2 from the system outside; According to reconstruct control signal C1 and clock signal C 2, the sample frequency size and the resolution figure place of 1 pair of production line analog-digital converter of reconstruct configuration control circuit are carried out dynamic-configuration and reconstruct, one group of non-overlapping clock signal and one group of control signal have been produced, and send first sampling hold circuit 2, controlled flow line circuit 3 and delay correction circuit 4 respectively to, as their clock signal and control signal.Under different input signal frequency ranges and application scenario, reconstruct configuration control circuit 1 can produce the non-overlapping clock signal and the different control signals of different frequency, thereby realizes dynamic-configuration and reconstruct to the sample frequency and the resolution figure place of analog to digital converter.
First sampling hold circuit 2 receives the analog signal C3 to be converted of outside input, and the non-overlapping clock signal and the control signal that dispose control circuit 1 from reconstruct, its major function is that the analog signal C3 to be converted to input samples and keeps the clock cycle half, and give controlled flow line circuit 3 with the magnitude of voltage that keeps, also be about to continually varying analog signal C3 discretization.Control the frequency that 2 pairs of inputs of first sampling hold circuit analog signal C3 samples from the non-overlapping clock signal of reconstruct configuration control circuit 1.Then control the operating state of first sampling hold circuit 2 from the control signal of reconstruct configuration control circuit 1, during operate as normal, first sampling hold circuit 2 is sampled to analog signal C3 when clock signal is height (perhaps low) level, when clock signal is low (perhaps high) level sampled value is kept half the clock cycle; When control signal was effective, first sampling hold circuit 2 is in did not work and off state, to save power consumption.
The input signal of controlled flow line circuit 3 is from the analog voltage of first sampling hold circuit 2 and from the non-overlapping clock signal and the control signal of reconstruct configuration control circuit 1, its major function is according to the control signal from reconstruct configuration control circuit 1, operating state by corresponding module in the control circuit, thereby the resolution figure place to production line analog-digital converter is configured and reconstruct, the magnitude of voltage of first sampling hold circuit 2 being sent here according to the resolution figure place that is disposed carries out scalar quantization afterwards, export the digital signal of corresponding figure place, and send delay correction circuit 4 to.
Controlled flow line circuit 3 comprises i-1 level transducer, and correspondence is provided with i-5 switch, and wherein, the span of i is 7～12.I got 12 o'clock, and controlled flow line circuit 3 can be realized 6～12 configuration and the reconstruct of totally 7 kinds of different resolution figure places; When i got 11, controlled flow line circuit 3 can be realized 6～11 configuration and the reconstruct of totally 6 kinds of different resolution figure places; When i got 10, controlled flow line circuit 3 can be realized 6～10 configuration and the reconstruct of totally 5 kinds of different resolution figure places; When i got 9, controlled flow line circuit 3 can be realized 6～9 configuration and the reconstruct of totally 4 kinds of different resolution figure places; When i got 8, controlled flow line circuit 3 can be realized 6～8 configuration and the reconstruct of totally 3 kinds of different resolution figure places; When i got 7, controlled flow line circuit 3 can be realized 6,7 configuration and the reconstruct of totally 2 kinds of different resolution figure places.
Getting 12 with i below is the concrete formation that example illustrates controlled flow line circuit 3.As shown in Figure 1, controlled flow line circuit 3 comprise the 1st grade of transducer 3A, the 2nd grade of transducer 3B ..., the 7th grade of transducer 3G ..., the 10th grade of transducer 3J, the 11st grade of transducer 3K and switch S 1, S2 ..., S7.
The input signal of the 1st grade of transducer 3A is from the non-overlapping clock signal of reconstruct configuration control circuit 1 and control signal and from the sampling retention value of first sampling hold circuit 2, its major function is that the sampling retention value of importing is quantized, produce one group of digital signal that has redundant digit of giving delay correction circuit 4, produce a surplus gain signal of giving the next stage transducer simultaneously.Control the operating state of the 1st grade of transducer from the control signal of reconstruct configuration control circuit 1, during operate as normal, the 1st grade of transducer directly quantizes the input analog signal of sending here through switch, and gives corresponding next stage circuit with its output; When control signal was effective, the 1st grade of transducer is in did not work and off state, to save power consumption.
The 2nd grade of transducer 3B ..., the 10th grade of transducer 3J 26S Proteasome Structure and Function just the same with the 1st grade of transducer 3A, their input signal all correspondingly is from the non-overlapping clock signal of reconstruct configuration control circuit 1 and control signal and from the surplus gain signal of front one-level transducer, they also all are that the analog signal of importing is quantized, and produce the one group of digital signal that has redundant digit and surplus gain signal of giving the next stage transducer of giving delay correction circuit 4.Wherein there are two kinds of situations in the input analog signal of the 2nd grade of transducer 3B～7th grade transducer 3G according to the difference of the control signal that disposes control circuit 1 from reconstruct: a kind of situation is the switch conduction that links to each other with transducer input at the corresponding levels, directly the analog signal from first sampling hold circuit 2 is quantized, and give corresponding next stage circuit the result; Another kind of situation then is that the switch that links to each other with transducer input at the corresponding levels disconnects, and directly the analog signal that front one-level transducer is sent here quantizes, and gives corresponding next stage circuit with the result.The operating state of the 2nd grade of transducer 3B～10th grade transducer 3J is subjected to the control from reconstruct configuration control circuit 1 control signal equally, and during operate as normal, transducers at different levels quantize the analog signal of input, and give corresponding next stage circuit with its output; When control signal was effective, transducer then is in did not work and off state, to save power consumption.
The 11st grade of transducer 3K is a complete parallel analog to digital converter, its input signal is from the non-overlapping clock signal of reconstruct configuration control circuit 1 and control signal and from the surplus gain signal of the 10th grade of transducer 3J, its major function is exactly that analog signal to input quantizes, produce one group give delay correction circuit 4 not with the digital signal of redundant digit.The operating state of the 11st grade of transducer 3K is subjected to the control from reconstruct configuration control circuit 1 control signal equally, during operate as normal, the analog signal of importing is quantized; When control signal is effective, then is in and does not work and off state.
When control signal configuration and reconstruct 12 bit resolutions, the analog signal that first sampling hold circuit 2 is sent here is directly given the 1st grade of transducer 3A through switch S 1, while cut-off switch S2～S7, after converting, the 1st grade of transducer 3A produce one group of digital signal of giving delay correction circuit 4, produce a surplus gain signal simultaneously and give the next stage transducer as its input signal, by that analogy, convert until the 11st grade of transducer 3K; When control signal configuration and reconstruct 11 bit resolutions, the analog signal that first sampling hold circuit 2 is sent here is directly given the 2nd grade of transducer through switch S 2, disconnect S1, S3～S7 simultaneously, and make the 1st grade of transducer 3A be in off position to save power consumption, the 2nd grade of transducer 3B changes the analog signal of input and produces the set of number signal, produce a surplus gain signal simultaneously and give the next stage transducer, by that analogy, convert until the 11st grade of transducer 3K as its input signal; When control signal configuration and reconstruct 10 bit resolutions, then the analog signal that first sampling hold circuit 2 is sent here is directly given the 3rd level transducer through switch S 3 and is changed, disconnect S1, S2, S4～S7 simultaneously, and make the 1st grade of transducer 3A and the 2nd grade of transducer 3B be in off position; When control signal configuration and reconstruct 9 bit resolutions, then the analog signal that first sampling hold circuit 2 is sent here is directly given the 4th grade of transducer through switch S 4 and is changed, disconnect S1～S3, S5～S7 simultaneously, and make the 1st grade of transducer 3A～3rd level transducer be in off position; When control signal configuration and reconstruct 8 bit resolutions, then the analog signal that first sampling hold circuit 2 is sent here is directly given the 5th grade of transducer through switch S 5 and is changed, disconnect S1～S4, S6, S7 simultaneously, and make the 1st grade of transducer 3A～4th a grade transducer be in off position; When control signal configuration and reconstruct 7 bit resolutions, then the analog signal that first sampling hold circuit 2 is sent here is directly given the 6th grade of transducer through switch S 6 and is changed, disconnect S1～S5, S7 simultaneously, and make the 1st grade of transducer 3A～5th a grade transducer be in off position; When control signal configuration and reconstruct 6 bit resolutions, then the analog signal that first sampling hold circuit 2 is sent here is directly given the 7th grade of transducer 3G through switch S 7 and is changed, disconnect S1～S6 simultaneously, and make the 1st grade of transducer 3A～6th a grade transducer be in off position.
The i value is 11,10 ..., 7 o'clock, the concrete configuration of the resolution figure place of controlled flow line circuit 3 and reconstruct situation and i value are that 12 o'clock concrete configuration and reconstruct situation is similar.
The input signal of delay correction circuit 4 is from the non-overlapping clock signal of reconstruct configuration control circuit 1 and from the digital signal of controlled flow line circuit 3, its major function is that the digital signal of the band redundant digit of transducer outputs at different levels in the controlled flow line circuit 3 is delayed time, thereby make these digital signals arrive digital correction circuit synchronously and proofread and correct, the digital signal of final one group of corresponding figure place of output (6～i position), and the baseband processor that sends the back to is done further processing.Because transducers at different levels in the controlled flow line circuit 3 are alternations under the control of non-overlapping clock, one-level keeps (perhaps sampling) after when also being previous stage sampling (perhaps maintenance), and previous stage sampling (perhaps keeping) and back one-level keep (perhaps sampling) always to carry out simultaneously, the back one-level just has the time-delay of half clock cycle with respect to previous stage like this, for the digital signal that makes every grade of transducer output arrives digital correction circuit synchronously just must be to the digital signal that more preceding transducers at different levels the are exported alignment of delaying time; Digital correction circuit then can be eliminated imbalance and the error that exists in the analog to digital converter to a great extent, thereby makes analog to digital converter reach higher precision.
As shown in Figure 2, reconstruct configuration control circuit 1 comprises register reconstruct control circuit 11, sample frequency configuration circuit 12 and resolution configuration circuit 13, and they can be realized by concrete sequential logical circuit and combinational logic circuit.Register reconstruct control circuit 11 mainly produces a configuration set signal according to the reconstruct control signal C1 that imports and gives sample frequency configuration circuit 12 and resolution configuration circuit 13; Sample frequency configuration circuit 12 is main according to producing one group of non-overlapping clock signal from the configuration signal of register reconstruct control circuit 11 and the clock signal C 2 of input, give first sampling hold circuit 2, controlled flow line circuit 3, delay correction circuit 4, as their clock signal, and reach the size of dynamic-configuration analog to digital converter sample frequency by the frequency of controlling non-overlapping clock signal; Resolution configuration circuit 13 is main according to the configuration signal from register reconstruct control circuit 11, produce one group of control signal, give first sampling hold circuit 2, controlled flow line circuit 3, and control the operating state of corresponding module in these circuit, thereby realize the dynamic-configuration and the reconstruct of analog-to-digital converter resolution figure place by this group signal.
As shown in Figure 3, each grade transducer all comprises second sampling hold circuit 21, sub-adc converter 22, digital to analog converter 23, subtracter 24 and residue-gain-circuit 25 among the 1st grade of transducer 3A～i-2 level transducer 3J.Wherein: second sampling hold circuit 21 mainly is to the analog signal sampling of input and keeps, and gives subtracter 24 with its sampling retention value afterwards; Sub-adc converter 22 is mainly carried out analog-to-digital conversion to the analog signal of input, produces one group of digital signal that has redundant digit correspondingly, and gives delay correction circuit 4 and digital to analog converter 23 with it; Digital to analog converter 23 mainly is that the digital signal that sub-adc converter 22 is sent here is changed, and produces an analog signal correspondingly, and gives subtracter 24 with it; Subtracter 24 mainly is that the analog signal that analog signal that second sampling hold circuit 21 is sent here and digital to analog converter 23 are sent here is subtracted each other, and obtains a surplus, it is given residue-gain-circuit 25 again; Residue-gain-circuit 25 mainly is that the residual signal that subtracter 24 is sent here is amplified, and obtains a surplus gain signal and gives the next stage transducer.
Disposed of in its entirety flow process of the present utility model is as follows: at first, reconstruct control signal C1 among Fig. 1 gives register reconstruct control circuit 11, produce a configuration set signal, this configuration signal produces one group of non-overlapping clock signal in conjunction with clock signal C 2 after sample frequency configuration circuit 12 is handled, as the clock signal of whole analog to digital converter, and realize the configuration of sample frequency size by the frequency of controlling non-overlapping clock signal; Meanwhile, configuration signal produces one group of control signal after resolution configuration circuit 13 is handled, control the operating state of transducers at different levels in first sampling hold circuit 2 and the controlled flow line circuit 3, thereby realize the configuration and the reconstruct of production line analog-digital converter resolution figure place; Afterwards, first sampling hold circuit 2 is sampled to the analog signal C3 that imports with the non-overlapping clock signal after the configuration and is kept, and the retention value of will sampling is given controlled flow line circuit 3; The sampling retention value that controlled flow line circuit 3 is received according to the resolution figure place butt joint after the configuration reconstruct quantizes, wherein, that one-level transducer that receives the analog signal that first sampling hold circuit 2 sends here carries out rudenss quantization by sub-adc converter 22 earlier, output two digits signal is given delay correction circuit 4, simultaneously this two digits signal after the digital to analog converter conversion analog signal and the analog signal of second sampling hold circuit, 21 maintenances after subtracter 24 subtracts each other, obtain a residual signal, again after residue-gain-circuit 25 amplifies, give the next stage transducer and carry out rudenss quantization again, by that analogy, convert output two digits signal until i-1 level production line 3K; Then, the digital signal that transducers at different levels are sent here in 4 pairs of controlled flow line circuits 3 of the delay correction circuit alignment of delaying time makes it arrive digital correction circuit synchronously and proofreaies and correct, and finally exports 6～i position digital signal corresponding D1.
As shown in Figure 4, the example of the utility model self-reconstruction assembly line A/D converter capable of dynamic configuration application is:
In wireless transceiver based on IEEE 802.11a/b/g agreement, input radio frequency signal C4 may be the 2.4GHz signal that meets IEEE 802.11b, IEEE 802.11g agreement, also may be the 5GHz signal that meets IEEE802.11a, IEEE 802.11g agreement.Input radio frequency signal C4 at first carries out mode detection, is in the 2.4GHz frequency range or is in the 5GHz frequency range thereby judge this input radio frequency signal, and produce a reconstruct control signal C1 and give self-reconstruction assembly line A/D converter capable of dynamic configuration; Meanwhile, radiofrequency signal after the mode detection is also given low noise amplifier and is amplified, radiofrequency signal after amplifying is given frequency mixer again, analog signal after the frequency mixer frequency reducing is given variable gain amplifier again, obtains analog signal C3 and gives self-reconstruction assembly line A/D converter capable of dynamic configuration after variable gain amplifier is handled; The reconstruct control signal C1 that self-reconstruction assembly line A/D converter capable of dynamic configuration (getting 12 with i is example) is sent here according to mode detection comes automatic sample frequency size and resolution figure place to analog to digital converter to be configured: if input signal is to be in the 2.4GHz frequency range, then produce the clock signal of the non-overlapping clock signal of one group of 40MHz as whole analog to digital converter by register reconstruct control circuit 11 and sample frequency configuration circuit 12, and by one group of control signal of resolution configuration circuit 13 generations, make switch S 1, S2, S4～S7 disconnects, make the 1st grade of transducer 3A and the 2nd grade of transducer 3B be in off position simultaneously, the sampling retention value of first sampling hold circuit 2 is given the 3rd level transducer through switch S 3 and is changed, giving the next stage transducer again after converting changes, convert until the 11st level production line 3K, give delay correction circuit 4 with the digital signal of 3rd level transducer～11st grade transducer 3K output more afterwards, after time-delay alignment and figure adjustment, obtain 10 final position digital signal D1; If input signal is to be in the 5GHz frequency range, then produce the clock signal of the non-overlapping clock signal of one group of 60MHz as whole analog to digital converter by register reconstruct control circuit 11 and sample frequency configuration circuit 12, and by one group of control signal of resolution configuration circuit 13 generations, make switch S 1～S4, S6, S7 disconnects, make the 1st grade of transducer 3A～4th a grade transducer be in off position simultaneously, the sampling retention value of first sampling hold circuit 2 is given the 5th grade of transducer through switch S 5 and is changed, giving the next stage transducer again after converting changes, convert until the 11st level production line 3K, give delay correction circuit 4 with the digital signal of the 5th grade of transducer～11st grade transducer 3K output more afterwards, after time-delay alignment and figure adjustment, obtain 8 final position digital signal D1.At last, the digital signal D1 that is converted to is fed to baseband processor and does further processing.Original like this 40MHz sample frequency, 10 bit resolutions and 60MHz sample frequency, two different analog to digital converters of 8 bit resolutions of needing, by just being configured, its sample frequency and resolution figure place realized now with a self-reconstruction assembly line A/D converter capable of dynamic configuration, this has greatly reduced wireless transceiver SoC area of chip, simultaneously, turn-offed the circuit module of not using as required in the dynamic-configuration process of analog to digital converter, this has also effectively reduced the power consumption of SoC chip.Though should be an optimization embodiment of choosing with example, but the professional and technical personnel should understand, the utility model is not limited to above-mentioned example, can also realize the dynamic-configuration of sample frequency and resolution figure place in more applications occasion, more frequency range.
Claims (4)
1, a kind of self-reconstruction assembly line A/D converter capable of dynamic configuration is characterized in that: it comprises reconstruct configuration control circuit (1), first sampling hold circuit (2), controlled flow line circuit (3) and delay correction circuit (4);
Reconstruct configuration control circuit (1) carries out dynamic-configuration and reconstruct according to the reconstruct control signal and the clock signal that receive to the sample frequency size and the resolution figure place of production line analog-digital converter, produce one group of non-overlapping clock signal and one group of control signal, and send first sampling hold circuit (2), controlled flow line circuit (3) and delay correction circuit (4) respectively to;
First sampling hold circuit (2) receives the analog signal to be converted of outside input, the non-overlapping clock signal of utilizing reconstruct configuration control circuit (1) to provide, to the input analog signal sampling to be converted and keep half period, and give controlled flow line circuit (3) with the magnitude of voltage that keeps, first sampling hold circuit (2) is in work or off state according to the control signal that reconstruct configuration control circuit (1) provides;
Controlled flow line circuit (3) comprises i-1 level transducer, wherein, and 7≤i≤12; It is according to the control signal from reconstruct configuration control circuit (1), the resolution figure place is configured and reconstruct, and the magnitude of voltage of first sampling hold circuit (2) being sent here according to the resolution figure place after the configuration reconstruct carries out scalar quantization, export the digital signal of corresponding figure place, and send delay correction circuit (4) to;
Delay correction circuit (4) receives from the non-overlapping clock signal of reconstruct configuration control circuit (1) and from the digital signal of controlled flow line circuit (3), the digital signal of the band redundant digit of transducers at different levels output in the controlled flow line circuit (3) is delayed time and proofreaied and correct, export the digital signal of one group of corresponding figure place.
2, self-reconstruction assembly line A/D converter capable of dynamic configuration according to claim 1, it is characterized in that: controlled flow line circuit (3) comprises i-1 level transducer and i-5 switch, according to different control signals, realize the not configuration and the reconstruct of isotopic number resolution of i-5 kind altogether of 6～i position;
The 1st grade of transducer disposes non-overlapping clock signal that control circuit (1) provides according to reconstruct the sampling retention value of first sampling hold circuit (2) that receives quantized, and produces the one group of digital signal that has redundant digit and surplus gain signal of giving the next stage transducer of giving delay correction circuit (4); The 1st grade of transducer disposes the control signal that control circuit (1) provides according to reconstruct, is in work or off state;
The 26S Proteasome Structure and Function of the 2nd grade of transducer to the i-2 level transducer is identical with the 1st grade of transducer, they dispose non-overlapping clock signal that control circuit (1) provides according to reconstruct the surplus gain signal of the front one-level transducer that receives are quantized, and produce the one group of digital signal that has redundant digit and surplus gain signal of giving the next stage transducer of giving delay correction circuit (4); The control signal that the 2nd grade of transducer～i-5 level transducer disposes control circuit (1) and provide according to reconstruct receives the analog signal of sending here from the analog signal or the front one-level transducer of first sampling hold circuit (2); The 2nd grade of transducer～i-2 level transducer disposes the control signal that control circuit (1) provides according to reconstruct, is in work or off state;
I-1 level transducer is a complete parallel analog to digital converter, it disposes non-overlapping clock signal that control circuit (1) provides according to reconstruct the surplus gain signal of the front one-level transducer that receives is quantized, and produces one group of digital signal that does not have redundant digit of giving delay correction circuit (4); I-1 level transducer disposes the control signal that control circuit (1) provides according to reconstruct, is in work or off state;
When control signal configuration and reconstruct i bit resolution, the analog signal of first sampling hold circuit (2) that controlled flow line circuit (3) will receive is directly given the 1st grade of transducer through switch S 1, while cut-off switch S2～Si-5, the 1st grade of transducer changed the analog signal that receives and produced one group of digital signal of giving delay correction circuit (4), produce a surplus gain signal simultaneously and give the next stage transducer as its input signal, by that analogy, convert until i-1 level transducer; When control signal configuration and reconstruct i-1 bit resolution, the analog signal of first sampling hold circuit (2) that controlled flow line circuit (3) will receive is directly given the 2nd grade of transducer through switch S 2, disconnect other switch simultaneously, and make the 1st grade of transducer be in off position, the 2nd grade of transducer changed the analog signal that receives and produced the set of number signal, produce a surplus gain signal simultaneously and give the next stage transducer as its input signal, by that analogy, convert until i-1 level transducer; ...; When control signal configuration and reconstruct 6 bit resolutions, the analog signal of first sampling hold circuit (2) that controlled flow line circuit (3) will receive is directly given i-5 level transducer through switches Si-5, disconnect S1～Si-6 simultaneously, and make the 1st grade of transducer to the i-6 level transducer be in off position, i-5 level transducer is changed the analog signal that receives and is produced the set of number signal, produce a surplus gain signal simultaneously and give the next stage transducer as its input signal, by that analogy, convert until i-1 level transducer.
3, self-reconstruction assembly line A/D converter capable of dynamic configuration according to claim 2 is characterized in that: the transducers at different levels in the controlled flow line circuit (3) include second sampling hold circuit (21), sub-adc converter (22), digital to analog converter (23), subtracter (24) and residue-gain-circuit (25);
Second sampling hold circuit (21) is used for the analog signal sampling of input and keeps, and gives subtracter (24) with its sampling retention value afterwards;
Sub-adc converter (22) is used for the analog signal of input is carried out analog-to-digital conversion, produces one group of digital signal that has redundant digit correspondingly, and gives delay correction circuit (4) and digital to analog converter (23) with it;
Digital to analog converter (23) is used for the digital signal that sub-adc converter (22) is sent here is changed, and produces an analog signal correspondingly, and gives subtracter (24) with it;
Subtracter (24) is used for analog signal that analog signal that second sampling hold circuit (21) is sent here and digital to analog converter (23) send here and subtracts each other and obtain a residual signal, and gives residue-gain-circuit (25) with it;
Residue-gain-circuit (25) is used for the residual signal that subtracter (24) is sent here is amplified, and obtains a surplus gain signal and gives the next stage transducer.
4, according to claim 1,2 or 3 described self-reconstruction assembly line A/D converter capable of dynamic configuration, it is characterized in that: reconstruct configuration control circuit (1) comprises register reconstruct control circuit (11), sample frequency configuration circuit (12) and resolution configuration circuit (13);
Register reconstruct control circuit (11) produces a configuration set signal according to the reconstruct control signal of importing and gives sample frequency configuration circuit (12) and resolution configuration circuit (13);
Sample frequency configuration circuit (12) is according to producing one group of non-overlapping clock signal from the configuration signal of register reconstruct control circuit (11) and the clock signal of input, send first sampling hold circuit (2), controlled flow line circuit (3) and delay correction circuit (4) respectively to, as their clock signal, and come the size of dynamic-configuration ground analog to digital converter sample frequency by the frequency of controlling non-overlapping clock signal;
Resolution configuration circuit (13) is according to the configuration signal from register reconstruct control circuit (11), produce one group of control signal, send first sampling hold circuit (2) and controlled flow line circuit (3) to, control its operating state, realize the dynamic-configuration of analog-to-digital converter resolution figure place.
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| CNU2007200888263U CN201150055Y (en) | 2007-12-07 | 2007-12-07 | A/D converter capable of dynamically collocating self-restruction assembly line |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2007200888263U CN201150055Y (en) | 2007-12-07 | 2007-12-07 | A/D converter capable of dynamically collocating self-restruction assembly line |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109639276A (en) * | 2018-11-23 | 2019-04-16 | 华中科技大学 | DT Doubling Time intertexture current steer type DAC with DDRZ calibration function |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109639276A (en) * | 2018-11-23 | 2019-04-16 | 华中科技大学 | DT Doubling Time intertexture current steer type DAC with DDRZ calibration function |
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