CN201142071Y - 8-digit flash memory microcontroller - Google Patents
8-digit flash memory microcontroller Download PDFInfo
- Publication number
- CN201142071Y CN201142071Y CNU2007201988447U CN200720198844U CN201142071Y CN 201142071 Y CN201142071 Y CN 201142071Y CN U2007201988447 U CNU2007201988447 U CN U2007201988447U CN 200720198844 U CN200720198844 U CN 200720198844U CN 201142071 Y CN201142071 Y CN 201142071Y
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Abstract
The utility model relates to a microcontroller of an 8-bit flash memory, which comprises an 8-bit microprocessor connected with a bus, a FLASH memory, a data memory, four 8-bit programmable input/output parallel ports, three 16-bit timer/ counters, an interrupt nesting unit, a serial port and a special function register. A clock circuit is connected with the microprocessor; an encryption-decryption unit is also connected between the microprocessor and the FLASH memory, and comprises an encryption seed interface circuit, a programming interface circuit, and an address encryption circuit and a data encryption circuit respectively connected with the programming interface circuit, the encryption seed interface circuit and the FLASH memory, and an address decryption circuit and a date decryption circuit respectively connected with the microprocessor and the FLASH memory. The microcontroller of the utility model obviously enhances confidentiality and security of the system.
Description
Technical field
The utility model relates to a kind of presetting apparatus, relates in particular to 8 bit flash memory microcontrollers of a kind of tape program and address encryption.
Background technology
Over nearly 20 years, 8 single-chip microcomputers are because of its price is cheap day by day, function becomes increasingly abundant, power consumption is humble day by day, the exploitation is easy day by day, add being on the increase and the continuous expansion of information peripheral interface of configuration peripheral module in the sheet, and become the focus of industry research and development.
At present, 8 single-chip microcomputers pass through RAM and the Interrupt Process and the serial line interface of 8 bit CPUs, Timer, a constant volume, the development control function provides reliability of system operation, progressively the external interface circuit of TT﹠C system is included in the sheet to realize the function of " microcontroller ".
Wherein 51 single-chip microcomputers are microcontrollers commonly used, be that the monolithic the most widely that uses in the market one of reaches, it is because instruction is simply distinct, powerful, cost performance is higher, and travelling speed is fast, antijamming capability is strong, reliability height, usable range are extremely wide, have in different production, control field extremely widely to use.
But the program of 51 traditional single-chip microcomputers can not be encrypted and/or stored program address can not be encrypted, and therefore has the technological deficiency of confidentiality difference.
The utility model content
The purpose of this utility model provides a kind of 8 bit flash memory microcontrollers with data and address encryption, and prior art microcontroller program can not be encrypted and/or stored program address can not be encrypted, the technological deficiency of confidentiality difference in order to overcome.
To achieve these goals, the utility model provides a kind of 8 bit flash memory microcontrollers, comprise a 8-bit microprocessor that all is connected with bus, a FLASH storer, a data storer, four 8 programmable I/O parallel ports, three 16 bit timings/counters, an interrupt nesting unit, a serial port and a special function register, be connected with a clock circuit on the described microprocessor, also be connected with the encrypting and decrypting unit between described microprocessor and the FLASH storer, it is characterized in that described encrypting and decrypting unit comprises: an encryption seed interface circuit, a DLL (dynamic link library) circuit, respectively with described DLL (dynamic link library) circuit, an address encryption circuit and a data encrypted circuit that the encryption seed interface circuit is connected with the FLASH storer, and an address decrypt circuit and a data encrypted circuit of being connected with the FLASH storer with described microprocessor respectively.
On the basis of technique scheme, also can be connected with the secret grade that is used to be provided with described 8 bit flash memory microcontroller secret grades between described DLL (dynamic link library) circuit and the FLASH program storage register is set.Described FLASH storer also can comprise two programmable safety encipher positions.
On the basis of technique scheme, described encryption seed interface circuit can specifically comprise the receiving element of the encryption seed signal that is used to receive user's input, and is connected with described receiving element be used for random code generator according to described encryption seed signal generation random code.
The utility model is provided with the encrypting and decrypting unit by increasing between the microprocessor CPU of 8 bit flash memory microcontrollers and FLASH storer, the address of this routine data of storage in program and the FLASH storer is carried out the mode of double-encryption by the encrypting and decrypting unit, effectively prevented the leakage of user source code, the problem of the confidentiality difference that the program that solved can not be encrypted and/or stored program address can not be encrypted and cause, the security that has obviously improved system.
Description of drawings
Fig. 1 is the utility model 8 bit flash memory microcontroller architecture synoptic diagram;
Fig. 2 is that structural representation is implemented in the utility model encrypting and decrypting unit first;
Fig. 3 is that structural representation is implemented in the utility model encrypting and decrypting unit second.
Description of reference numerals:
The 1-bus; The 2-microprocessor; The 3-FLASH storer;
The 4-data-carrier store; 5-encrypting and decrypting unit; The 7-Timer;
The programmable I/O parallel port of 6-; 8-interrupt nesting unit;
The 9-serial port; The 10-special function register; The 11-clock circuit;
51-encryption seed interface circuit; 52-DLL (dynamic link library) circuit; 53-address encryption circuit;
54-data encryption circuit; 55-address decrypt circuit; 56-data encryption circuit;
The 57-secret grade is provided with register.
Embodiment
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
Fig. 1 is the utility model 8 bit flash memory microcontroller architecture synoptic diagram.As shown in Figure 1, the utility model 8 bit flash memory microcontrollers comprise: all have the interrupt nesting unit 8 of 6 interrupt sources, serial port (UART) 9, special function register (SFR) 10 with the programmable I/O parallel port of 4, four 8 of the data-carrier stores (RAM) of bus 1 microprocessor linked (CPU) 2, FLASH storer 3,512 bytes 6, three 16 bit timings/7, one in counters.Wherein, also be connected with clock circuit 11 on the microprocessor 2, be connected with encrypting and decrypting unit 5 between microprocessor 2 and the FLASH storer 3.
Fig. 2 is that structural representation is implemented in the utility model encrypting and decrypting unit first.Join illustrated in figures 1 and 2ly, this encrypting and decrypting unit 5 comprises: encryption seed interface circuit 51, DLL (dynamic link library) circuit 52, address encryption circuit 53, data encryption circuit 54, address decrypt circuit 55 and data encryption circuit 56.Wherein, address encryption circuit 53 is connected with DLL (dynamic link library) circuit 52, encryption seed interface circuit 51, FLASH storer 3 and data encryption circuit 54; Data encryption circuit 54 is connected with DLL (dynamic link library) circuit 52, encryption seed interface circuit 51, address encryption circuit 53 and FLASH storer 3; Address decrypt circuit 55 is connected with microprocessor 2, FLASH storer 3 and data decryption circuit 56; Data decryption circuit 56 is connected with microprocessor 2, FLASH storer 3 and address decrypt circuit 55.
Encryption seed interface circuit 51 comprises the receiving element of the encryption seed signal that is used to receive user's input, and is connected with receiving element be used for random code generator according to encryption seed signal generation random code.The receiving element of encryption seed interface circuit 51 receives the encryption seed signal of user's input, this encryption seed signal generates a random code by the random code generator in the encryption seed interface circuit 51, and microprocessor 2 is stored in this random code in the assigned address corresponding memory space of FLASH storer 3 simultaneously.
DLL (dynamic link library) circuit 52 is used to receive the address and the routine data of user's input, and this address and routine data are sent to address encryption unit 53 and DEU data encryption unit 54 respectively.
Address encryption circuit 53 is used to receive the random code of coming the address and sending from encryption seed interface circuit 51 from 52 transmissions of DLL (dynamic link library) circuit, this address and random code are carried out mathematic(al) manipulation according to preset algorithm (as: random code and address code can be carried out the XOR conversion, but be not limited thereto mathematic(al) manipulation) new address of generation, point in the FLASH storer and this new address corresponding address code, and send these new addresses to data encryption circuit 54.
Data encryption circuit 54 is used to receive the random code of coming routine data and sending from encryption seed interface circuit 51 from 52 transmissions of DLL (dynamic link library) circuit, this routine data is carried out mathematic(al) manipulation with random code according to the preset algorithm identical with address encryption, generate a new procedures data code, and this new procedures data code is left in the storage space that the new address after address encryption circuit 53 is encrypted is pointed in the FLASH storer 3.
Address decrypt circuit 55 is used for according to the mathematics inverse transformation of random code and identical preset algorithm the address being decrypted, its principle is: when microprocessor 2 operations, microprocessor 2 reads the random code that is stored in FALSH storer 3 assigned address, address decrypt circuit 55 receives the reference address and the random code of microprocessor 2 outputs, and adopt identical algorithms to carry out the mathematics inverse transformation when this address and random code adopted address encryption, decrypt the program memory address of the FLASH storer 3 of this address correspondence, the address after the deciphering is outputed to data decryption circuit 56.
Data decryption circuit 56 is used for according to the mathematics inverse transformation of random code and identical preset algorithm routine data being decrypted, its principle is: when microprocessor 2 operations, after data decryption circuit 56 receives the deciphering address of random code that microprocessor 2 sends and 55 outputs of address decrypt circuit, read the routine data that is stored under this deciphering address corresponding memory space to FLASH storer 3 according to this deciphering address, and adopt identical algorithms to carry out the mathematics inverse transformation when adopting address encryption according to this encrypted program data and random code, obtain the routine data after the deciphering and send to microprocessor 2.
In the technique scheme, FLASH storer of the present utility model has encryption function, when FLASH is in encrypted state, the MOVC instruction execution that is under an embargo, the data that are stored among the FLASH can not be read out, except ERASE_CHIP and PROGRAM_SEC instruction, all systems programming ISP orders all are under an embargo, all external host orders execution that also all is under an embargo.Address of the present utility model deciphering and routine data deciphering all are to carry out in sheet.The address of the outer output of sheet is a dummy address, and routine data all is dark texts.Therefore can prevent that the source program of the leakage of user source code or the FLASH stored that maloperation causes from being changed or wiping, help improving security.
Fig. 3 is that structural representation is implemented in the utility model encrypting and decrypting unit second.As shown in Figure 3, on the basis of technique scheme, also be connected with the secret grade that is used to be provided with secret grade between FLASH storer 6 and the DLL (dynamic link library) circuit 51 register 57 is set.The setting of register 57 is set by 51 pairs of secret grades of DLL (dynamic link library) circuit, the level of security of the utility model 8 bit flash memory microcontrollers is divided into 3 kinds: first kind, do not encrypt, promptly after the full wafer chip is wiped free of, the safety encipher position is in the state that is not programmed, all encryption functions all do not have open, MOVC and all external hosts, and systems programming ISP instruction can move; Second kind, encrypt, promptly the FLASH storer is lockable, and the MOVC instruction is under an embargo, and systems programming ISP orders all except the CHIP_ERASE instruction all are under an embargo, and except ERASE_CHIP and PROGRAM_SEC instruction, all external host orders all are under an embargo; The third, the special encryption, promptly except the characteristic of all and second kind of encryption, the EA signal also is under an embargo, and all programs are storer operation internally all.
FLASH storer of the present utility model also can use two safety encipher position SB1 and SB2, no matter under what level of security, these two safety encipher positions can be programmed, but in case after being programmed, this process is just irreversible, unless just the last all data of FLASH are all wiped and can be programmed once more.
The utility model is provided with the encrypting and decrypting unit by increasing between the microprocessor CPU of 8 bit flash memory microcontrollers and FLASH storer, the address of this routine data of storage in routine data and the FLASH storer is carried out the mode of double-encryption by the encrypting and decrypting unit, effectively prevented the danger that the source program of the leakage of user source code or the FLASH stored that maloperation causes is changed or wiped, the problem of the confidentiality difference that the program that solved can not be encrypted and/or stored program address can not be encrypted and cause, the security that has obviously improved system.
It should be noted that at last: above embodiment only in order to the explanation the technical solution of the utility model, is not intended to limit; Although the utility model is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that previous embodiment is put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of the utility model embodiment technical scheme.
Claims (4)
1. bit flash memory microcontroller, comprise a 8-bit microprocessor that all is connected with bus, a FLASH storer, a data storer, four 8 programmable I/O parallel ports, three 16 bit timings/counters, an interrupt nesting unit, a serial port and a special function register, be connected with a clock circuit on the described microprocessor, also be connected with the encrypting and decrypting unit between described microprocessor and the FLASH storer, it is characterized in that described encrypting and decrypting unit comprises: an encryption seed interface circuit, a DLL (dynamic link library) circuit, respectively with described DLL (dynamic link library) circuit, an address encryption circuit and a data encrypted circuit that the encryption seed interface circuit is connected with the FLASH storer, and an address decrypt circuit and a data encrypted circuit of being connected with the FLASH storer with described microprocessor respectively.
2. 8 bit flash memory microcontrollers according to claim 1 is characterized in that being connected with between described DLL (dynamic link library) circuit and the FLASH program storage secret grade that is used to be provided with described 8 bit flash memory microcontroller secret grades register are set.
3. 8 bit flash memory microcontrollers according to claim 1 and 2 is characterized in that described FLASH storer comprises two programmable safety encipher positions.
4. 8 bit flash memory microcontrollers according to claim 1, it is characterized in that described encryption seed interface circuit comprises: be used to receive the receiving element of the encryption seed signal of user's input, and is connected with described receiving element be used for random code generator according to described encryption seed signal generation random code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201988447U CN201142071Y (en) | 2007-12-04 | 2007-12-04 | 8-digit flash memory microcontroller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201988447U CN201142071Y (en) | 2007-12-04 | 2007-12-04 | 8-digit flash memory microcontroller |
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| Publication Number | Publication Date |
|---|---|
| CN201142071Y true CN201142071Y (en) | 2008-10-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2007201988447U Expired - Lifetime CN201142071Y (en) | 2007-12-04 | 2007-12-04 | 8-digit flash memory microcontroller |
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| CN (1) | CN201142071Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719098B (en) * | 2009-05-26 | 2011-08-17 | 苏州国芯科技有限公司 | Storage controller of Nandflash chipsets |
| CN102591803A (en) * | 2011-01-17 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Method for protecting data in flash |
| CN106201352A (en) * | 2016-07-07 | 2016-12-07 | 广东高云半导体科技股份有限公司 | The secrecy system of data streaming file and decryption method on non-volatile FPGA sheet |
| CN109656839A (en) * | 2017-10-12 | 2019-04-19 | 意法半导体股份有限公司 | For access encrypted data electronic equipment and corresponding method |
-
2007
- 2007-12-04 CN CNU2007201988447U patent/CN201142071Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719098B (en) * | 2009-05-26 | 2011-08-17 | 苏州国芯科技有限公司 | Storage controller of Nandflash chipsets |
| CN102591803A (en) * | 2011-01-17 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Method for protecting data in flash |
| CN106201352A (en) * | 2016-07-07 | 2016-12-07 | 广东高云半导体科技股份有限公司 | The secrecy system of data streaming file and decryption method on non-volatile FPGA sheet |
| CN109656839A (en) * | 2017-10-12 | 2019-04-19 | 意法半导体股份有限公司 | For access encrypted data electronic equipment and corresponding method |
| CN109656839B (en) * | 2017-10-12 | 2023-10-20 | 意法半导体股份有限公司 | Electronic device for accessing encrypted data and corresponding method |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20081029 |
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| CX01 | Expiry of patent term |