CN201138374Y - Real-time software receiving machine of global position system - Google Patents
Real-time software receiving machine of global position system Download PDFInfo
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- CN201138374Y CN201138374Y CNU2007200762814U CN200720076281U CN201138374Y CN 201138374 Y CN201138374 Y CN 201138374Y CN U2007200762814 U CNU2007200762814 U CN U2007200762814U CN 200720076281 U CN200720076281 U CN 200720076281U CN 201138374 Y CN201138374 Y CN 201138374Y
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Abstract
The utility model relates to navigation and positioning equipment which belongs to the electronic technical field, in particular to a global positioning system real-time software receiver which uses modern scientific and technological means to conduct real-time positioning with the received global positioning system (GPS) signal, and is applied in signal sampling and computer software processing. The utility model consists of a complicated programmable logic device, a bus, an interface, an antenna, a shift register, a memory, a signal sampling and transmitting module including a radio frequency signal sampling module and a serial-to-parallel converting interface module, etc.; the utility model mainly solves the relevant interface technical problems of the signal sampling and transmitting module as well as a high-speed digital signal collection card, etc. The equipment has the advantages of the realization of real-time operation in a Microsoft Windows XP system so as to output positioning results real time, the performance indexes meet the project requirements with quite high precision and sensitivity.
Description
Technical field
The utility model relates to navigation, the positioning equipment of electronic technology field, outstanding a kind of modern means of science and technology of utilizing of purport, by Global Positioning System (GPS) GPS (the Global Positioning System) signal that receives, carry out real-time positioning, be applied to the real-time software receiving machine device of signal sampling and software processing.
Background technology
At present, Global Positioning System (GPS) GPS software receiver has demonstrated the advantage of oneself gradually with its alterability and advantage cheaply.
Present Global Positioning System (GPS) GPS software receiver shortcoming is that the real-time of receiver signal Processing in windowsXP operating system commonly used is poor, positioning result can not in time respond the Doppler shift of satellite-signal, influenced locating accuracy, accomplish that real-time processing often need realize in special real time operating system, influence is promoted.
Summary of the invention
In order to overcome above-mentioned weak point, fundamental purpose of the present utility model aims to provide and a kind ofly realizes by base band relevant treatment part is put in the computing machine fully, promptly the sampled signal of radio frequency (Radio Frequency) end is directly sent into computing machine, finish whole computings by microprocessor then; Adopt the program of Windows operating system to carry out Signal Processing, by signal sampling transport module and high-speed digital signal capture card, by the digital signal acquiring card if sampling signal is sent into relevant interfaces such as calculator memory again, used new digital signal processing algorithm, successfully realized the real time execution of software receiver, reach and to handle and the realization real-time positioning by fast signal, have the global position system real-time software receiving machine of degree of precision and sensitivity again.
The technical problems to be solved in the utility model is: hardware components mainly solves signal sampling transport module and the high-speed digital signal capture card problem of how realizing; How about the if sampling signal is sent into relevant interfacing problems such as calculator memory by the digital signal acquiring card.
The technical scheme that its technical matters that solves the utility model adopts is: this device is by CPLD, bus, interface, antenna, shift register, storer, socket, parts such as A/D and computing machine are formed, be provided with the 32-bit number data acquisition card in the described computing machine, the 32-bit number data acquisition card is inserted on the computer main frame panel peripheral element extension interface PCI slot, send the data to computing machine by the peripheral element extension interface pci bus, this computing machine is by the wireless navigation signal of antenna reception from the global position system GPS satellite, behind the radiofrequency signal sampling module, 2 position digital signals are delivered to string and translation interface module, through string and the output signal of translation interface module by computing machine based on general processor, but not the special-purpose baseband processing chip of global position system GPS carries out the processing of baseband signal, each module combinations is holistic software receiver, and this device comprises at least:
Form by radiofrequency signal sampling module and string and translation interface module in the one signal sampling transport module, the input end of the radiofrequency signal sampling module in antenna and the signal sampling transport module is connected, the radiofrequency signal sampling module is with the wireless navigation signal sampling and the digital-to-analog conversion of antenna input, the I/O of the input/output terminal of radiofrequency signal sampling module and string and translation interface module interconnects, and the output terminal output digital signal transfers of string and translation interface module is to the input end of 32-bit number data acquisition card;
One computer software processing module by sampled signal and local signal relevant treatment and signal capture, tracking, synchronously, the navigation calculation module forms, the input/output terminal of sampled signal and local signal relevant treatment and signal capture, tracking, I/O synchronous, the navigation calculation module interconnect;
One 32-bit number data acquisition card interconnects by the input end of sampled signal in peripheral element extension interface pci bus and the computer software processing module and local signal relevant treatment, between computing machine and the 32-bit number data acquisition card for to be electrically connected mutually.
The radiofrequency signal sampling module of described global position system real-time software receiving machine by gang socket with the string and the translation interface module in each parts be connected, wherein:
One radiofrequency signal sampling module is made up of GP2015 chip and serial ports, the GP2015 chip is exported two bit-serial digital signals successively, one is sign bit, and one is the amplitude position, is connected with corresponding each input port of chip for driving in string and the translation interface module by gang socket respectively; The GP2015 chip is exported a sampled clock signal and is connected with the respective input of chip for driving in string and the translation interface module by gang socket; The transmission and the received signal of two Transistor-Transistor Logic levels of serial ports input and output, the output of serial ports sends signal and is connected with the respective input mouth of serial ports level conversion in string and the translation interface module by gang socket, and the output received signal of serial ports level conversion is connected with the respective input of serial ports;
A string and translation interface module mainly is made up of CPLD, direct supply conversion, switch, serial ports level conversion, boundary scan interface and minicomputer system scsi interface, string and translation interface module are accepted 12V direct current supply, power supply is through there being one tunnel input end that inputs to the direct supply conversion module behind the switch, the direct supply conversion is output as power supply 3.3V, and be divided into five tunnel outputs: first via power supply signal is delivered to the respective input of pilot lamp; The second road power supply signal is delivered to the respective input of CPLD; The Third Road power supply signal is delivered to the respective input of serial ports level conversion and boundary scan interface simultaneously; The four road power supply signal is delivered to the respective input of jumper switch, and after the jumper switch closure, then active antenna power supply and power supply 3.3V are communicated with, and the active antenna power supply signal is delivered to antenna simultaneously; The five road power supply signal is delivered to the respective input of radiofrequency signal sampling module by gang socket;
One CPLD is accepted the three-way output signal from the GP2015 chip: sign bit, amplitude position and sampling clock are respectively through inputing to the respective input of CPLD after gang socket and the chip for driving; CPLD reads the level of sign bit and amplitude position at the rising edge of sampling clock, after per 16 rising edges of sampling clock, sampled the respectively level of 16 sign bits and amplitude position of CPLD, and its output become 2 16 parallel data: parallel symbol position and parallel amplitude position, and export the respective input of minicomputer system scsi interface respectively to; CPLD also will become the respective input that 16 frequency division sampling clocks also export the minicomputer system scsi interface to behind sampling clock 16 frequency divisions; The input end of the output terminal of minicomputer system scsi interface and digital signal acquiring card interconnects; The I/O of the input and output of CPLD and boundary scan interface module interconnects;
The output received signal of one serial ports level conversion is connected with the respective input mouth of serial port module by gang socket, and the output transmission signal that receives from serial ports is connected with the respective input mouth of serial ports level switch module by gang socket; The serial ports level conversion is that the transmission level of RS232 level sends the respective input that signal is delivered to the serial ports jack module with the transmission conversion of signals of Transistor-Transistor Logic level, and the transmission level received signal of RS232 level is delivered to the respective input of serial ports level switch module, the received signal that is converted to Transistor-Transistor Logic level through the serial ports level switch module is delivered to the respective input of serial port module by gang socket.
The CPLD U2 chip of described global position system real-time software receiving machine interconnects with the corresponding port of boundary scan interface, direct supply conversion U1 chip, serial ports level conversion U4 chip and chip for driving U3 chip module respectively; Wherein:
One CPLD U2 pin of chip 48,83,45 with 47 respectively with the boundary scan interface module in the pin 4,3,2 of JP1 socket be connected with 1 corresponding port is parallel mutually, the pin 6 of JP1 socket interconnects with the corresponding port of direct supply conversion U1 pin of chip 6, serial ports level conversion U4 pin of chip 16 and chip for driving U3 pin of chip 20 respectively simultaneously;
The while interconnected with the corresponding port of direct supply conversion U1 pin of chip 6 and chip for driving U3 pin of chip 20 after described CPLD U2 pin of chip 5,26,38,51,57,88 and 98 walked abreast mutually and is connected;
Described CPLD U2 pin of chip 21,31,44,62,69,75,84 and 100 corresponding port be parallel mutually to be connected ground connection afterwards;
Described CPLD U2 pin of chip 97,96 is connected with chip for driving U3 pin of chip 18,16,14 corresponding ports are parallel mutually respectively with 22; Pin 95 interconnects with the corresponding port of the pin 2 of J2 socket;
Described CPLD U2 pin of chip 33,32,30,29,20,19,16 and 15 interconnects with the pin 54,53,52,51,48,47,45 of J2 socket and 44 corresponding port respectively; Pin 14 and 17 interconnects with the pin 10 of J2 socket and 12 corresponding port respectively;
Described CPLD U2 pin of chip 56,58,54,53,49,46,41,40 and 36 interconnects with the pin 67,54,52,51,29,28,26,25 of J2 socket and 23 corresponding port respectively;
Described CPLD U2 pin of chip 35,34,28,25,24 and 18 interconnects with the pin 22,21,17,16,15 of J2 socket and 13 corresponding port respectively;
Described CPLD U2 pin of chip 37,39,42,43,50,52 and 55 interconnects with the pin 57,58,60,61,63,64 of J2 socket and 66 corresponding port respectively.
The serial ports level conversion U4 chip of described global position system real-time software receiving machine interconnects with the corresponding port of the module of J1 socket and JP3 socket respectively; Wherein:
One serial ports level conversion U4 chip pin 1 interconnects by capacitor C 6 and pin 3 ports; Pin 4 interconnects by capacitor C 7 and pin 5 ports;
A road of described serial ports level conversion U4 pin of chip 16 interconnects with the corresponding port of the pin 2 of power supply 3.3V and JP3, JP6 socket respectively, another road has two-way to connect respectively by capacitor C 9: the pin 10,13,16 and 18 ports of the first via and JP3 socket interconnect, the second the tunnel interconnects with the pin 5 and U4 pin of chip 15 ports of J1 socket, and interconnects by capacitor C 8, C10 and U4 pin of chip 2 and 4 ports respectively;
Described serial ports level conversion U4 pin of chip 13 and 14 interconnects with the pin 3 of J1 socket and 2 corresponding port respectively;
Described serial ports level conversion U4 pin of chip 11 and 12 interconnects with the pin 11 of JP3 socket and 12 corresponding port respectively.
The corresponding port of 1 while of direct supply conversion U1 pin of chip of described global position system real-time software receiving machine with the negative pole of an end of capacitor C 2 and diode D1 interconnects; Pin 2 lead up to capacitor C 1 back ground connection, another road via switch S 1 and socket P1 after ground connection; Pin 3 interconnects with the corresponding port of an end of the other end of the negative terminal of stabilivolt D2, capacitor C 2 and inductance L 1 simultaneously respectively; Pin 4 ground connection; Pin 6 interconnects with the corresponding port of the other end of the power end of an end of capacitor C 4, light emitting diode DSI and inductance L 1 simultaneously respectively; Pin 7 is by capacitor C 3 and resistance R 1 back ground connection; Pin 8 ground connection.
The chip for driving U3 chip pin 1 of described global position system real-time software receiving machine and 19 is mutually parallel to be connected back ground connection, pin 20 through capacitor C 5 and pin 10 walk abreast mutually are connected after ground connection; Pin 2,4 and 6 interconnects with the pin 1,2 of JP2 socket and 3 corresponding port respectively; Pin 14,16 and 18 interconnects with the corresponding port of CPLD U2 pin of chip 97,96 and 22 respectively.
The beneficial effects of the utility model are: this device has been realized real time execution in windows XP system of Microsoft, can export positioning result in real time; The major function of software receiver realizes that all the test result of present stage shows that the performance index of software receiver have all reached project demand, such as the accuracy of catching, the cold start-up time, the correctness of tracking loop and stability, and have higher precision and sensitivity.
Description of drawings
Below in conjunction with drawings and Examples the utility model is further specified.
Accompanying drawing 1 adds the development plan block diagram of digital data acquisition card for the utility model computing machine;
Accompanying drawing 2 is the utility model system global structure block scheme;
Accompanying drawing 3 is the utility model signal sampling transport module structural representation;
Accompanying drawing 4 is the utility model interface board circuit theory diagrams;
Accompanying drawing 7 is the utility model CPLD circuit theory diagrams;
Label declaration in the accompanying drawing:
The 1-computer software processing module;
11-sampled signal and local signal relevant treatment;
12-signal capture, tracking, synchronous, navigation calculation;
2-32 position digital signal capture card;
3-signal sampling transport module;
31-radiofrequency signal sampling module; 32-string and translation interface module;
The 3101-GP2015 chip; The 3201-CPLD;
The 3102-serial ports; The conversion of 3202-direct supply;
The 3103-sign bit; The 3203-switch;
3104-amplitude position; The 3204-pilot lamp;
The 3105-sampling clock; 3205-serial ports level conversion;
3106-sends; The 3206-boundary scan interface;
3107-receives; 3207-serial ports socket;
The 4-antenna; 3208-minicomputer system scsi interface;
The 10-computing machine; 3209-gang socket;
33-string and conversion; 3210-power supply 3.3V;
3211-parallel symbol position;
The 3212-amplitude position that walks abreast;
3213-16 frequency division sampling clock;
The 3214-transmission level sends signal;
3215-transmission level received signal;
The 3216-chip for driving;
The 3217-jumper switch;
The power supply of 3218-active antenna;
Embodiment
See also shown in the accompanying drawing 1,2,3,4,5,6,7, the utility model adopts the program of independently developed Windows operating system based on Microsoft to carry out Signal Processing, by signal sampling transport module and high-speed digital signal capture card, by the digital signal acquiring card if sampling signal is sent into relevant interfaces such as calculator memory, use new digital signal processing algorithm, successfully realized the real time execution of software receiver.
The utility model is by CPLD, bus, interface, antenna, shift register, storer, socket, A/D and computing machine, be provided with 32-bit number data acquisition card 2 in the described computing machine 10,32-bit number data acquisition card 2 is inserted on the computer main frame panel peripheral element extension interface PCI slot, send the data to computing machine by the peripheral element extension interface pci bus, the wireless navigation signal that this computing machine receives from the global position system GPS satellite by antenna 4, behind radiofrequency signal sampling module 31,2 position digital signals are delivered to string and change 33 modules, through string and the output signal of changing 33 modules by calculation procedure software based on general processor, but not the special-purpose baseband processing chip of global position system GPS carries out the processing of baseband signal, each module combinations is holistic software receiver, it is characterized in that: this device comprises at least:
Form by radiofrequency signal sampling module 31 and string and translation interface module 32 in the one signal sampling transport module 3, the input end of the radiofrequency signal sampling module 31 in antenna 4 and the signal sampling transport module 3 is connected, radiofrequency signal sampling module 31 is with the wireless navigation signal sampling and the digital-to-analog conversion of antenna 4 inputs, the I/O of the input/output terminal of radiofrequency signal sampling module 31 and string and translation interface module 32 interconnects, and the output terminal output digital signal transfers of string and translation interface module 32 is to the input end of 32-bit number data acquisition card 2;
One computer software processing module 1 by sampled signal and local signal relevant treatment 11 and signal capture, tracking, synchronously, navigation calculation 12 modules form, the input/output terminal of sampled signal and local signal relevant treatment 11 and signal capture, tracking, I/O synchronous, navigation calculation 12 modules interconnect;
One 32-bit number data acquisition card 2 interconnects by the sampled signal in peripheral element extension interface PCI (Peripheral Component Interconnect) bus and the computer software processing module 1 and the input end of local signal relevant treatment 11, after computing machine 10 obtains the data of 32-bit number data acquisition card 2, by software processes, finish the work of receiver.
See also shown in the accompanying drawing 3, the radiofrequency signal sampling module 31 of described global position system real-time software receiving machine by gang socket 3209 with the string and translation interface module 32 in each parts be connected, wherein:
One radiofrequency signal sampling module 31 is made up of GP2015 chip 3101 and serial ports 3102, GP2015 chip 3101 is exported two bit-serial digital signals successively, one is sign bit 3103, one is amplitude position 3104, is connected with corresponding each input port of chip for driving 3216 in string and the translation interface module 32 by gang socket 3209 respectively; GP2015 chip 3101 outputs one sampling clock 3105 signals are connected with the respective input of chip for driving 3216 in string and the translation interface module 32 by gang socket 3209; The transmission 3106 of two Transistor-Transistor Logic levels of serial ports 3102 input and output and reception 3107 signals, the output of serial ports 3102 sends 3106 signals and is connected with the respective input mouth of serial ports level conversion 3205 in string and the translation interface module 32 by gang socket 3209, and the output of serial ports level conversion 3205 receives 3107 signals and is connected with the respective input of serial ports 3102;
A string and translation interface module 32 mainly is made up of CPLD 3201, direct supply conversion 3202, switch 3203, serial ports level conversion 3205, boundary scan interface 3206 and minicomputer system scsi interface 3208, string and translation interface module 32 are accepted 12V direct current supply, power supply is through there being one tunnel input end that inputs to direct supply conversion 3202 modules behind the switch 3203, direct supply conversion 3202 is output as power supply 3.3V 3210, and be divided into five tunnel outputs: first via power supply signal is delivered to the respective input of pilot lamp 3204; The second road power supply signal is delivered to the respective input of CPLD 3201; The Third Road power supply signal is delivered to the respective input of serial ports level conversion 3205 and boundary scan interface 3206 simultaneously; The four road power supply signal is delivered to the respective input of jumper switch 3217, and after the jumper switch closure, then active antenna power supply 3218 and power supply 3.3V 3210 are communicated with, and active antenna 3218 signals of powering are delivered to antenna simultaneously; The five road power supply signal is delivered to the respective input of radiofrequency signal sampling module 31 by gang socket 3209;
The three-way output signal that one CPLD 3201 is accepted from GP2015 chip 3101: sign bit 3103, amplitude position 3104 and sampling clock 3105 are respectively through inputing to the respective input of CPLD 3201 after gang socket 3209 and the chip for driving 3216; CPLD 3201 reads the level of sign bit 3103 and amplitude position 3104 at the rising edge of sampling clock 3105, after per 16 rising edges of sampling clock 3105, sampled the respectively level of 16 sign bits 3103 and amplitude position 3104 of CPLD 3201, and its output become 2 16 parallel data: parallel symbol position 3211 and parallel amplitude position 3212, and export the respective input of minicomputer system scsi interface 3208 respectively to; CPLD 3201 also will become the respective input that 16 frequency division sampling clocks 3213 also export minicomputer system scsi interface 3208 to behind sampling clock 3,105 16 frequency divisions; The input end of the output terminal of minicomputer system scsi interface 3208 and digital signal acquiring card 2 interconnects; The I/O of the input and output of CPLD 3201 and boundary scan interface 3206 modules interconnects;
The output of one serial ports level conversion 3205 receives 3107 signals and is connected by the respective input mouth of gang socket 3209 with serial ports 3102 modules, and receives output from serial ports 3102 and send 3106 signals and be connected by the respective input mouth of gang socket 3209 with serial ports level conversion 3205 modules; Serial ports level conversion 3205 is that the transmission level of RS232 level sends the respective input that signal 3214 is delivered to serial ports socket 3207 modules with transmission 3106 conversion of signals of Transistor-Transistor Logic level, and the transmission level received signal 3215 of RS232 level is delivered to the respective input of serial ports level conversion 3205 modules, be reception 3107 signals of Transistor-Transistor Logic level are delivered to serial ports 3102 modules by gang socket 3209 respective input through serial ports level conversion 3205 module converts.
See also shown in the accompanying drawing 4, the CPLD 3201 U2 chips of described global position system real-time software receiving machine interconnect with the corresponding port of boundary scan interface 3206, direct supply conversion 3202 U1 chips, serial ports level conversion 3205 U4 chips and chip for driving (3216) U3 chip module respectively; Wherein:
One CPLD, 3201 U2 pin of chip 48,83,45 with 47 respectively with boundary scan interface 3206 modules in the pin 4,3,2 of JP1 socket be connected with 1 corresponding port is parallel mutually, the pin 6 of JP1 socket interconnects with the corresponding port of direct supply conversion 3202 U1 pin of chip 6, serial ports level conversion 3205 U4 pin of chip 16 and chip for driving 3216 U3 pin of chip 20 respectively simultaneously;
The while interconnected with the corresponding port of direct supply conversion 3202 U1 pin of chip 6 and chip for driving 3216 U3 pin of chip 20 after described CPLD 3201 U2 pin of chip 5,26,38,51,57,88 and 98 walked abreast mutually and are connected;
Described CPLD 3201 U2 pin of chip 21,31,44,62,69,75,84 and 100 corresponding port be parallel mutually to be connected ground connection afterwards;
Described CPLD 3201 U2 pin of chip 97,96 are connected with chip for driving 3216 U3 pin of chip 18,16,14 corresponding ports are parallel mutually respectively with 22; Pin 95 interconnects with the corresponding port of the pin 2 of J2 socket;
Described CPLD 3201 U2 pin of chip 33,32,30,29,20,19,16 and 15 interconnect with the pin 54,53,52,51,48,47,45 of J2 socket and 44 corresponding port respectively; Pin 14 and 17 interconnects with the pin 10 of J2 socket and 12 corresponding port respectively;
Described CPLD 3201 U2 pin of chip 56,58,54,53,49,46,41,40 and 36 interconnect with the pin 67,54,52,51,29,28,26,25 of J2 socket and 23 corresponding port respectively;
Described CPLD 3201 U2 pin of chip 35,34,28,25,24 and 18 interconnect with the pin 22,21,17,16,15 of J2 socket and 13 corresponding port respectively;
Described CPLD 3201 U2 pin of chip 37,39,42,43,50,52 and 55 interconnect with the pin 57,58,60,61,63,64 of J2 socket and 66 corresponding port respectively.
See also shown in the accompanying drawing 5, the serial ports level conversion 3205 U4 chips of described global position system real-time software receiving machine interconnect with the corresponding port of the module of J1 socket and JP3 socket respectively; Wherein:
One serial ports level conversion, 3205 U4 chip pins 1 interconnect by capacitor C 6 and pin 3 ports; Pin 4 interconnects by capacitor C 7 and pin 5 ports;
A road of described serial ports level conversion 3205 U4 pin of chip 16 interconnect with the corresponding port of the pin 2 of power supply 3.3V and JP3, JP6 socket respectively, another road has two-way to connect respectively by capacitor C 9: the pin 10,13,16 and 18 ports of the first via and JP3 socket interconnect, the second the tunnel interconnects with the pin 5 and U4 pin of chip 15 ports of J1 socket, and interconnects by capacitor C 8, C10 and U4 pin of chip 2 and 4 ports respectively;
Described serial ports level conversion 3205 U4 pin of chip 13 and 14 interconnect with the pin 3 of J1 socket and 2 corresponding port respectively;
Described serial ports level conversion 3205 U4 pin of chip 11 and 12 interconnect with the pin 11 of JP3 socket and 12 corresponding port respectively.
See also shown in the accompanying drawing 6, the corresponding port of direct supply conversion 1 while of 3202 U1 pin of chip of described global position system real-time software receiving machine with the negative pole of an end of capacitor C 2 and diode D1 interconnects; Pin 2 lead up to capacitor C 1 back ground connection, another road via switch S 1 and socket P1 after ground connection; Pin 3 interconnects with the corresponding port of an end of the other end of the negative terminal of stabilivolt D2, capacitor C 2 and inductance L 1 simultaneously respectively; Pin 4 ground connection; Pin 6 interconnects with the corresponding port of the other end of the power end of an end of capacitor C 4, light emitting diode DSI and inductance L 1 simultaneously respectively; Pin 7 is by capacitor C 3 and resistance R 1 back ground connection; Pin 8 ground connection.
See also shown in the accompanying drawing 3,4, the chip for driving 3216 U3 chip pins 1 of described global position system real-time software receiving machine and 19 are mutually parallel to be connected back ground connection, pin 20 through capacitor C 5 and pin 10 walk abreast mutually are connected after ground connection; Pin 2,4 and 6 interconnects with the pin 1,2 of JP2 socket and 3 corresponding port respectively; Pin 14,16 and 18 interconnects with the corresponding port of CPLD 3201 U2 pin of chip 97,96 and 22 respectively.
Principle of work of the present utility model and system's characteristics are as follows:
See also shown in the accompanying drawing 1,2, characteristics of the present utility model are base band relevant treatment part to be put in the computing machine fully realize, promptly the sampled signal of RF end are directly sent into computing machine, finish whole computings by microprocessor then.
Hardware components in this programme needs a shift register module and a high-speed digital signal capture card.The effect of shift register module is that 1 or 2 s' radio-frequency front-end if sampling conversion of signals is become 32, sends into the digital signal acquiring card then.The digital signal acquiring card is sent into calculator memory to the if sampling signal, finishes whole computings by the central processing unit of computing machine then.The utility model is exactly to adopt this method to realize the GPS sign indicating number receiver of real-time GPS single-frequency (L1 frequency range).
What antenna that uses in this system and radio frequency were bought is ripe commercial module.To be converted to 32/16 parallel signal by complex programmable logic device (CPLD) (Complex programmable logic device) by 1 of radio-frequency module output or 2 position digital signals, be sent to the digital signal acquiring card together with clock signal.The digital signal card adopts National Instruments (American National instrument) digital signal acquiring card (NI DIOPCI6534).
GPS software receiver hardware consists of the following components:
1. radiofrequency signal sampling module (the SuperStarII receiver includes the GP2015 chip);
2. go here and there and translation interface module (mainly forming) by CPLD (CPLD) circuit
3. digital signal acquiring card (NI PCI-6534)
6. PC;
7. external power supply (3～25V direct current).
See also shown in the accompanying drawing 1,2,3,4, whole GPS receiver system can be divided into antenna, signal sampling transport module, digital signal acquiring card, computer software processing module.
Signal sampling transport module 3 mainly contains radiofrequency signal sampling module 31 and string and translation interface module 32 and is formed by connecting.Detailed structure is seen Fig. 3.Radiofrequency signal sampling module 31 is GPS receiver cards of a commercialization, and model is the superstar II of Novatel company.A GP2015 chip 3101 is arranged in the radiofrequency signal sampling module 31, and it exports two bit-serial digital signals, and one is that 3103, one of sign bits are amplitude position 3104.GP2015 chip 3101 is also exported a sampling clock 3105 simultaneously, and clock frequency is 5.714MHz.The transmission 3106 of two Transistor-Transistor Logic levels of serial ports 3102 input and output and reception 3107 signals.Because radiofrequency signal sampling module 31 and string and translation interface module 32 are two independently circuit boards.Above-mentioned five road signals 3103,3104,3105,3106,3107 by gang socket 3209 with the string and translation interface module 32 in each parts link to each other.String and translation interface module 32 are accepted 1 2V direct current supply, and power supply inputs to direct supply conversion 3202 through another road, switch 3203 back, and 3～25V that direct supply conversion 3202 will be imported is transformed to 3.3V.Direct supply conversion 3202 is output as 3.3V 3210 power supplys, and the first via gives pilot lamp 3204 power supplies, and after switch 3203 closures, pilot lamp 3204 is lighted; The second the tunnel gives CPLD 3201 power supplies, Third Road gives the serial ports level conversion 3205 power supplies, and the four the tunnel inputs to jumper switch 3217, after the jumper switch closure, then active antenna power supply 3218 and power supply 3.3V 3210 are communicated with, and active antenna power supply 3218 provides power supply to antenna.The gang socket 3209 of leading up at last gives the radiofrequency signal sampling module 31 power supplies.Three tunnel outputs of the GP2015 chip 3101 of radiofrequency signal sampling module 31: input to CPLD 3201 after sign bit 3103 amplitude positions 3104 sampling clocks, 3105 process gang sockets 3209 and the chip for driving 3216.CPLD 3201 reads the level of sign bit 3103 amplitude positions 3104 at the rising edge of sampling clock 3105, after per 16 rising edges of sampling clock 3105, sampled the respectively level of 16 sign bits 3103 and amplitude position 3104 of CPLD 3201, and it is become 2 16 parallel data: parallel symbol position 3211 and parallel amplitude position 3212 export scsi interface 3208 to.CPLD 3201 still exports scsi interface 3208 to becoming 16 frequency division sampling clocks 3213 behind sampling clock 3,105 16 frequency divisions.Scsi interface 3208 is connected with digital signal acquiring card 2.
The input and output of CPLD 3201 are connected with boundary scan interface 3206, are used for the programming to CPLD 3201 internal logic circuits.
The transmission 3106 of two Transistor-Transistor Logic levels of serial ports 3102 input and output is connected with serial ports level conversion 3205 by gang socket 3209 with reception 3107 signals.Serial ports level conversion 3205 is converted to the transmission level transmission signal 3214 of RS232 level with the transmission 3106 of Transistor-Transistor Logic level, and the transmission level received signal 3215 of RS232 level is converted to reception 3107 signals of Transistor-Transistor Logic level.Transmission level sends signal 3214, transmission level received signal 3215 links to each other with serial ports socket 3207.
Digital signal acquiring card 2 is the NI PCI-6534 of NI (American National instrument) company.
The output that interface module of the present utility model has also been finished the SuperStarII receiver is converted to RS232 serial ports form, directly uses for the software that moves on the PC.
Therefore, GPS software receiver and SuperStarII receiver shared radio frequency front end in this interface module.Both can offer capture card, in PC, finish the acquisition and tracking algorithm by independently developed software then by the digital signal that the SCSI joint is exported radio-frequency front-end; Simultaneously the SuperStarII receiver also can operate as normal, and output is resolved the result and be transferred to the PC serial ports after level translation, is handled by the special software that moves on the PC.Adopt this scheme, the effect of acquisition and tracking is different when adopting same radio-frequency front-end with software receiver and SuperStarII receiver.
Claims (6)
1, a kind of global position system real-time software receiving machine, this device has CPLD, bus, interface, antenna, shift register, storer, socket, A/D and computing machine, be provided with 32-bit number data acquisition card (2) in the described computing machine (10), 32-bit number data acquisition card (2) is inserted in the expansion of computer main frame panel peripheral element and connects on the PCI slot, send the data to computing machine by the peripheral element extension interface pci bus, this computing machine is by the wireless navigation signal of antenna (4) reception from the global position system GPS satellite, behind radiofrequency signal sampling module (31), 2 position digital signals are delivered to string and conversion (33) module, through the output signal of string and conversion (33) module by based on the computing machine of general processor, but not the special-purpose baseband processing chip of global position system GPS carries out the processing of baseband signal, each module combinations is holistic software receiver, it is characterized in that: this device comprises at least:
In the one signal sampling transport module (3) by radiofrequency signal sampling module (31) and the string and translation interface module (32) form, the input end of the radiofrequency signal sampling module (31) in antenna (4) and the signal sampling transport module (3) is connected, radiofrequency signal sampling module (31) is with the wireless navigation signal sampling and the digital-to-analog conversion of antenna (4) input, the I/O of the input/output terminal of radiofrequency signal sampling module (31) and string and translation interface module (32) interconnects, and the output terminal output digital signal transfers of string and translation interface module (32) is to the input end of 32-bit number data acquisition card (2);
One computer software processing module (1) by sampled signal and local signal relevant treatment (11) and signal capture, tracking, synchronously, navigation calculation (12) module forms, the input/output terminal of sampled signal and local signal relevant treatment (11) and signal capture, tracking, I/O synchronous, navigation calculation (12) module interconnect;
One 32-bit number data acquisition card (2) interconnects by the input end of sampled signal in peripheral element extension interface pci bus and the computer software processing module (1) and local signal relevant treatment (11), between computing machine (10) and the 32-bit number data acquisition card (2) for to be electrically connected mutually.
2, global position system real-time software receiving machine according to claim 1 is characterized in that: described radiofrequency signal sampling module (31) by gang socket (3209) with the string and translation interface module (32) in each parts be connected, wherein:
One radiofrequency signal sampling module (31) is made up of GP2015 chip (3101) and serial ports (3102), GP2015 chip (3101) is exported two bit-serial digital signals successively, one is sign bit (3103), one is amplitude position (3104), is connected with corresponding each input port of chip for driving (3216) in string and the translation interface module (32) by gang socket (3209) respectively; GP2015 chip (3101) output one sampling clock (3105) signal is connected with the respective input of chip for driving (3216) in string and the translation interface module (32) by gang socket (3209); The transmission (3106) of two Transistor-Transistor Logic levels of serial ports (3102) input and output and reception (3107) signal, the output of serial ports (3102) sends (3106) signal and is connected with the respective input mouth of serial ports level conversion (3205) in string and the translation interface module (32) by gang socket (3209), and the output of serial ports level conversion (3205) receives (3107) signal and is connected with the respective input of serial ports (3102);
A string and translation interface module (32) is mainly by CPLD (3201), direct supply conversion (3202), switch (3203), serial ports level conversion (3205), boundary scan interface (3206) and minicomputer system scsi interface (3208) are formed, string and translation interface module (32) are accepted 12V direct current supply, power supply has one tunnel input end that inputs to direct supply conversion (3202) module after through switch (3203), direct supply conversion (3202) is output as power supply 3.3V (3210), and be divided into five tunnel outputs: first via power supply signal is delivered to the respective input of pilot lamp (3204); The second road power supply signal is delivered to the respective input of CPLD (3201); The Third Road power supply signal is delivered to the respective input of serial ports level conversion (3205) and boundary scan interface (3206) simultaneously; The four road power supply signal is delivered to the respective input of jumper switch (3217), and after the jumper switch closure, then active antenna power supply (3218) and power supply 3.3V (3210) are communicated with, and active antenna power supply (3218) signal is delivered to antenna simultaneously; The five road power supply signal is delivered to the respective input of radiofrequency signal sampling module (31) by gang socket (3209);
One CPLD (3201) is accepted the three-way output signal from GP2015 chip (3101): sign bit (3103), amplitude position (3104) and sampling clock (3105) pass through the respective input that inputs to CPLD (3201) after gang socket (3209) and the chip for driving (3216) respectively; CPLD (3201) reads the level of sign bit (3103) and amplitude position (3104) at the rising edge of sampling clock (3105), after per 16 rising edges of sampling clock (3105), sampled the respectively level of 16 sign bits (3103) and amplitude position (3104) of CPLD (3201), and its output become 2 16 parallel data: parallel symbol position (3211) and parallel amplitude position (3212), and export the respective input of minicomputer system scsi interface (3208) respectively to; CPLD (3201) also will become the respective input that 16 frequency division sampling clocks (3213) also export minicomputer system scsi interface (3208) to behind sampling clock (3105) 16 frequency divisions; The input end of the output terminal of minicomputer system scsi interface (3208) and digital signal acquiring card (2) interconnects; The I/O of the input and output of CPLD (3201) and boundary scan interface (3206) module interconnects;
The output of one serial ports level conversion (3205) receives (3107) signal and is connected by the respective input mouth of gang socket (3209) with serial ports (3102) module, and output transmission (3106) signal that receives from serial ports (3102) is connected by the respective input mouth of gang socket (3209) with serial ports level conversion (3205) module; Serial ports level conversion (3205) is that the transmission level of RS232 level sends the respective input that signal (3214) is delivered to serial ports socket (3207) module with transmission (3106) conversion of signals of Transistor-Transistor Logic level, and the transmission level received signal (3215) of RS232 level is delivered to the respective input of serial ports level conversion (3205) module, be reception (3107) signal of Transistor-Transistor Logic level is delivered to serial ports (3102) module by gang socket (3209) respective input through serial ports level conversion (3205) module converts.
3, global position system real-time software receiving machine according to claim 2 is characterized in that: described CPLD (3201) U2 chip interconnects with the corresponding port of boundary scan interface (3206), direct supply conversion (3202) U1 chip, serial ports level conversion (3205) U4 chip and chip for driving (3216) U3 chip module respectively; Wherein:
One CPLD (3201) U2 pin of chip 48,83,45 with 47 respectively with boundary scan interface (3206) module in the pin 4,3,2 of JP1 socket be connected with 1 corresponding port is parallel mutually, the pin 6 of JP1 socket interconnects with the corresponding port of direct supply conversion (3202) U1 pin of chip 6, serial ports level conversion (3205) U4 pin of chip 16 and chip for driving (3216) U3 pin of chip 20 respectively simultaneously;
The while interconnected with the corresponding port of direct supply conversion (3202) U1 pin of chip 6 and chip for driving (3216) U3 pin of chip 20 after described CPLD (3201) U2 pin of chip 5,26,38,51,57,88 and 98 walked abreast mutually and is connected;
Described CPLD (3201) U2 pin of chip 21,31,44,62,69,75,84 and 100 corresponding port be parallel mutually to be connected ground connection afterwards;
Described CPLD (3201) U2 pin of chip 97,96 is connected with chip for driving (3216) U3 pin of chip 18,16,14 corresponding ports are parallel mutually respectively with 22; Pin 95 interconnects with the corresponding port of the pin 2 of J2 socket;
Described CPLD (3201) U2 pin of chip 33,32,30,29,20,19,16 and 15 interconnects with the pin 54,53,52,51,48,47,45 of J2 socket and 44 corresponding port respectively; Pin 14 and 17 interconnects with the pin 10 of J2 socket and 12 corresponding port respectively;
Described CPLD (3201) U2 pin of chip 56,58,54,53,49,46,41,40 and 36 interconnects with the pin 67,54,52,51,29,28,26,25 of J2 socket and 23 corresponding port respectively;
Described CPLD (3201) U2 pin of chip 35,34,28,25,24 and 18 interconnects with the pin 22,21,17,16,15 of J2 socket and 13 corresponding port respectively;
Described CPLD (3201) U2 pin of chip 37,39,42,43,50,52 and 55 interconnects with the pin 57,58,60,61,63,64 of J2 socket and 66 corresponding port respectively.
4, global position system real-time software receiving machine according to claim 2 is characterized in that: described serial ports level conversion (3205) U4 chip interconnects with the corresponding port of the module of J1 socket and JP3 socket respectively; Wherein:
One serial ports level conversion (3205) U4 chip pin 1 interconnects by capacitor C 6 and pin 3 ports; Pin 4 interconnects by capacitor C 7 and pin 5 ports;
A road of described serial ports level conversion (3205) U4 pin of chip 16 interconnects with the corresponding port of the pin 2 of power supply 3.3V and JP3, JP6 socket respectively, another road has two-way to connect respectively by capacitor C 9: the pin 10,13,16 and 18 ports of the first via and JP3 socket interconnect, the second the tunnel interconnects with the pin 5 and U4 pin of chip 15 ports of J1 socket, and interconnects by capacitor C 8, C10 and U4 pin of chip 2 and 4 ports respectively;
Described serial ports level conversion (3205) U4 pin of chip 13 and 14 interconnects with the pin 3 of J1 socket and 2 corresponding port respectively;
Described serial ports level conversion (3205) U4 pin of chip 11 and 12 interconnects with the pin 11 of JP3 socket and 12 corresponding port respectively.
5, global position system real-time software receiving machine according to claim 2 is characterized in that: described direct supply conversion (3202) U1 pin of chip 1 interconnects with the corresponding port of the negative pole of end of capacitor C 2 and diode D1 simultaneously; Pin 2 lead up to capacitor C 1 back ground connection, another road via switch S 1 and socket P1 after ground connection; Pin 3 interconnects with the corresponding port of an end of the other end of the negative terminal of stabilivolt D2, capacitor C 2 and inductance L 1 simultaneously respectively; Pin 4 ground connection; Pin 6 interconnects with the corresponding port of the other end of the power end of an end of capacitor C 4, light emitting diode DSI and inductance L 1 simultaneously respectively; Pin 7 is by capacitor C 3 and resistance R 1 back ground connection; Pin 8 ground connection.
6, global position system real-time software receiving machine according to claim 2 is characterized in that: described chip for driving (3216) U3 chip pin 1 and 19 is mutually parallel to be connected back ground connection, pin 20 through capacitor C 5 and pin 10 walk abreast mutually are connected after ground connection; Pin 2,4 and 6 interconnects with the pin 1,2 of JP2 socket and 3 corresponding port respectively; Pin 14,16 and 18 interconnects with the corresponding port of CPLD (3201) U2 pin of chip 97,96 and 22 respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2007200762814U CN201138374Y (en) | 2007-11-16 | 2007-11-16 | Real-time software receiving machine of global position system |
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| CNU2007200762814U CN201138374Y (en) | 2007-11-16 | 2007-11-16 | Real-time software receiving machine of global position system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101839970B (en) * | 2009-03-18 | 2012-02-29 | 杭州中科微电子有限公司 | Method for quickly acquiring GPS signal and system thereof |
| CN104079309A (en) * | 2014-06-11 | 2014-10-01 | 南京第五十五所技术开发有限公司 | Communication device and communication method of K wave band vehicle-mounted receiver |
| CN105022072A (en) * | 2015-05-19 | 2015-11-04 | 武汉理工大学 | Mixed de-noising method of a Beidou satellite positioning coordinate continuous time series |
-
2007
- 2007-11-16 CN CNU2007200762814U patent/CN201138374Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101839970B (en) * | 2009-03-18 | 2012-02-29 | 杭州中科微电子有限公司 | Method for quickly acquiring GPS signal and system thereof |
| CN104079309A (en) * | 2014-06-11 | 2014-10-01 | 南京第五十五所技术开发有限公司 | Communication device and communication method of K wave band vehicle-mounted receiver |
| CN105022072A (en) * | 2015-05-19 | 2015-11-04 | 武汉理工大学 | Mixed de-noising method of a Beidou satellite positioning coordinate continuous time series |
| CN105022072B (en) * | 2015-05-19 | 2017-12-29 | 武汉理工大学 | The mixed denoising method of big-dipper satellite elements of a fix continuous time series |
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