CN201114403Y - High-speed image sensing system based on industrial CCD - Google Patents
High-speed image sensing system based on industrial CCD Download PDFInfo
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- CN201114403Y CN201114403Y CNU2007200766590U CN200720076659U CN201114403Y CN 201114403 Y CN201114403 Y CN 201114403Y CN U2007200766590 U CNU2007200766590 U CN U2007200766590U CN 200720076659 U CN200720076659 U CN 200720076659U CN 201114403 Y CN201114403 Y CN 201114403Y
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Abstract
A high-speed image sensing system based on industrial CCD is characterized in that the structure is as follows: an adjustable diaphragm is closely arranged in front of a photosensitive surface of a low-speed CCD with an adjustable driving circuit and a peripheral circuit, and the output end of the CCD is sequentially connected with a de-noising circuit and an analog-to-digital conversion circuit. The exposure area of the CCD photosensitive area is controlled by the diaphragm, the CCD chip is driven to work by the special adjustable driving circuit, only the charge of the CCD pixel unit of the exposure part is transferred, the charge transfer time can be obviously reduced, and the CCD frame rate is improved. The utility model has the characteristics of system simple structure, reliability are high, with low costs, measuring speed is fast, the precision is high, and sinusoidal phase modulation surface morphology interferometry that is used for that can be fine is applicable to the real-time detection in fields such as manufacturing, image recognition, automatic precision measurement, robot vision, automatic tracking.
Description
Technical field
The utility model relates to high speed imaging sensor, and particularly a kind of high speed image sensor-based system based on industrial CCD relates to the high speed image sensor-based system based on industrial CCD that is used for the sinusoidal phase modulation interferometry.
Background technology
Need devices such as high-speed charge coupled device (being designated hereinafter simply as CCD) imageing sensor and CMOS (Complementary Metal Oxide Semiconductor) (abbreviating CMOS as) imageing sensor usually from fields such as motion tracking, automatic accurate measurements, in order to the variation of fast recording image information.The high-speed CCD and the cmos image sensor of at present existing comparative maturity, the nonadjustable surely problem but commercial high-speed CCD transducer ubiquity cost costliness, complex structure, sacrifice sensor accuracy and frame are tachy steroled.
(formerly technology 1 at international advanced sinusoidal phase modulation (abbreviating SPM as) face shape interfere measurement technique, OsamiSasaki, Hirokazu Okazaki, Sinusoidal phase modulating interferometry for surface profilemeasurement, Applied Optics, 1986,25 (18): 3137-3140), need be with the tens of width of cloth interference patterns of collection of hundreds of Hz even higher frame frequency continuous precise, be used for signal processing such as Fourier conversion, thus the acquisition measured surface pattern of nano-precision; Also need the image acquisition process of ccd sensor and the modulation signal strict synchronism that the SPM interfere measurement technique is adopted simultaneously, and satisfy specific phase relation.General commercial high-speed CCD frame frequency is non-adjustable, the IMAQ phase place is wayward, the photodetection noise is generally bigger, is difficult to satisfy the demand of technology 1 formerly.
Technology 2 (Liu Changlin, Zhou Xudong, image sensor technologies and application formerly, publishing house of University of Electronic Science and Technology 2004:74-78) has reported a kind of high-speed CCD imageing sensor, and its pixel cell is 80 * 80, frame frequency was up to for 2000 frame/seconds, single Pixel Dimensions 40 μ m * 40 μ m.This technology adopts the image partition method and the parallel way of output of two channels, uses the signal synthetic technology two sub-images are spliced, and forms a width of cloth complete image.Because the system that this technology adopted needs chiller, causes complex structure, the cost costliness; In addition,, use two operational amplifiers respectively the different pixels signal to be amplified, reduced the consistency of CCD picture element signal, cause certain noise, can not finely satisfy the requirement of high-acruracy survey because this technology adopts binary channels output; And the pixel count of this technology and frame tachy sterol surely, and its range of application is restricted.
Kodak in 2003 releases new product KODAK KAI-0340M imageing sensor, image output reach 210 frame/seconds video effect (formerly technology 3,
Http:// www.kodak.com/CN/zh-cn/dpq/site/SENSORS/ name/KAI-0340_product).This imageing sensor has the resolution of 640 (H) * 480 (V), optional single or dual enhancement mode frame rate output.Use quick horizontal line to store up technology during output, can further frame speed be brought up to per second 4000 frames, resolution is the video of 244 (H) * 60 (V).But this technology has only several groups of fixing frame speed and pixel count combination.
Summary of the invention
The purpose of this utility model is the difficult problem for deficiency that overcomes above-mentioned technology formerly and existence, and a kind of high speed image sensor-based system based on industrial CCD is provided.The frame speed of this transducer is adjustable continuously; Image acquisition process can with the outer synchronous signal strict synchronism; Based on the commercial CCD chip of common low speed, cheap; And certainty of measurement is high and measuring speed is fast, can be good at being used for the interferometry of SPM surface topography, from fields such as motion trackings good application prospects is being arranged also.
The utility model principle is according to being:
Based on general commercial low speed CCD device, Fig. 1 is the structural representation of the commercial area array CCD of low speed.It mainly is made up of photosensitive area, memory block, horizontal readout register and output circuit four parts.Photosensitive area and memory block constitute by M * N CCD pixel cell, and horizontal readout register generally also has N CCD unit.Φ
A, Φ
B, Φ
HRepresent that respectively frame transfer, row shift and read the shift pulse group.When CCD worked, the photosensitive area at first entered the light integral process, and each CCD unit carries out opto-electronic conversion, and signal charge is stored in the potential well of corresponding units, finishes the light integral process.Then, by the frame transfer pulse, make the signal charge of photosensitive area move to the memory block.After frame transfer finished, the photosensitive area entered second light integration.When the photosensitive area is in second light integration, be expert to shift and carry out M row under the pulsed drive and shift in the memory block, each row transfer each unit, pulsed drive memory block with signal charge to horizontal shifting register translation delegation.After carrying out once row transfer, under the effect of reading shift pulse, fast the signal of the N in the horizontal shifting register is exported successively through output circuit.After this delegation all exported, carrying out next time again, row shifted.Like this, between second light integration period, the charge signal of memory block and horizontal readout register is exported first field signal under the effect of driving pulse separately line by line.The above-mentioned course of work as shown in Figure 2.Repeat above process, realize continuous operation.
By above narration as can be known, the frame period of CCD mainly comprises the time of integration, charge transfer time and output time.Can foreshorten to the microsecond magnitude time of integration of CCD at present, charge transfer time becomes the main factor in restriction frame period.And charge transfer time is directly proportional with the pixel count of every frame.Satisfying under the prerequisite of measuring needs,, then can shorten the frame period, improving frame speed if reduce the pixel count of the every frame of CCD.
The utility model is under the certain situation of the maximum operating frequency of low speed CCD and output bandwidth speed, and the work of special-purpose drive circuit driven CCD is adopted in the exposure area of adopting adjustable diaphragm control CCD, by controlling every frame valid pixel number, improves the frame frequency of CCD.In drive circuit, use phase-locked frequency multiplier circuit simultaneously, CCD is synchronoused working with outer synchronous signal (as the modulation signal in the SPM interfere measurement technique).
The utility model adopts the exposure area of adjustable diaphragm control CCD photosensitive area, as shown in Figure 3.Front in CCD device photosensitive area is close to and is placed a diaphragm that is not less than M * N CCD pixel size, and its clear aperature is variable, is m * n pixel size.Therefore only make m * n pixel of CCD device photosensitive area can carry out the light integration, other pixel is covered (dash area among the figure) by diaphragm, and photogenerated charge is zero.Therefore, shift and displacement when reading going, do not need to read the photogenerated charge of whole M * N pixel cell, only need to migrate out the photogenerated charge of m * n CCD pixel (exposure region and with diaphragm transition region).By special-purpose drive circuit driven CCD chip operation, only consider m * n exposure CCD pixel cell, can reduce charge transfer time, improve CCD frame speed.
Fig. 4 is the electric charge readout of the special-purpose drive circuit of the utility model.The transfer process of electric charge from the photosensitive area to the memory block is identical with commercial CCD.The transition phase of being expert at, because the photosensitive area capable CCD pixel of below a is not carried out the light integration, therefore preceding a capable transfer process, horizontal readout register does not carry out read operation, has shortened their capable transfer time greatly.For the capable exposure area of m, after each row shifts, only carry out the read operation of n sub-level readout register, also shortened capable transfer time to a certain extent.Only read the charge signal of m * n exposure area at last.Therefore,, realized reading of CCD device local pixel unit, reduced charge transfer time, improved frame speed by special-purpose drive circuit and adjustable diaphragm.
Technical solution of the present utility model is as follows:
A kind of high speed image sensor-based system based on industrial CCD, characteristics are that its structure is: be close to before the photosurface of the low speed CCD with adjustable drive circuit and peripheral circuit and place an adjustable diaphragm, the output of described CCD connects denoising circuit and analog to digital conversion circuit in turn.
Described adjustable drive circuit is made of pulse-generating circuit, frequency dividing circuit, counting circuit, synchronous circuit, line-scan circuit, field-scanning circuit; The input of the phase locking frequency multiplying circuit in the described pulse-generating circuit is connected with external synchronization signal S, and its output is connected with the first input end of frequency dividing circuit, the input of counting circuit respectively; The output of this frequency dividing circuit is connected with the input of line-scan circuit, the first input end of the level shifting circuit in the output of this line-scan circuit and the described peripheral circuit is connected, and first output of this level shifting circuit shifts the pulse signal control end with the row of described CCD and is connected; The output of described counting circuit is connected with the input of described synchronous circuit, first output of this synchronous circuit, second output are connected with second input of described frequency dividing circuit, the input of described field-scanning circuit respectively, second input of the described level shifting circuit in the output of this field-scanning circuit and the peripheral circuit is connected, and second output of described level shifting circuit shifts a pulse signal control end with the field of CCD and is connected.
Described diaphragm is the field stop that described CCD sensitive volume is limited in the front of being close to the photosensitive area that is placed on described CCD, and the size of this diaphragm is not less than M * N pixel, and its clear aperature is adjustable, is m * n pixel size.
Described external synchronization signal S is meant the sine voltage signal certain with the phase difference of CCD measuring object.
Described low speed CCD is a frame transfer type area array CCD, or interline transfer type area array CCD, or frame interline transfer type area array CCD.
The synchronization pulse that described phase locking frequency multiplying circuit is its output and the frequency of external sync input signal satisfy the circuit of multiple relation and constant phase difference.
Described frequency dividing circuit is the circuit that requires to produce different divider ratios pulses according to the frame frequency of CCD, as counter.
Described counting circuit is the logical circuit of control CCD line scanning pulse and horizontal readout register read pulse number.
Described synchronous circuit is a logical circuit of coordinating sequential relationship between CCD light integration, row transfer pulse and the horizontal readout register read pulse three.It makes the three satisfy the sequential requirement of CCD chip operate as normal.
Described line-scan circuit is the pulse generating circuit of the horizontal readout register read pulse of generation signal.
Described field-scanning circuit is the logical circuit that produces CCD light integration and row transfer pulse signal.
Described peripheral circuit be meant the logical circuit of the CCD that can realize resetting and can realize going, the field scan pulse is converted to the required level signal of driven CCD work by Transistor-Transistor Logic level circuit.
Described diaphragm is meant the field stop of restriction CCD sensitive volume.The size of diaphragm is not less than M * N CCD pixel, is close to the front that is placed on the CCD photosensitive area, and its clear aperature is a m * n CCD pixel size.
Described CCD is meant the surface array charge-coupled device that can finish opto-electronic conversion, and it can be frame transfer type area array CCD, interline transfer type area array CCD, frame interline transfer type area array CCD.
Described external synchronization signal is meant the sine voltage signal certain with the phase difference of CCD measuring object.
The utility model has the advantages that:
1, compare with technology 3 formerly with technology 2 formerly, the utility model adopts adjustable drive circuit, has realized the continuous adjustable of CCD frame frequency and based on the high speed image sensing of low speed CCD;
2, the utility model does not have complicated control assembly, and adjustable drive circuit is simple, the stability of system and reliability height, and cost is low;
3, by adopting the phase locking frequency multiplying circuit, can make work and the outer synchronous signal strict synchronism of CCD.
Description of drawings
Fig. 1 is the structural representation of the commercial area array CCD of low speed.
Fig. 2 is the electric charge readout schematic diagram of the commercial CCD of low speed.
Fig. 3 is the high speed sensing arrangement schematic diagram based on the low speed area array CCD of the present utility model.
Fig. 4 is the electric charge readout schematic diagram of the utility model CCD.
Fig. 5 is the high speed image sensor-based system structural representation of the utility model based on industrial CCD.
Fig. 6 is adjustable drive circuit of CCD of the present utility model and peripheral circuit structural representation.
Embodiment
Below by embodiment and accompanying drawing thereof the utility model is further specified, but should not limit protection range of the present utility model with this.
Consult Fig. 5 and Fig. 6, Fig. 5 is the structural representation of the high speed image sensor-based system embodiment based on industrial CCD of the present utility model, and Fig. 6 position is the adjustable drive circuit and the peripheral circuit structural representation of ccd image sensor of the present utility model.Structure of the present utility model is: be close to before the photosurface of the low speed CCD 4 with adjustable drive circuit 1 and peripheral circuit 2 and place a diaphragm 3; The input of the phase locking frequency multiplying circuit 1001 in the adjustable drive circuit 1 is connected with external synchronization signal S, and its output is connected with the first input end 111 of frequency dividing circuit 11, the input of counting circuit 12 respectively; The output of this frequency dividing circuit 11 is connected with the input of line-scan circuit 14, the first input end 211 of the level shifting circuit 21 in the output of this line-scan circuit 14 and the described peripheral circuit 2 is connected, and first output 213 of this level shifting circuit 21 shifts the pulse signal control end with the row of CCD4 and is connected; The output of counting circuit 12 is connected with the input of synchronous circuit 13, first output 131, second output 132 of this synchronous circuit 13 are connected with second input 112 of frequency dividing circuit, the input of field-scanning circuit 15 respectively, second input 212 of the level shifting circuit 21 in the output of this field-scanning circuit 15 and the described peripheral circuit 2 is connected, and second output 214 of this level shifting circuit 21 shifts the pulse signal control end with the row of CCD4 and is connected.The output of described CCD4 connects denoising circuit 5 and analog to digital conversion circuit 6 in turn.
Described diaphragm 3 is meant the field stop of restriction CCD4 sensitive volume.The size of this diaphragm 3 is not less than M * N pixel, is close to the front that is placed on described CCD4 photosensitive area, and its clear aperature is adjustable, is m * n pixel size.
Described external synchronization signal S is meant the sine voltage signal certain with the phase difference of CCD4 measuring object.
Working condition of the present utility model is as follows:
The exposure area of diaphragm 3 control CCD4 photosensitive areas, the photosensitive area of CCD4 has only m * n pixel can carry out the light integration, and other pixel is covered by diaphragm 3.The light that is radiated at by diaphragm 3 on the photosensitive area of CCD4 is converted into charge signal, is stored in the potential well of each pixel cell.Synchronous circuit 13 is coordinated the light integration of described CCD4, the logical circuit that row shifts sequential relationship between pulse and the horizontal readout register read pulse three.Under the effect of frame transfer pulse, charge signal is transferred in the memory block of CCD4.After frame transfer finished, the photosensitive area of CCD4 entered second optical-integral-time.The charge signal of CCD4 memory block is exported under the drive signal effect of adjustable drive circuit 1 output line by line at this moment.
The utility model is under the situation that does not change the ccd data transmission rate, set the field scan pulse number by counting circuit, can from the CCD pel array, choose the pixel output of any amount, thereby improve the frame frequency of low speed CCD, and the precision that has kept low speed CCD realizes high-speed high-acruracy survey.
Phase locking frequency multiplying circuit 1001 adopts 74HC4046, and Digital Logical Circuits adopts Field Programmable Gate Array Flex10K30A to realize, comprising: frequency dividing circuit 11, counting circuit 12, synchronous circuit 13, line-scan circuit 14, field-scanning circuit 15 etc.Level shifting circuit 21 adopts DS0026,75361 chips.Denoising circuit 5 adopts ac-coupled circuits to remove in the raw video signal after the flip-flop, by clamped circuit (circuit such as 74HC123), sampling hold circuit (two sampling denoising circuit CX10045) filtering noise, vision signal after the denoising is amplified, after the shaping, is sent into analog to digital converter 6 (A/D converter is CX20052) through amplifying circuit circuit such as () 74HC04.CCD4 adopts area array CCD ICX018, and spectral region is the 0.4-1.1 micron, is of a size of 8.7mm * 6.4mm.The diaphragm clear aperature is 1.2mm * 0.9mm.
The frame speed of the utility model transducer is adjustable continuously; Image acquisition process can with the outer synchronous signal strict synchronism; Based on the commercial CCD chip of common low speed, cheap; And certainty of measurement is high and measuring speed is fast, can be good at being used for the interferometry of SPM surface topography, from fields such as motion trackings good application prospects is being arranged also.The utlity model has characteristics such as system configuration is simple, reliability is high, cost is low, measuring speed is fast, precision height, be applicable to manufacturing industry, image recognition, accurate measurement automatically, robot vision, the real-time detection in fields such as motion tracking.
Imageing sensor of the present utility model is used for the interferometry of SPM surface topography, and test shows, adopts the utility model, has realized taking out from 510 * 492 pixels of CCD 80 * 80 pixels of every frame, and frame frequency reaches 1000 frames/more than second.
Claims (5)
1, a kind of high speed image sensor-based system based on industrial CCD, be characterised in that its structure is: be close to before the photosurface of the low speed CCD (4) with adjustable drive circuit (1) and peripheral circuit (2) and place an adjustable diaphragm (3), the output of described CCD (4) connects denoising circuit (5) and analog to digital conversion circuit (6) in turn.
2, the high speed image sensor-based system based on industrial CCD according to claim 1 is characterized in that described adjustable drive circuit (1) is made of pulse-generating circuit (10), frequency dividing circuit (11), counting circuit (12), synchronous circuit (13), line-scan circuit (14), field-scanning circuit (15); The input of the phase locking frequency multiplying circuit (1001) in the described pulse-generating circuit (10) is connected with external synchronization signal S, and its output is connected with the first input end (111) of frequency dividing circuit (11), the input of counting circuit (12) respectively; The output of this frequency dividing circuit (11) is connected with the input of line-scan circuit (14), the first input end (211) of the level shifting circuit (21) in the output of this line-scan circuit (14) and the described peripheral circuit (2) is connected, and first output (213) of this level shifting circuit (21) shifts the pulse signal control end with the row of described CCD (4) and is connected; The output of described counting circuit (12) is connected with the input of described synchronous circuit (13), first output (131) of this synchronous circuit (13), second output (132) respectively with second input (112) of described frequency dividing circuit, the input of described field-scanning circuit (15) connects, second input (212) of the described level shifting circuit (21) in the output of this field-scanning circuit (15) and the peripheral circuit (2) is connected, and second output (214) of described level shifting circuit (21) shifts a pulse signal control end with the field of CCD (4) and is connected.
3, the high speed image sensor-based system based on industrial CCD according to claim 1, it is characterized in that described diaphragm (3) is the field stop that described CCD (4) sensitive volume is limited in the front of being close to the photosensitive area that is placed on described CCD (4), the size of this diaphragm (3) is not less than M * N CCD (4) pixel, its clear aperature is adjustable, is m * n CCD pixel size.
4, the high speed image sensor-based system based on industrial CCD according to claim 1 and 2 is characterized in that described external synchronization signal S is meant and the certain sine voltage signal of phase difference of CCD (4) measuring object.
5, the high speed image sensor-based system based on industrial CCD according to claim 1 is characterized in that described low speed CCD (4) is a frame transfer type area array CCD, or interline transfer type area array CCD, or frame interline transfer type area array CCD.
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| CNU2007200766590U CN201114403Y (en) | 2007-10-25 | 2007-10-25 | High-speed image sensing system based on industrial CCD |
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| CNU2007200766590U CN201114403Y (en) | 2007-10-25 | 2007-10-25 | High-speed image sensing system based on industrial CCD |
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Granted publication date: 20080910 Termination date: 20091125 |