CN201110896Y - High resolution mine geology detector - Google Patents

Abstract

The utility model relates to a high-resolution mine geological detector, comprising a set of display equipment, a set of parameter setting equipment and a power system. The utility model is characterized in that the detector also comprises a six-channel high-speed high-solution shallow seismic data acquisition system of an SOPC data acquisition and control platform based on a programmable plate, and a main case system of a 32-bit embedded processing system platform based on a PowerPC system structure. The utility model can compose an intrinsically safe type mine-use high-solution shallow seismic detecting instrument with low-power consumption and is used for mine geological exploration and engineering geological structure. Concretely speaking, the detector of the utility model can not only go beyond the exploration of the geological structures on the mine coal working face and the geological structures in front of the heading working face, but also detect the thickness and the geological structures of mine tunnel roof and floor, as well as the coal beds and terranes on both sides within a certain cope. In addition, the detector can be used for roadbed and embankment defect detection.

Description

High resolving power mine shaft geology detection instrument

Technical field:

The utility model relates to a kind of shallow seismic exploration instrument in tectonic structure exploration on every side of colliery underworkings and engineer geological prospecting field, it is mainly used in unusual tectonic structure (comprising ore bed structure, the old sky of little kiln, solution cavity, tomography and shatter belt, karst collapse col umn, splitting of coal seam and merging, Coal Seam Thickness Change, magma and rock mass structure, top board and stability of surrounding rock and the unusual little structure) forward probe in mine coal-cutting workplace and driving face the place ahead, and the thickness of coal seam in the top board in tunnel, base plate and the both sides nation certain limit and rock stratum and tectonic structure detection.In addition, the ground surface works geologic prospecting be can also be used for, the exploration of building lot tectonic structure, the exploration of dam dyke tectonic structure, highway and the exploration of railway bed tectonic structure, the exploration of airport ground tectonic structure and other engineer geological prospecting comprised.

Background technology:

Shallow seismic exploration be a youth just in flourish exploration geophysics section.It is to study the seismologic parameter on stratum and the relation between ground physical parameter and the structural parameters according to the physical characteristics that artificial excitation's seismic event is propagated in tested geologic body, determine the locus and the form of various geological interfaces, solve form, character and the structure of the little tectonic geology body of non-homogeneous complexity, and underground geologic body is comprehensively reviewed.Therefore, shallow seismic exploration is widely used in engineering geology and the environmental geology exploration.The shallow seismic exploration instrument is as the main tool and the means of shallow seismic exploration, and its each technological breakthrough has all greatly promoted the development of shallow seismic exploration theory, technology and method.

At present represent the shallow seismic exploration instrument of international most advanced level many, as the SE series engineering detection instrument of the SWS engineering exploration of the WZG series engineering seismograph of the MK series shallow layer seismograph of the ES of U.S. Geometrics company series and Geode series shallow layer seismograph, the Japanese OYO McSEIS-SX of company series shallow layer seismograph, Sweden ABEM company, the serial shallow layer seismograph of the DZQ of Chongqing Geological Instrument Factory, Chongqing ten thousand horse geophysical prospecting equipment company limiteds, Beijing water power physical prospecting research institute and detector, Jilin GeoPen company etc.The common feature of these advanced instruments is host computer system and the port numbers many (being generally more than 12 roads) that adopt based on universal PC 104 industrial computers, and power consumption is high and volume is big.These instruments are very suitable for ground surface works geologic prospecting and environmental geology exploration, but are difficult to satisfy the power consumption requirement of colliery intrinsic safety type product to instrument, therefore are not suitable for the construction geology exploration all around of colliery underworkings.

The advanced shallow seismic exploration instrument that is applied at present under the coal mine is fewer, have only the KDZ1114-3 series portable mine shaft geology detection instrument of Fuzhou Huahong Intelligent Technology Development Co., Ltd. and two kinds of products of YIR (D) R wave detection instrument of Xi of Coal Mining Research Institute, the common feature of these two kinds of instruments be low in energy consumption, volume is little and in light weight, all belong to use the intrinsic safety type product under the coal mine.Wherein, KDZ1114-3 portable mine geology detecting instrument is a super low-power consumption based on microcontroller (MCU), be integrated with the mine shaft geology detection instrument of multiple on-the-spot shallow seismic exploration method, but its A/D conversion figure place has only 12, surveys with the analyzing and processing precision to be restricted.YIR (D) R wave detection instrument is a high resolving power based on universal PC 104 industrial computers (A/D conversion figure place is 24 a) mine shaft geology detection instrument, but it provides a kind of on-the-spot detection method (Rayleigh ground roll detection method), and its range of application is restricted.

How to make full use of the shallow seismic exploration instrument advanced technology of in ground surface works geology and environmental geology engineering, using at present, and in conjunction with current embedded system and low power design technique thereof, the low-power consumption intrinsic safety type advanced person's that research and development can be used under coal mine mine shallow seismic exploration instrument is to guarantee that the construction geology safety of Coal Production presses for the problem of solution.

Summary of the invention:

In order to overcome existing ground shallow seismic exploration instrument power consumption high and mine shallow seismic exploration accuracy of instrument difference and the limited problem of range of application, the utility model provides a kind of high resolving power mine shaft geology detection instrument, it not only can make the power consumption of shallow seismic exploration instrument satisfy colliery intrinsic safety type product requirement, and can solve mine shallow seismic exploration accuracy of instrument and the limited problem of range of application.In addition, this instrument also has the little characteristics such as in light weight of volume, can solve the limited and construction site problem of bringing far away of the on-the-spot space exploration environment of mine laneway.

The utility model comprises display device, parameter setting device, power-supply system, it is characterized in that: this instrument also includes based on six passage high speed, high resolution shallow earthquake data acquisition system (DAS)s of programmable system on chip SOPC data acquisition control platform with based on the host computer system of 32 embedded processing systems platforms of PowerPC architecture.

Aspect the data acquisition system (DAS) of instrument, adopt system for acquiring seismic data based on six passages of programmable system on chip (SOPC) acquisition controlling platform independent " program control amplification+24 a high-speed a/d conversion "; Aspect the host computer system of instrument, adopt embedded system based on 32 flush bonding processors of PowerPC architecture (MPC823e); Aspect the man-machine interface of instrument, adopt the TFT-LCD module and the special PVC keyboard that has 38 keys of LED-backlit 800 * 600 resolution; Aspect machine-machine interface (being instrument and PC interface), adopt communication of 10base-T Ethernet interface and USB flash disk dump seismologic record data; Aspect power-supply system, adopt built-in lithium battery group and colliery intrinsic safety type distributed power supply system.

Aspect the data acquisition system (DAS) of instrument, adopt system for acquiring seismic data based on six passages of programmable system on chip (SOPC) acquisition controlling platform independent " program control amplification+24 a high-speed a/d conversion ", the know-why of its foundation is as follows:

(1) adopts six channel data acquisition system schemes, meet under the coal mine construction environment and satisfy mine shallow seismic exploration Technology Need.At first, because colliery underworkings site operation environmental limit, especially when the driving face carried out forward probe, the width of face generally can not surpass 3 to 4 meters, adopted the six passage seismologic record data acquisitions that are total to shot point normally proper.Secondly, can satisfy the needs of most shallow seismic exploration methods.For example, Rayleigh ground roll exploration, zero-offset reflection exploration, offset distance reflection exploration altogether, optimized migration are apart from the detection etc. automatically of reflection exploration, monolateral refraction shooting, bilateral refraction shooting, the well logging of PS ripple and tunnel roof and floor thickness of coal seam.The 3rd, not only can satisfy the on-the-spot needs of surveying, and the power consumption of lowering apparatus greatly.At present, in ground surface works geology and environmental geology exploration, the data acquisition channel number of employed shallow seismic exploration instrument is generally 24 roads or 48 roads, that have even reach highly to 72 roads, this provides the effective means that reduces on-the-spot detection operations amount and improve exploration efficiency for engineer geological prospecting and environmental geology exploration.But, bring negative problem quite a few, it not only makes the volume and weight of instrument increase, and has greatly increased the power consumption of instrument.Obviously, adopt number more shallow seismic exploration instrument in road to be not suitable for the mine laneway geologic prospecting.

(2) adopt independently " program control amplification+24 a high-speed a/d conversion " data acquisition channel of per pass, not only can simplify each data acquisition channel design, reduce each passage power consumption and improve anti-cross-talk ability between the passage, and can reduce instrument data noise that acquisition channel produces to greatest extent, thereby improve seismic signal signal to noise ratio (S/N ratio) and resolution to a certain extent.At present, most shallow seismic exploration instruments all embed hardware filtering circuit or floating-point amplifying circuit in data acquisition channel.Wherein, the purpose of embedded hardware filtering circuit is an interference wave and the signal to noise ratio (S/N ratio) that improves seismologic record in the compacting earthquake record data.But, because seismic event is the communication process process of a complexity normally in tested geologic body medium, instrument collect is the composite wave of an interference wave and significant wave aliasing from the seismic signal of wave detector, the single hardware frequency wave filter of sampling is to suppress the interference wave of interfering mutually with significant wave in the seismic signal under many circumstances, can increase noise of instrument own and reduction on the contrary from the signal to noise ratio (S/N ratio) than the faint seismic signal of deep layer.Therefore, in the data acquisition system (DAS) of shallow seismic exploration instrument, do not establish preposition hardware filtering device, and in latter earthquake record data process software, strengthen numerical frequency filtering and digital smear means of filtering has become present a kind of obvious development trend.Simultaneously, can also fundamentally eliminate, and simplify the instrument data system architecture and reduced power consumption and cost because of the hardware filtering circuit embeds the noise of introducing.The purpose that embeds the floating-point amplifying circuit in data acquisition channel is to improve the dynamic range of instrument data acquisition system, because early stage A/D converter technical limitation, its figure place is generally 12～16, embeds the floating-point amplifying circuit and have very big effect for improving instrument dynamic range in data acquisition channel.But advanced at present high resolving power shallow seismic exploration instrument generally all adopts 24 A/D converters, can satisfy shallow seismic exploration fully to the instrument dynamic range requirement.In addition,, in the data acquisition circuit of instrument, add such circuit, must cause the noise and the power consumption of the forward path of acquisition system to increase, be unfavorable for from the input of seismic wave faintly than deep layer because hardware floating-point amplifying circuit is very complicated.Therefore, floating-point amplifying circuit during the cancellation forward path is logical, and in the seismologic record data processing software, increase digitizing floating-point magnify tool, not only can fundamentally eliminate the problem that the floating-point amplifying circuit is caused, and guaranteed that original seismic data reflects seismic event propagation condition in medium truly, thereby made things convenient at the scene correct judgement the earthquake tracer signal.

(3) employing is based on the data acquisition system (DAS) scheme of system on the upper side able to programme (SOPC) acquisition controlling platform, not only can solve the seismic signal data acquisition control problem of shallow seismic exploration hole instrument high-speed complexity, and cause different sampling control methods in collecting method difference can adapt to the shallow seismic exploration instrument and be integrated with multiple method of exploration the time.Aspect the data acquisition system (DAS) control of the utility model instrument, need the project of control to have: the port number that participates in sampling, the program control preposition simulation of four class is amplified, sampling interval, sampling number, leading sampling number, the sampling time-delay, sampling starts triggering mode and (comprises internal trigger, external trigger, lacking earlier afterwards breaks triggers and short triggering of having no progeny earlier) and trigger voltage, and tested geologic body ground unrest detects, realize so many parameter item destination data acquisition controlling, and finish the parameter setting and the A/D conversion and control at a high speed of continuous item in phase, adopt single software program or pure hardware control logic to control suitable difficulty, the method that must adopt software and hardware to combine realizes.For this reason, introducing altera corp's programmable system on chip (SOPC) technology aspect the data acquisition system sampling control of instrument, it not only can realize the required high-speed sampling hardware logic control of data acquisition system (DAS) on single-chip, and can on chip, embed 32 soft nuclears of NIOS-II flush bonding processor, thereby on single-chip, solved the problem of the software and hardware combining of shallow seismic exploration instrument data acquisition system controlling of sampling, simplified the multiple tracks high-speed data acquisition controlling Design problem of instrument greatly, reduced at instrument in the power consumption aspect the acquisition controlling, and the data acquisition system (DAS) that makes instrument effectively is as an independent data acquisition platform.In addition, owing in data acquisition system (DAS), adopted data acquisition control platform based on SOPC, therefore, also can utilize the programmable features of SOPC chip aspect two of hardware and softwares to be solved even different shallow seismic exploration methods has different requirements to data acquisition controlling aspect.

Aspect the host computer system of instrument, adopt embedded system based on 32 flush bonding processors of PowerPC architecture (MPC823e), the know-why of its foundation is as follows:

(1) sampling as the host computer system hardware platform, helps the power consumption of lowering apparatus aspect host computer system based on the embedded system of 32 flush bonding processors of PowerPC architecture (MPC823e).At present, determine most of advanced persons' shallow seismic exploration instrument all adopts general PC/104 industrial computer as instrument host system hardware platform.Adopt the advantage of such technical scheme to be, can utilize at present the very universal PC of mature and reliable/104 industrial computer OEM products, accelerate the instrument development progress.But also there is certain inferior position in the method.The OEM product of first PC/104 series is the universal product for the industrial control equipment exploitation, its low consumption problem when design is not the emphasis of considering, and have the unwanted circuit module of shallow seismic exploration instrument host system onboard, this has increased the host computer system power consumption of instrument virtually, for the shallow seismic exploration instrument that uses in ground surface works geology and the environmental engineering geology exploration, increasing these power consumptions may influence and not be very big, but for the mine shallow seismic exploration instrument that uses under the coal mine, sometimes may be fatal, this be because mine intrinsic safety holotype equipment requires restriction to cause to power consumption.It two is because PC/104 industrial computer series product is a kind of OEM product of maturation, and its price comparison height will cause the cost of product to increase.At present, become based on the embedded system of 32 flush bonding processors and to have measured and control product main flow, it is very ripe technically and have a series of advantages.The characteristics of this type of flush bonding processor maximum are on single processor chips integrated the needed various peripheral control units of observing and controlling product (comprising man-machine interface controller, machine-machine communication controler, serial and parallel expansion interface controller), and when chip design, just considered low-power consumption and use problem thereof, possessed the essential characteristic of low-power consumption system-on-a-chip.32 flush bonding processors of the utility model instrument host MPC823e that system adopts are exactly a integrated 32 embedded processing kernels, lcd controller, I2C controller, ethernet controller, SPI controller and the UART controller of PowerPC architecture, and RISC architecture 32 8-digit microcontrollers that have the DSP function are provided.Therefore, it not only can satisfy the primary demand of shallow seismic exploration instrument host system to hardware platform, and needs carried out the requirement that quick filter is handled when the shallow seismic exploration instrument is on-the-spot to be surveyed but also can satisfy.Therefore, the utility model host computer system scheme adopts the embedded system based on 32 flush bonding processors of MPC823e.It has that power consumption is little, cost is low and characteristics such as specificity with comparing based on the host computer system of PC/104 industrial computer, but also there is certain shortcoming, promptly need to research and develop voluntarily, the development progress of instrument is slow, and need expend certain human and material resources and financial resources, and there is not mature enough problem in exploitation first.But, in case succeed in developing the effect of putting things right once and for all with obtaining.The more important thing is, independently developed instrument host hardware platform can need design by shallow seismic exploration instrument host system, do not have unnecessary functional module, the power consumption of main control system system and cost to greatest extent, and can reduce arbitrarily as required, this be based on the PC/104 industrial computer the host computer system scheme can't realize.

(2) sampling based on the embedded system of 32 flush bonding processors of PowerPC architecture (MPC823e) as the host computer system hardware platform, can adopt the built-in Linux operating system that to reduce, reduce the storage system capacity requirement of operating system, thereby reduced the power consumption of host stores system instrument host.At present, employing is based on the host computer system of PC/104 industrial computer, the core of its software systems adopts Windows operating system usually, Windows operating system is that a kind of software product and code capacity of non-open source code is bigger, the user can't freely reduce it, and this must cause the memory capacity of instrument host system to increase.For the shallow seismic exploration instrument that adopts solid-state disk, the memory capacity increase will cause storage chip to increase, and the storage chip increase will cause the power consumption of host computer system to increase and cost increases.Yet, host computer system based on 32 flush bonding processors, usually adopt the core of built-in Linux operating system as software systems, built-in Linux operating system is a kind of operating system of increasing income, can freely reduce, can drop to the operating system code capacity minimum according to the detection and the process software demand of instrument, thereby reduced instrument host system memory size expense, the power consumption of the host computer system that reduces.

Aspect the man-machine interface of instrument, adopt the TFT-LCD module and the special PVC keyboard that has 38 keys of LED-backlit 800 * 600 resolution, the know-why of its foundation is as follows:

(1) aspect the display of instrument, adopt the TFT-LCD module of LED-backlit 800 * 600 resolution, guarantee that LCD display backlight circuit supply voltage meets the requirement of mine intrinsic safety type product, and provide hardware foundation for the graphic user interface of instrument (GUI) platform.It is the indispensable basic functions of seismic prospecting instrument that the seismologic record waveform shows, so graphic alphanumeric display is the assembly of shallow seismic exploration instrument indispensability.At present, the graphic alphanumeric display that the shallow seismic exploration instrument is adopted has two major types, i.e. LCD display and CRT monitor.Because some intrinsic defectives of CRT monitor existence itself (big as volume, voltage is high and power consumption high), so LCD display becomes the main display device of current shallow seismic exploration instrument.For ground shallow seismic exploration instrument, which kind of backlight is the LCD module adopt is not the focus that design is paid close attention to, but to mine shallow seismic exploration instrument, because mine intrinsic safety type product standard restriction, it is inappropriate adopting high-frequency and high-voltage CCFT backlight, must adopt the LED-backlit source of Low-voltage Low-power.What the utility model adopted is 800 * 600 resolution Via Color TFT-LCD modules (LQ104S1DG21), and it is CCFT that its backlight adopts, and obviously is not meet mine intrinsic safety type product requirement.Therefore, must transform its backlight, remove original CCFT backlight, the low-voltage LED backlight that makes into to design voluntarily is so that be fit to mine intrinsic safety type product requirement.

(2) aspect the keyboard of instrument, adopt the special PVC keyboard have 38 keys, combine together with the panel of instrument, be convenient to the integrally-built sealing of instrument, be the moistureproof dustproof basis that provides of instrument.The keyboard special of instrument is positioned at the bottom of instrument panel, has 38 keys, is divided into 4 keypads, i.e. numeric keypad, function key area, power control key district and brilliance control keypad.Wherein, the numeric keypad is positioned at the lower right corner (having 16 keys) of panel, comprises 10 numerical keys, 1 acknowledgement key and 4 calculation keys (add, subtract, take advantage of and remove); Function key area is positioned at the lower left corner (having 16 keys) of panel, comprises 4 direction keyboards (left and right, upper and lower), 4 page keies (going up page or leaf, nextpage, beginning of the page, page footing), 3 editing keies (insertion, deletion and backspace), 2 keyboard control keys (perform, keying), 1 state switch key (Tab), 1 sample key and 1 ESC Escape; The power control key district is positioned at the middle part, the end of instrument panel and takes back (having 3 keys), comprises power supply "on" and "off" key and reset key; The middle part took over (having 3 keys) at the bottom of LCD brilliance control keypad was positioned at panel, comprised increase brightness key (+), reduced brightness key (-) and brightness preservation key.

Aspect machine-machine interface (being instrument and PC and peripheral interface thereof), adopt 10base-T Ethernet and PC to realize communication interface and USB flash disk dump seismologic record data, the know-why of its foundation is as follows: the 10base-T ethernet controller that directly utilizes the MPC823e flush bonding processor to be provided, and external corresponding transceiving driver constitutes the communication interface of instrument and background PC computer; Directly utilize the USB controller of 1.1 versions that the MPC823e flush bonding processor provided, circumscribed USB transceiving driver and USB HUB chip constitute the USB interface of the seismologic record data conversion storage of instrument.

Aspect power-supply system, adopt built-in lithium battery group and colliery intrinsic safety type distributed power supply system, the know-why of its foundation is as follows: electric battery adopts 2 electric core series connection to add fender, and every standard is 3.7V/10Ah.Current-limiting resistance and the distributed power supply system of the external 1.5 Ω/50W of electric battery, the mine intrinsic safety type power supply of formation instrument.Wherein, distributed power supply system is made up of 6 tunnel low pressure reduction voltage stabilizings and DC-DC translation circuit and power control switch circuit, be respectively sampling plate provide+5V ,-5V and+the 3.3V power supply, for mainboard and controlling of sampling plate provide+5V and+3.3V power supply, the dimmable backlights power supply that provides 1.2～3.2V to have memory function for the LED-backlit of LCD module.

Advantage of the present utility model has: can constitute the shallow-layer high resolving power shallow seismic exploration instrument of low-power consumption mine intrinsic safety type, be used to survey mine shaft geology and engineering geology structure.Specifically, not only can forward probe mine coal-cutting workplace and the tectonic structure (comprising tomography and shatter belt, karst collapse col umn, old kiln goaf, solution cavity, splitting of coal seam and merging, Coal Seam Thickness Change, magma and rock mass structure, top board and stability of surrounding rock, ore bed structure, little structure etc.) in driving face the place ahead; And can survey the coal seam in mine laneway top board and base plate, the both sides nation certain limit and the thickness and the tectonic structure of rock stratum.In addition, can also be used for road foundation and dyke defect detection.

Description of drawings:

Fig. 1 is the utility model hardware system ultimate principle block diagram;

Fig. 2 is that the utility model is based on programmable system on chip (SOPC) high speed, high resolution shallow earthquake data acquisition system (DAS) block diagram;

Fig. 3 is that the simulating signal of the utility model acquisition system is amplified buffer circuit I (first three passage);

Fig. 4 is that the simulating signal of the utility model acquisition system is amplified buffer circuit II (back three passages);

Fig. 5 is six passages, 24 A/D change-over circuits independently of the utility model acquisition system;

Fig. 6 is the sampling trigger starting circuit with four kinds of triggering modes of the utility model acquisition system;

Fig. 7 is based on the data acquisition control platform block diagram of programmable system on chip (SOPC);

Fig. 8 is programmable system on chip (SOPC) the sheet inner joint circuit of the utility model data acquisition control platform;

Fig. 9 is the clock generating circuit and the configuration circuit of the utility model data acquisition control platform;

Figure 10 is the program and the data-carrier store (SRAM) of the utility model data acquisition control platform;

Figure 11 is the dual port bus on-off circuit of the utility model data acquisition control platform;

Figure 12 is the interface circuit of the utility model data acquisition control platform;

Figure 13 is the interface circuit of the utility model acquisition system and data acquisition control platform;

Figure 14 is the sampled data storer (SRAM) of the utility model acquisition system;

Figure 15 is the sampled data memory read write control circuit of the utility model acquisition system;

Figure 16 is the interface circuit of the utility model acquisition system and host computer system;

Figure 17 is the interface circuit of the utility model acquisition system and power-supply system;

Figure 18 is 32 the embedded host system charts of the utility model based on the PowerPC architecture;

Figure 19 is the MPC823e flush bonding processor circuit of the utility model host computer system;

Figure 20 is real-time clock, battery detection and the I/O expanded circuit of the utility model host computer system;

Figure 21 is address bus, data bus and the control bus driving circuit of the utility model host computer system;

Figure 22 is the SDRAM storage system of the utility model host computer system;

Figure 23 is the Flash storage system (Flash storage card) of the utility model host computer system;

Figure 24 is the man-machine interface circuit of the utility model host computer system;

Figure 25 is the machine-machine interface circuit of the utility model host computer system;

Figure 26 is serial monitoring and the test and the debug circuit of the utility model host computer system;

Figure 27 be the utility model host computer system power supply, reset and clock circuit;

Figure 28 is the interface circuit of the utility model host computer system and acquisition system and Flash storage system;

Figure 29 is the machine-machine communication switching box circuit of the utility model based on USB HUB;

Figure 30 is the built-in intrinsic safety holotype power-supply system block diagram of the utility model;

Figure 31 is the built-in intrinsic safety type power system circuit of the utility model.

Embodiment:

The utility model comprises display device, parameter setting device, power-supply system, and this instrument also includes based on six passage high speed, high resolution shallow earthquake data acquisition system (DAS)s of programmable system on chip SOPC data acquisition control platform with based on the host computer system of 32 embedded processing systems platforms of PowerPC architecture.Described image display is the display based on LED-backlit 800 * 600 resolution Via Color TFT-LCD modules; Described parameter setting device is the special PVC panel based on 38 keys of four keypads; Described power-supply system is the intrinsic safety type power-supply system based on the lithium battery group; Describedly become the controlling of sampling plate based on programmable system on chip SOPC data acquisition control platform independent design, six passage high speed, high resolution shallow earthquake data acquisition system (DAS) independent design become sampling plate, become motherboard based on 32 embedded processing systems platforms of PowerPC architecture independent design.

Independently form by analog input channel, trigger control circuit, controlling of sampling plate interface, sampled data storer and read-write control logic circuit, motherboard interface and power interface by 6 for above-mentioned six passage high speed, high resolution shallow earthquake data acquisition system (DAS)s; Each analog input channel contains simple component wave detector interface, capacitance-resistance buffer circuit, programmable amplifying circuit, amplification buffer circuit and 24 high-speed a/d change-over circuits, described program control gain amplifier shelves are designed to 0dB, 24dB, 36dB and 48dB, and the sampling interval of A/D change-over circuit is designed to the multiple of 16 microseconds; Trigger control circuit contains and trigger to start interface, preposition trigger pip buffer circuit, triggering mode and select circuit, activation threshold value circuit to be set, to trigger and start comparator circuit and rearmounted trigger pip buffer circuit, realizes internal trigger, external trigger, has no progeny and shortly trigger and lack earlier the four kinds of optional triggering modes of triggering that afterwards break earlier; Sampled data storer and read-write control logic circuit thereof contain 2 256kB * 16 high-speed cmos SRAM, 8 and have eight bus transceivers of direction pin, 1 bus buffer, 1 four logical AND gate chip and pull-up resistor, and the capacity of sampled data storer is 1MB.

Above-mentioned based on programmable system on chip SOPC data acquisition control platform by programmable system on chip SOPC chip, clock generator circuit, serial Flash configuration data memory and interface thereof, directly configuration interface, configuration control indicating circuit, 1MB SRAM program data memory, power circuit and interface, dual port bus on-off circuit, sampled data memory interface and other expansion interface are formed; Programmable system on chip SOPC chip is embedded with the soft nuclear of general NIOS-II32 position flush bonding processor, specialized high-speed data acquisition control IP kernel and sampled data memory read/write control IP kernel.

Above-mentioned based on 32 embedded processing systems platforms of PowerPC architecture by 32 flush bonding processors based on the PowerPC architecture, bus driving circuits, the SDRAM storage system, the Flash storage system, the LCD display interface, the keyboard special interface circuit, ethernet interface circuit, usb circuit, machine-machine communication interface, power circuit, reset circuit, clock circuit, real time clock circuit, battery detection circuit, the I/O port expansion circuit, debugging and test interface circuit, serial monitor-interface circuit and sampling plate interface are formed; 32 flush bonding processors based on the PowerPC architecture adopt the MPC823e processor, bus driving circuits is made up of 88 bus transceivers with direction pin, the 32MB that the SDRAM storage system is made up of 4 SDRAM chips～128MB capacity is storage system at random, the 16MB that the Flash storage system is made up of 4 Flash memory chips～64MB capacity flash memory system, 64 keyed jointing mouth circuit that the keyboard special interface circuit is made up of 2 long-range 8 I/O extended chips of I2C bus, ethernet interface circuit is made up of general 10base-T Ethernet transceiver, usb circuit is made up of the USB universal serial bus transceiver, power circuit is by host computer system debugging power circuit, PLL power circuit and power switch circuit are formed, reset circuit is by the chip and have electrification reset and the software and hardware reset circuit that the dual reset chip of push button function is formed of resetting that draws output on having, clock circuit is by the 8MHz master clock circuit, 32.768kHz auxilliary clock circuit and 48MHz USB clock circuit are formed, real time clock circuit is by I2C bus interface real-time timepiece chip, have that the controller chip of battery detection and button cell form, battery detection circuit is made up of 8 A/D converters of serial line interface, what the I/O expanded circuit adopted is long-range 8 the I/O extended chips of I2C bus, and serial monitor-interface circuit is made up of RS232 serial transceiving chip and transient voltage suppressor.

In Fig. 1, will arrange wave detector according to the construction recording geometry of various different method of exploration, and wave detector will be connected to the wave detector interface by cable, excite the triggering of starter to start cable man-made explosion and be connected to triggering startup interface.At tested geologic body upper epidermis by the man-made explosion earthquake-wave-exciting, produce and trigger enabling signal, deliver to data acquisition platform by the sampling enabling signal that trigger control circuit obtained among Fig. 1, according to the sampling parameter that sets in advance and sample mode start 1～6 independently analog input channel carry out data sampling.Consecutive shock signal from wave detector, controlling of sampling algorithm according to the data acquisition control platform among Fig. 1, change digital signal into by capacitance-resistance buffer circuit, programmable amplifying circuit, amplification buffer circuit and A/D change-over circuit in the analog input channel, be kept at last in the sampled data storer of Fig. 1.The sampled data memory read/write control logic circuit that 32 embedded system platforms among Fig. 1 pass through, the seismologic record data that are kept in the acquired data storage device are read in its SDRAM accumulator system, and be presented on the Via Color TFT-LCD display module among Fig. 1, finally the file with certain format is saved in its Flash storage system.Controllably shake the demonstration and the processing mode of wave recording by the special PVC keyboard among Fig. 1, and various parameters such as sampling triggering startup and controlling of sampling are set.If the seismologic record file transfer that needs to be kept at the Flash accumulator system is handled and interpretation software to the seismic event that is arranged on the background PC computer, can be by the ethernet interface circuit among Fig. 1, and, be transferred in the PC through the machine-machine communication switching box among Fig. 1.If the seismologic record file that needs to be kept at the Flash accumulator system dumps in the USB flash disk, can pass through the usb circuit among Fig. 1, and be saved in the USB flash disk of standard through the machine-machine communication switching box among Fig. 1.Standard USB keyboard also can be connected to the usb circuit among Fig. 1 by the machine among Fig. 1-machine communication switching box, as the external keyboard of instrument, with convenient indoor use and operation.Instrument if the lithium battery group there is not electricity or electric weight deficiency, can use the special charger of instrument configuration by intrinsic safety type power system circuit all Circuits System power supplies in Fig. 1 based on the lithium battery group among Fig. 1, by the charging inlet among Fig. 1 to batteries charging.Divide several sections that the utility model embodiment is further specified below in conjunction with drawings and Examples.

One, the sampling plate of acquisition system

Acquisition system is made up of sampling plate and controlling of sampling plate, and its major function is to finish the earthquake signals collecting, and by certain algorithm the seismologic record data is kept in the sampled data storer.The block scheme of acquisition system as shown in Figure 2, it is to be core with the data acquisition control platform based on programmable system on chip among Fig. 2 (employing control panel), is a complete high speed, high resolution shallow earthquake data acquisition system (DAS) with 6 analog input channels.

6 analog input channels among Fig. 2 all are made up of wave detector interface, capacitance-resistance buffer circuit, program control amplification, amplification buffer circuit and A/D change-over circuit.Wherein, the wave detector interface of 6 passages, capacitance-resistance buffer circuit, program control amplification and amplification cushioning principle circuit are as shown in Figure 3 and Figure 4.Each channel circuit among Fig. 3 and Fig. 4 all is channel interface, capacitance-resistance buffer circuit, instrumentation amplifier, pre-amp gain switching switch circuit and amplifies buffer circuit and form.Wherein, the capacitance-resistance buffer circuit of each passage all is made up of block condenser and resistance, sees CA7 and CA8, CB7 and CB8, CC7 and CC8, CD7 and CD8, CE7 and CE8, CF7 and CF8 and related resistors thereof among Fig. 3 and Fig. 4.What instrumentation amplifier adopted is accurate low-power consumption instrumentation amplifier INA128 (seeing U1N, U2N, U3N, U4N, U5N and U6N among Fig. 3 and Fig. 4), and itself and 4 passage multidiameter option switch ADG604 (seeing U1M, U2M, U3M, U4M, U5M and U6M among Fig. 3 and Fig. 4) constitute program-controlled pre-amplification circuit.Pre-amp gain is designed to 4 grades, is respectively 0dB, 24dB, 36dB and 48dB.Amplify buffer circuit and adopt high-performance fully differential AUDIO OP amplifier OPA1632 (seeing U1H, U2H, U3H, U4H, U5H and U6H among Fig. 3 and Fig. 4), the single-ended output of instrumentation amplifier INA128 is become meet the balanced differential output that A/D converter requires.The reference voltage of OPA1632 amplifier is by the reference voltage device R EF3125 of accurate low-power consumption (seeing U1J, U2J, U3J, U4J, U5J and U6J among Fig. 3 and Fig. 4).Each passage of 6 pattern input channels among Fig. 2 all adopts an independently A/D change-over circuit, as shown in Figure 5.The core devices of A/D change-over circuit is 24 bit wide band high-speed AD converter ADS1271 (seeing UAD1, UAD2, UAD3, UAD4, UAD5 and UAD6 among Fig. 5).The pattern control of the A/D converter of six passages is provided by quick cmos buffer driver PI49FCT3805 (seeing the U9 among Fig. 5) output signal, the function of this device is that single input is become multichannel output, has guaranteed the translative mode unanimity of the A/D converter of each passage.The circuit that the reference voltage of the A/D converter of six passages is made up of accurate low-power consumption reference voltage device R EF3125 (seeing the U24 among Fig. 5) and speed buffering amplifier OPA350 (seeing the U25 among Fig. 5) provides, precision and stability that it can fine assurance A/D converter reference voltage.The changeover control signal of the A/D converter of six passages is to be provided by the data acquisition control platform (see figure 7) based on programmable system on chip, can realize each passage synchronized sampling, sampling interval is the multiple of 16us, promptly 16us, 32us, 48us ..., select arbitrarily in the 160000us scope, and dynamic range reaches 120dB.

Sampling trigger control circuit major function among Fig. 2 is trigger to start acquisition system to sample, and alternative four kinds of triggering modes are provided, and comprises internal trigger, external trigger, has no progeny and shortly trigger and lack earlier the triggering of afterwards breaking earlier.It is selected by triggering startup interface, preposition trigger pip buffer circuit, triggering mode, and circuit, activation threshold value are provided with circuit, triggering starts comparator circuit and rearmounted trigger pip buffer circuit is formed, as shown in Figure 6.Wherein, preposition trigger pip buffer circuit is made up of two-way Zener breakdown type moment overvoltage su re or 1SMB10CAT3 family device (seeing TVS1, TVS2 and TVS3 among Fig. 6) and two high speed mosfet driver TPS2813 (seeing the U12 among Fig. 6), its major function is moment overvoltage and the over-current signal that suppresses from triggering the startup interface, to obtain the triggered as normal enabling signal.Triggering mode selection circuit is made up of CMOS simulation multidiameter option switch device CD4051 (seeing the U13 among Fig. 6), and its major function is to select the trigger pip of four kinds of different triggering modes.Wherein, the trigger pip of internal trigger mode is exported from the U1N among Fig. 3, external trigger, have no progeny the short trigger pip that triggers and lack earlier the triggering mode that afterwards break from triggering startup interface (seeing the JQD among Fig. 6) earlier, and triggering mode selection control signal is from the data acquisition control platform (see figure 2).Activation threshold value is provided with circuit by two digital regulation resistance X9313 (seeing U14 and U16 among Fig. 6), and its major function is to start the positive and negative threshold voltage signal that comparer provides comparison for triggering, and the control signal of digital regulation resistance is from data acquisition control platform.Triggering startup comparator circuit is made up of two differential comparator LM2093 (seeing the U15 among Fig. 6), and its major function is the trigger pip that obtains to start the acquisition system sampling.Rearmounted trigger pip buffer circuit is made up of two 9013 triodes (seeing T1 and T2 among Fig. 6), its major function is to realize that level and signal polarity conversion and signal amplify, and starts trigger pip the most at last and offer the data acquisition control platform (see figure 2).

Acquisition system shown in Figure 2 is made up of sampling plate and controlling of sampling plate, the built-in six tunnels analogy input circuits of sampling plate,, A/D change-over circuit, sampling start triggering circuit, sampled data storer and read-write control logic circuit thereof.Interface is that its major function is a grafting controlling of sampling plate by 3 dual-in-line sockets (seeing J1, J3 and J3B among Figure 13) between sampling plate and the controlling of sampling plate, realize sampling plate and controlling of sampling plate mechanical and electric on be connected.

Sampled data storer among Fig. 2 as shown in figure 14, it is made up of two 256K * 16 high-speed cmos sram chip IDT71V416S (seeing U39 and U40 among Figure 14), its major function is to preserve data acquisition control platform to collect six passage seismologic record data, deposit acquisition system setting and controlled variable, and realize communicating by letter between 32 embedded system platforms (motherboard) and the data acquisition control platform (controlling of sampling plate) from 32 embedded system platforms (motherboard).

Sampled data memory read/write control logic circuit among Fig. 2 as shown in figure 15, it is (to see the U28 among Figure 15 by 8 eight bus three-state transceiver 74LCX245 with direction pin, U31, U32, U33, U34, U35, U36 and U37), the four bus buffer AM74HC1G125 (seeing the U30 among Figure 15) of 1 ternary output and 1 four dual input (are seen the U29A among Figure 15 with door SN74HC08, U29B, U29C and U29D) to form, its major function is to realize that 32 embedded system platforms (motherboard) read and write control to sampled data storer (seeing Figure 14).Wherein, U31, U32, four 74LCX245 of U33 and U34 form 32 ternary data bus buffers of 32 embedded system platforms (motherboard) and sampled data memory interface, the end of these four 74LCX245 (A end) is connected with 32 embedded system platforms (motherboard) data bus, the other end (B end) is connected with the data bus of sampled data storer (seeing the U39 and U40 of Figure 14), its data transfer direction control is to control (seeing the DGPLA10 among Figure 15) by exporting from the read control signal of 32 embedded system platforms (motherboard) and by U28, and it is by controlling (seeing the CS40 among Figure 15) from the sheet selected control system signal of 32 embedded system platforms (motherboard) and by U30 output that data transmission allows control signal control.U35, three 74LCX245 of U36 and U37 form 24 three-state address bus buffers of 32 embedded system platforms (motherboard) and sampled data memory interface, the end of these three 74LCX245 (A end) is connected with 32 embedded system platforms (motherboard) address bus, the other end (B end) is connected with the address bus of sampled data storer (seeing the U39 and U40 of Figure 14), because address bus signal is always from 32 embedded system platforms (motherboard), therefore the direction of these three 74LCX245 is controlled pin DIR and is connect 3.3V power supply (seeing the VCC3.3 among Figure 15), and the address signal transmission allows control signal control still by controlling (seeing the CS40 among Figure 15) from the sheet selected control system signal of 32 embedded system platforms (motherboard) and by U30 output.This a slice of U28 74LCX245 forms the read-write control bus of 32 embedded system platforms (motherboard) and sampled data memory interface, U28 one end (A end) is connected with 32 embedded system platforms (motherboard) read-write control bus, the read-write control logic circuit of the other end (B end) and sampled data control store (is seen U29A among Figure 15～D) be connected, because read-write control bus signal is always from 32 embedded system platforms (motherboard), therefore the direction of U28 is controlled pin DIR and is connect 3.3V power supply (seeing the VCC3.3 among Figure 15), and the read-write transmission allows control signal control still by controlling (seeing the CS40 among Figure 15) from the sheet selected control system signal of 32 embedded system platforms (motherboard) and by U30 output.U29A, U29B, U29C and U29D are positioned at the chip with a slice SN74HC08, have constituted 32 embedded system platforms (motherboard) and the read-write control logic circuit of data acquisition control platform (controlling of sampling plate) to the sampled data storer by it.The input signal DWE L00 of the input signal DWE L20 of input signal DGPLA10, the U29C of input signal CS40, the U29B of U29A and U29D, output with U30 and U28 is connected respectively, and these signals are from the sheet choosing and the read-write control signal of 32 embedded system platforms (motherboard) control bus; And the input signal AD_SRAM_WE of the input signal of input signal AD_SRAM_RD, the U29C of input signal AD_SRAM_CS, the U29B of U29A and U29D, from the sheet choosing and the read-write control signal of the control bus of data acquisition control platform (controlling of sampling plate); U29A, U29B, the output signal of U29C and U29C is connected with the chip selection signal pin of sampled data storer (seeing U39 and U40 among Figure 14) (seeing the CS_n among U39 and the U40) respectively, read signal pin (seeing the OE_n among U39 and the U40) is connected with write signal pin (seeing the WE_n among U39 and the U40) and is connected, thereby formed 32 embedded system platforms (motherboard) and data acquisition control platform (controlling of sampling plate) steering logic that storage can be read and write to sampled data, realized read-write control and the data communication between them thereof of motherboard and controlling of sampling plate the sampled data storer.It should be noted that to be connected with respectively in the output of U28 and U29 and draw electricity group R48, R49, R50 and RN1, purpose is to guarantee that its output signal has stable signal level at one's leisure.Because from the chip selection signal CS4 of 32 embedded system platforms (motherboard) need (seeing U28 among Figure 15～U39) be connected increases its driving force by AM74HC1G125 bus buffer (seeing U30), and its output signal is CS40 with 9 chips.

Acquisition system among Fig. 2 and host system interface are as shown in figure 16.Wherein, JCYB1, JCYB2 and JREST are the bus interface sockets of 32 embedded system platforms (motherboard), it is realized the machinery of motherboard and sampling plate and is electrically connected, is respectively data bus, address bus and control bus signal and I/O signal that sampling plate and controlling of sampling plate provide 32 embedded system platforms (motherboard).JJ is the socket of acquisition system (sampling plate) and keyboard interface, and signal wire supply socket direct and on the sampling plate is connected (seeing that the JD among Figure 17 connects) in this socket.Wherein, control signal SWON1 in the JJ socket, SWON2 and SWOF1 are power switch and reset signal, its the most original control signal is used for the open and close of control instrument power supply and resetting of instrument system from the power control key district of instrument panel PVC keyboard special; Control signal ASE in the JJ socket, PU and PD are the LED-backlit brilliance controls of TFT-LCD module and preserve signal, its the most original control signal is from the brilliance control keypad of instrument panel PVC keyboard special, is used to increase or reduces the brightness of LED-backlit and the brightness setting of preserving LED-backlit.JPOWER is the supply socket that sampling plate is connected with motherboard, the power-supply system of instrument by this socket for motherboard provide+3.3 and+the 5V power supply, and provide the battery detection signal for the battery detection circuit of motherboard.

Acquisition system among Fig. 2 and power source system interface circuit are as shown in figure 17.Wherein, power interface socket (seeing the JD among Figure 17) for the LED-backlit of sampling plate, controlling of sampling plate, motherboard and TFT-LCD module provide+5V ,-5V ,+being electrically connected of 3.3V power supply and backlight electric power, and provide control and detection signal for power supply control, backlight control and battery detection.In addition, the relevant pin with JD of charging inlet (seeing the JC among Figure 17) directly connects, and it provides charging gang socket for the charging inlet that is positioned on the instrument panel.U22 among Figure 17 adopts low-voltage difference adjustor LT1763, and it provides+the 1.5V power supply for the programmable system on chip chip on the controlling of sampling plate.

Two, the controlling of sampling plate of acquisition system

The data acquisition control platform based on programmable system on chip among Fig. 2 directly is designed to an independently controlling of sampling plate, this data acquisition control platform block diagram as shown in Figure 7, its by programmable system on chip (SOPC) chip, clock generating circuit, serial Flash config memory and interface thereof, directly dispose SOPC interface, program and data-carrier store, dual port bus on-off circuit and interface circuit and form, major function is to finish the data acquisition control and the data storage of acquisition system.

Programmable system on chip among Fig. 7 (SOPC) chip adopts the SOPC chip EP1C20 of Cyclone FPGA series.This SOPC chip has following characteristic: have 20060 logic elements (LEs), 64 M4K RAM pieces (every is 128 * 36) have 294912RAM position (36864 byte), support by low-cost series arrangement cell configuration, support LVTTL, LVCOMS, SSTL-2 and SSTTL-3I/O standard, 32 PCI standards of 66-MHz and low speed (311Mbps) LVDS I/O, 2 phaselocked loops (PLL) that clock multiplier and phase shift can be provided, support comprises DDR SDRAM (133MHz), the external memory storage of FCRAM and single data rate (SDR) SDRAM, and support multiple intellecture property (IP) nuclear (IP kernel that comprises the multiple Altera SOPC standard of 32 soft nuclears of flush bonding processor of NIOS-II), chip is for the BGA encapsulation and 301 user I/O pins are provided.The utility model has been embedded in 32 general soft nuclears of NIOS-II flush bonding processor, special-purpose high-speed data controlling of sampling IP kernel and the sampled data memory read/write control IP kernel of exploitation voluntarily at the SOPC of Fig. 7 chip EP1C20, and with the interface circuit of external devices.SOPC chip among Fig. 7 is based on data acquisition control platform (controlling of sampling plate) core of programmable system on chip, also is whole acquisition system core.

The various interface circuit as shown in Figure 8 on the SOPC chip among Fig. 7.Wherein, U1A is SOPC chip 1MB SRAM program external with it and data-carrier store interface; U1B, U1C and U1F are SOPC chip and the sampled data memory interface that is positioned on the sampling plate, and U1F also provides some expansion I/O mouths in addition; U1E is SOPC chip clock extraneous with it and configuration circuit interface; U1D is the power interface circuit of SOPC chip.These interfaces of all mistakes of SOPC chip and external circuit are set up and are connected on electric.

Clock generating circuit among Fig. 7, serial Flash configuration data memory and interface thereof, and directly dispose the SOPC interface circuit as shown in Figure 9.Wherein, what clock generating circuit adopted is 50MHz clock oscillator (seeing the Y2 among Fig. 9), this oscillator output directly is connected with the clock pin of SOPC chip through RP3 current limliting electricity group back, through obtaining the 100MHz clock signal after phaselocked loop (PLL) the circuit frequency multiplication of SOPC chip internal, as the dominant frequency of the NIOS-II flush bonding processor on the SOPC chip and other IP kernel and circuit.The serial Flash configuration data memory adopt the special use of SOPC chip based on Flash configuring chip EPCS4 (capacity is 512KB) cheaply, its major function is to be used to preserve the configuration data of SOPC chip and to start boot.EPCS4 is supported in systems programming, new configuration data can be under Altera Quartus II integrated development system be supported, USB Blaster, EthernetBlaster or the ByteBlaster II download cable by altera corp and be arranged in configuration interface on the controlling of sampling plate (seeing the J28 of Fig. 9) and download to the EPCS4 chip.In addition, also can be configured the SOPC chip by the direct configuration interface among Fig. 9 (seeing the J24 among Fig. 9).In layoutprocedure, can understand configuring condition by configuration control indication (seeing the LED1 among Fig. 9).

1MB SRAM program among Fig. 7 and data-carrier store are as shown in figure 10, it forms (seeing U7 and U8 among Figure 10) by two 256K * 16 high-speed cmos sram chip IDT71V416S, and its major function is the program of 32 embedded NIOS-II flush bonding processors of storage SOPC chip and the data in the controlling of sampling process.

Dual port bus on-off circuit among Fig. 7 as shown in figure 11, it forms (seeing U9, U10, U11, U12, U13, U14 and U15 among Figure 11) by 7 10 dual port bus switching device PI5C3384, and its major function is the level conversion that realizes between 3.3V and the 5V.

Sampled data memory interface among Fig. 7, power interface and other expansion I/O interface are as shown in figure 12.J1 among Figure 12, J3 and J3B are the interfaces of controlling of sampling plate and sampling plate, its major function be the machinery of realizing controlling of sampling plate and sampling plate with electric on be connected.J4 is other I/O interface, and its major function provides the I/O interface of expansion.

Three, the motherboard of host computer system

Host computer system structured flowchart of the present utility model as shown in figure 18, it is by forming based on embedded system platform, man-machine interface (keyboard special and TFT-LCD module) and the machine-machine interface (based on machine-machine communication switching box of USB HUB) of 32 flush bonding processors of PowerPC architecture (MPC823e), major function is to realize seismologic record data presentation and processing, and man-machine interaction and seismologic record data transmission and unloading, be the main body key component of instrument.

32 flush bonding processor circuit of the MPC823e of the PowerPC architecture among Figure 18 as shown in figure 19.Wherein, U0 is 32 flush bonding processors of MPC823e, be aly to be integrated with, to have advanced person's the low-power-consumption embedded processor of RISC architecture 32 8-digit microcontrollers, lcd controller, I2C controller, ethernet controller, SPI controller and the UART controller of DSP function based on 32 flush bonding processors of PowerPC architecture nuclear, it not only can satisfy, and shallow seismic exploration instrument earthquake record data show and the processing needs, and can satisfy the shallow seismic exploration appliance requires and carry out the requirement that digital filtering is handled fast.Because the integrated required peripheral interface circuit of shallow seismic exploration instrument on single processor chips, it is minimum that number of chips is dropped to, and makes the circuit structure of host computer system reach optimum, thereby reach the power consumption that reduces host computer system.

Real time clock circuit among Figure 18, battery detection circuit and I/O port expansion circuit are as shown in figure 20.Wherein, real time clock circuit by 32.768KHz oscillator (seeing the CY1 among Figure 20), I2C bus interface real time clock device PCF8563 (seeing the U9 among Figure 20), have that the non-volatile controller DS1314 of battery monitor 3V (seeing the U10 among Figure 20) and button cell (JDIANCH1 among Figure 20 connects button cell) form, its major function is to provide real-time clock and backup battery monitoring thereof for instrument.The I2C signal wire of U9 directly is connected with the I2C control unit interface lead-in wire of MPC823e processor (seeing the U0 among Figure 19), and the battery voltage monitoring output signal of U10 is connected with an interrupt line of MPC823e processor (seeing the U0 among Figure 19).The battery detection circuit is made up of 8 the A/D converter TLC0831 (seeing the U0831 among Figure 20) that have serial line interface, its function is the lithium battery voltage in the monitoring instrument power-supply system, and be converted into digital value, the I2C bus by serial line interface and I/O expanded circuit (seeing the U/I/O among Figure 20) is connected with MPC823e processor (seeing the U0 among Figure 19).The I/O expanded circuit is made up of long-range 8 the I/O extended device PCF8574 of I2C bus (seeing the U/I/O among Figure 20), and its major function is to provide expansion I/O mouth line for battery detection circuit, backlight control circuit, ethernet transmitting-receiving driving circuit and power switch circuit control.

Bus driving circuits among Figure 18 as shown in figure 21, it has direction pin 8 bus transceiver 74LCX245 by 8 and forms (seeing U1, U2, U3, U4, U5, U6, U7 and U8 among Figure 21), and its major function is the driving force that increases address bus, data bus and the control bus of MPC823e processor (seeing the U0 among Figure 19).Wherein, U1, U2 and U3 form the address bus driver of MPC823e (seeing the U0 among Figure 19), U5, U6, U7 and U8 form the data bus driver of MPC823e (seeing the U0 among Figure 19), and U4 forms the read-write bus driver of MPC823e (seeing the U0 among Figure 19) control bus.The data transfer direction control of data bus driver is to be controlled by the reading signal lines DGPLA1 that U4 exports.

32MB among Figure 18～128MB SDRAM storage system circuit as shown in figure 22, it mainly forms (seeing U12, U13, U14 and U15 among Figure 22) by 4 MT48LC series SDRAM storage chips, major function is as the host computer system internal memory.If that U12, U13, U14 and U15 adopt is MT48LC32M16A2TG, then the total volume of SDRAM storage system is 256MB; If that U12, U13, U14 and U15 adopt is MT48LC16M16A2TG, then the total volume of SDRAM storage system is 128MB; If that U12, U13, U14 and U15 adopt is MT48LC8M16A2TG, then the total volume of SDRAM storage system is 64MB; If that U12, U13, U14 and U15 adopt is MT48LC4M16A2TG, then the total volume of SDRAM storage system is 32MB.The type selecting of these chips realizes (seeing RN1 and RN2 among Figure 22) by two toggle switchs.The work clock of SDRAM chip is by the clock signal CLKOUT of MPC823e (seeing the U0 among Figure 19), and provide by zero propagation buffering CY2305 (seeing the U11 among Figure 22).Data bus, address bus and the control bus that it should be noted that the SDRM storer is and MPC823e processor (seeing the U0 among Figure 19) direct interface, is not from bus driving circuits shown in Figure 21.

16MB among Figure 18～64MB Flash accumulator system circuit as shown in figure 23, it is to occur with independent F lash storage card form in instrument, so that change when instrument maintenance and system upgrade.The Flash storage card is made up of 4 28FxxxJ3 family chips (seeing U1, U2, U3 and U4 among Figure 23) and a dual-in-line plug (seeing the JFlash among Figure 23), and major function is the software systems and the seismologic record data of preserving main frame.If that U1, U2, U3 and U4 adopt is 28F128J3A, then the capacity of Flash storage card is 64MB; If that U1, U2, U3 and U4 adopt is 28F640J3A, then the capacity of Flash storage card is 32MB; If that U1, U2, U3 and U4 adopt is 28F320J3A, then the capacity of Flash storage card is 16MB.JFlash connector among Figure 23 is the bridge that Flash storage card and motherboard are realized electric and mechanical connection.

LCD display interface among Figure 18 and keyboard special interface circuit as shown in figure 24, its major function is that color graphics liquid crystal display and the keyboard special for instrument provides interface.Because MPC823e flush bonding processor chip (seeing the U0 among Figure 19) is built-in with lcd controller, so the LCD interface circuit fairly simple (seeing JLCD and RNLCD among Figure 24) on motherboard.The LCD display that the utility model adopts is 800 * 600 resolution Via Color TFT-LCD module LQ104S1DG21, the JLCD interface that is provided among Figure 24 can be directly therewith the TFT-LCD module directly connect.But, because LQ104S1DG21 has 18 display data signal lines of three primary colours (R, G and B), and the built-in lcd controller of MPC823e has only 12 display data signal lines of three primary colours (R, G and B), therefore in Figure 24, set up the RNLCD interface socket, so that the three primary colours of LQ104S1DG21 are had more 6 video data line ground connection or connect power supply, adopt direct grounding way usually.Keyboard interface circuit among Figure 24 adopts two long-range 8 I/O extended device PCF8574 of I2C bus (seeing U36 and U37 among Figure 24).RPZ2 among Figure 24 and RPZ2A draw exclusion on the keyboard interface, the push button signalling level equalization when it can guarantee keyboard scan.JKEY socket among Figure 24 is connected with the keyboard interface on being positioned at instrument panel, and its maximum can connect 64 digital character keys and function key, but the utility model only uses 32 keys in instrument reality.Button interrupt signal interface circuit adopts is a JK flip-flop (seeing the UJA among Figure 20) among the 74HC73, and its output directly links to each other with middle fracture line of MPC823e flush bonding processor (seeing the U0 among Figure 19).

Ethernet interface circuit among Figure 18, usb circuit and machine-machine communication interface as shown in figure 25, its major function is to provide interface for the Ethernet of instrument and usb communication.Because MPC823e chip (seeing the U0 among Figure 19) provides the ethernet communication controller of 10Mbps, therefore only need external ethernet communication transceiver just can constitute the ethernet communication circuit.Ethernet communication transceiver among Figure 25 adopts general 10base-T transceiver LXT905 (seeing the U24 among Figure 25), and its clock signal provides (seeing the OSC2 among Figure 25) by the 20MHz clock oscillator.Because MPC823e chip (seeing the U0 among Figure 19) provides the USB controller of 1.1 versions, therefore only need the circumscribed USB communication transceiver just can constitute the usb communication circuit.Usb communication transceiver among Figure 25 adopts universal serial bus transceiver PDIUSBP11A (seeing the U25 among Figure 25).The 20 core sockets (seeing the JWAISHE among Figure 25) that machine-machine communication interface adopts, it can directly be connected with the converting interface on being positioned at instrument panel, the converting interface on the instrument panel and the standard fitting of instrument---and the machine-machine communication switching box with USB HUB is connected.

Debugging among Figure 18 and test interface circuit and serial monitor-interface circuit as shown in figure 26, its major function be for host computer system provide the debugging and test interface.Because MPC823e chip (seeing the U0 among Figure 19) provides UART controller, therefore only need external RS232 serial transceiver just can constitute motherboard serial monitor-interface circuit.Serial interface circuit among Figure 26 is made up of RS232 transceiver, transient voltage suppressor and RS232 socket.Wherein, the RS232 transceiver adopts to have ± the RS232 transceiver MAX3225ECAP (seeing the U23 among Figure 26) of 15kV esd protection; transient voltage suppressor adopts SMAJ13CA (seeing TV1, TV2, TV3 and TV4 among Figure 26); what the RS232 socket adopted is the trapezoidal socket of 9 cores, can be directly and BDI2000 hardware debugger and PC interface.Because MPC823e chip (seeing the U0 among Figure 19) provides the jtag controller that is used for chip and circuit board testing, so the debugging of host computer system is relative with test interface circuit simple.PDEBUG socket among Figure 26 is a debugging interface, and it can directly be connected with the BDI2000 hardware debugger.PTAP socket among Figure 26 is a test interface, can with the circuit board testing device direct interface.

Power circuit among Figure 18, reset circuit and clock circuit are as shown in figure 27.The host computer system power circuit is made up of host computer system debugging power circuit, PLL power circuit and power switch circuit.Wherein, host computer system debugging power circuit is made up of linear voltage adjuster and supply socket, and its major function is that input 5V supply voltage is become the 3.3V device use of 3.3 supply voltages for host computer system.The linear voltage adjuster adopts 3A linear voltage adjuster CS5203A (seeing the RG0 among Figure 27), and columned supply socket (seeing the P5V among Figure 27) is adopted in supply socket.It should be noted that host computer system debugging power circuit just uses when motherboard exploitation debugging, remove this circuit in the formal product and change power-supply system power supply by instrument.Because the stability of the PLL circuit supply voltage in the MPC823e chip (seeing the U0 among Figure 19) directly has influence on the stability of host computer system dominant frequency, therefore added lc circuit (seeing the circuit that L1, C6, C6A, CT13 and CF36 among Figure 27 form) and guaranteed that supply voltage is stable in the PLL of MPC823e circuit power energization pins.Power switch circuit is made up of Sheffer stroke gate SN74HC04 (seeing the U17 among Figure 27) and single channel power distribution switching device MIC2025 (seeing the U16 among Figure 27), it mainly is for peripheral interface device on the motherboard provides the feed circuit that can turn off, and the control signal of power switch power supply is from I/O port expansion circuit (seeing the U/O/I among Figure 20).Because MPC823e processor (seeing the U0 among Figure 19) has three kinds of dissimilar reset pins, promptly therefore electrification reset, hardware reset and software reset have designed electrification reset and software and hardware reset circuit in Figure 27.Wherein, electrify restoration circuit is made up of the reset device DS1815 that draws output on having (seeing the U20 among Figure 27), and it provides power-on reset signal for the MPC823e processor; The software and hardware reset circuit is made up of the dual reset device DS1834 (seeing the U22 among Figure 27) with push button function, it provides the hardware and software reset signal for the MPC823e processor, and the control signal of software and hardware reset circuit is to be provided by keyboard interface (seeing the JKEY among Figure 24) by the reset button on the instrument panel.The clock circuit of host computer system is made up of master clock circuit, auxilliary clock circuit and USB clock circuit.Wherein, master clock circuit is made up of 8MHz clock oscillator (seeing the OSC1 among Figure 27), and it provides master clock signal for the MPC823e processor, and the PLL frequency multiplier circuit of process processor inside has obtained 64MHz dominant frequency clock signal.Auxilliary clock circuit is made up of 32.768KHz crystal oscillator (seeing the CY2 among Figure 27) and several capacitance resistance wares, and it provides clock during for MPC823e processor low-power consumption mode.The USB clock circuit is made up of 48MHz clock oscillator (seeing the OSC USB among Figure 27), and its USB controller for MPC823e processor inside provides clock signal.

Host computer system among Figure 18 and Flash card and acquisition system interface are as shown in figure 28.JCYB1 among Figure 28, JCYB2 and JREST are the interface cards of motherboard and sampling plate, and its major function is to realize the electric and mechanical connection of motherboard and sampling plate.JFlash among Figure 28 is the interface card of motherboard and Flash card, and its major function is to realize the electric and mechanical connection of Flash card and motherboard.

Four, the machine of host computer system-machine communication switching plate

The machine based on USB HUB among Figure 18-machine communication switching box is a standard fitting of the present utility model, machine-machine communication interface circuit plate that interconnecting device is built-in, itself and motherboard, TFT-LCD module and the PVC panel instrument that has a keyboard special have constituted the complete host computer system with communication function.Machine-machine communication interface circuit as shown in figure 29, it is made up of USB HUB, power circuit and several sockets, its major function is to provide interface for instrument and PC, USB flash disk and USB keyboard.USB HUB among Figure 29 adopts USB 2.0 low-power consumption HUB controller GL850A (seeing the U1 among Figure 29), and this HUB device can provide four USB interface, and the utility model has used two USB interface.JDB interface among Figure 29 provides from the Ethernet of instrument host plate and usb communication signal, what the JLAN interface adopted is standard ethernet network RJ45 interface socket, the USB2 interface adopts the standard USB interface socket with double-H groove weld SB interface, and the JPower interface adopts columned supply socket.Power circuit is made up of 3A linear voltage adjuster CS5203A (seeing the RG0 among Figure 29) and some LC devices, its major function is with power supply input the becoming 3.3V power supply output of 5V, provides 5V power supply for USB HUB chip provides 3.3V power supply and external USB flash disk and the USB keyboard of machine-machine communication switching box.It should be noted that, the power supply of machine-machine communication switching box is to exchange the power supply adaptor of importing the output of 5V direct current by external～220V to provide, rather than provided by the power-supply system of instrument internal, so machine-machine communication switching box only allows can not be used for the scene in indoor use.

Five, the built-in power-supply system of instrument

The built-in power-supply system of the utility model instrument is formed (as shown in figure 30) by lithium battery group, intrinsic safety type power system circuit and charging inlet, its major function be sampling plate, controlling of sampling plate and the motherboard for instrument provide+5V ,-5V and+the 3.3V stable power, and provide 1.2～3.2V adjustable LED-backlit power supply for the TFT-LCD module.The built-in power-supply system block diagram of instrument as shown in figure 30, its circuit diagram is as shown in figure 31.

Battery circuit shown in Figure 31 is made up of 7.4V/10Ah lithium battery group, current limliting electricity group and charging circuit, and its major function is to provide colliery intrinsic safety type power supply for instrument.Wherein, 7.4V/10Ah lithium battery group is concatenated into by 2 3.7V/10Ah lithium cells; Current-limiting resistance adopts heat radiator 1.5 Ω/50W wire wound resistor (seeing the RP1 among Figure 30) is installed, and this resistor back side scribbles the powerful thermal grease of non-silicone grease, is directly installed in the battery case; Charging circuit is that the power diode IN5822 by 2 3A composes in parallel, and charge power supply is directly from standard of instruments accessory special charger.The entire cell circuit is installed in the battery case, and semi-fluid drops down the burnt HT901 potting of the monocomponent room-temperature cured organosilicon of type, so that protection, sealing and reinforce battery circuit.

The distributed power source (as shown in figure 30) that the built-in power system circuit of instrument is made up of LED dimmable backlights power circuit, power panel and the sampling plate interface of battery interface, power on-off control circuit, sampling plate+5V power circuit, sampling plate-5V power circuit, sampling plate+3.3V power circuit, motherboard and controlling of sampling plate+3.3V power circuit, motherboard and controlling of sampling plate+5V power circuit, LCD display, its major function are that sampling plate, controlling of sampling plate, motherboard and the TFT-LCD module for instrument provides needed stabilized power source.Whole distributed power supply system is designed to an independently power panel, and power panel is fixed on the battery case.The 4 core supply sockets (seeing the JB among Figure 31) of sampling of battery interface among Figure 30, its major function are to realize being electrically connected of battery circuit and power panel.Power control switch circuit among Figure 30 is formed (seeing Figure 31) by mini power relay, triode, diode and some Resistor-Capacitor Units, and its major function is to open and close battery circuit and be connected with power-supply system, realizes the start and the shutdown of instrument.The Push And Release control signal of power control switch circuit is from the "on" and "off" button in the power control key district of instrument panel.The employed power switch relay of power switch circuit among Figure 31 is mini power relay G6C1114P-UL (seeing the JQ1-5.0V among Figure 31).Sampling plate among Figure 30+5V power circuit is formed (seeing the U1 among Figure 31) by DC-DC transducer MAX710, it mainly is to isolate stable+5V mimic channel power supply for six tunnels analogy input circuits of acquisition system and A/D change-over circuit provide, so that guarantee the data acquisition precision of acquisition system.Sampling plate among Figure 30-5V power circuit is formed (seeing the U4 among Figure 31) by DC-DC transducer MAX764, it mainly is to isolate stable-5V mimic channel power supply for six tunnels analogy input circuits of acquisition system and A/D change-over circuit provide, so that guarantee the data acquisition precision of acquisition system.Sampling plate among Figure 30+3.3V power circuit changes response LDO voltage adjuster LT1963AEQ-3.3 fast by the 1.5A low noise and forms (seeing the U3 among Figure 31), and its major function is to provide stable+3.3V power supply for the A/D change-over circuit of sampling plate and start triggering circuit.Motherboard among Figure 30 and controlling of sampling plate+3.3V power circuit also change response LDO voltage adjuster LT1963AEQ-3.3 fast by the 1.5A low noise and form (seeing the U5 among Figure 31), and its major function is to provide stable+3.3V power supply for the sampling memory of motherboard, controlling of sampling plate and sampling plate and read-write control circuit thereof.Motherboard among Figure 30 and controlling of sampling plate+5V power circuit are formed (seeing the U2 among Figure 31) by DC-DC transducer MAX710, and its major function is isolated stable+5V power supply for motherboard and controlling of sampling plate provide.LCD display 1.2～3.2V adjustable LED backlight electric power circuit among Figure 30 is changed response LDO voltage adjuster LT1963AEQ-3.3 (seeing the U8 among Figure 31) fast, is had that 32 grades of digital regulation resistance X9511 of button control (seeing the U9 among Figure 31) and backlight electric power control circuit (seeing the T3 among Figure 31) form by the 1.5A low noise, its major function is that the LED-backlit circuit for the TFT-LCD module provides 1.2～3.2V regulated power supply, so that the brightness of control LCD display.Signal is preserved in the LED-backlit brilliance control of backlight electric power circuit and brightness, direct "+", "-" and " storage " key from the brilliance control keypad on the instrument panel, and the switch controlling signal of backlight electric power is from the I/O port expansion circuit (seeing the U/I/O among Figure 20) of motherboard.The power-supply system among Figure 30 and the interface of acquisition system adopt 40 pin dual-in-line sockets (seeing the JD among Figure 31), and it realizes being electrically connected of power panel and sampling plate by flat cable.

Intrinsic safety type battery circuit recited above and distributed stabilized power source circuit system have been formed colliery of the present utility model intrinsic safety type power-supply system, and whole power-supply system is installed in the battery case of sealing, so that guarantee the safety and reliability of power-supply system.

Claims (3)

1. high resolving power mine shaft geology detection instrument, comprise display device, parameter setting device, power-supply system, it is characterized in that: this instrument also includes based on six passage high speed, high resolution shallow earthquake data acquisition system (DAS)s of programmable system on chip SOPC data acquisition control platform with based on the host computer system of 32 embedded processing systems platforms of PowerPC architecture; Described based on programmable system on chip SOPC data acquisition control platform by programmable system on chip SOPC chip, clock generator circuit, serial Flash configuration data memory and interface thereof, directly configuration interface, configuration control indicating circuit, 1MB SRAM program data memory, power circuit and interface, dual port bus on-off circuit, sampled data memory interface and other expansion interface are formed; Programmable system on chip SOPC chip is embedded with 32 soft nuclears of flush bonding processor of general NIOS-II, specialized high-speed data acquisition control IP kernel and sampled data memory read/write control IP kernel; Described based on 32 embedded processing systems platforms of PowerPC architecture by 32 flush bonding processors based on the PowerPC architecture, bus driving circuits, the SDRAM storage system, the Flash storage system, the LCD display interface, the keyboard special interface circuit, ethernet interface circuit, usb circuit, machine-machine communication interface, power circuit, reset circuit, clock circuit, real time clock circuit, battery detection circuit, the I/O port expansion circuit, debugging and test interface circuit, serial monitor-interface circuit and sampling plate interface are formed; 32 flush bonding processors based on the PowerPC architecture adopt the MPC823e processor, bus driving circuits is made up of 88 bus transceivers with direction pin, the 32MB that the SDRAM storage system is made up of 4 SDRAM chips～128MB capacity is storage system at random, the 16MB that the Flash storage system is made up of 4 Flash memory chips～64MB capacity flash memory system, 64 keyed jointing mouth circuit that the keyboard special interface circuit is made up of 2 long-range 8 I/O extended chips of I2C bus, ethernet interface circuit is made up of general 10base-T Ethernet transceiver, usb circuit is made up of the USB universal serial bus transceiver, power circuit is by host computer system debugging power circuit, PLL power circuit and power switch circuit are formed, reset circuit is by the chip and have electrification reset and the software and hardware reset circuit that the dual reset chip of push button function is formed of resetting that draws output on having, clock circuit is by the 8MHz master clock circuit, 32.768kHz auxilliary clock circuit and 48MHzUSB clock circuit are formed, real time clock circuit is by I2C bus interface real-time timepiece chip, have that the controller chip of battery detection and button cell form, battery detection circuit is made up of 8 A/D converters of serial line interface, what the I/O expanded circuit adopted is long-range 8 the I/O extended chips of I2C bus, and serial monitor-interface circuit is made up of RS232 serial transceiving chip and transient voltage suppressor.

2. high resolving power mine shaft geology detection instrument according to claim 1 is characterized in that: described display device is the display based on LED-backlit 800x600 resolution Via Color TFT-LCD module; Described parameter setting device is the special PVC panel based on 38 keys of four keypads; Described power-supply system is the intrinsic safety type power-supply system based on the lithium battery group; Describedly become the controlling of sampling plate based on programmable system on chip SOPC data acquisition control platform independent design, six passage high speed, high resolution shallow earthquake data acquisition system (DAS) independent design become sampling plate, become motherboard based on 32 embedded processing systems platforms of PowerPC architecture independent design.

3. high resolving power mine shaft geology detection instrument according to claim 1 and 2 is characterized in that: independently form by analog input channel, trigger control circuit, controlling of sampling plate interface, sampled data storer and read-write control logic circuit, motherboard interface and power interface by 6 for described six passage high speed, high resolution shallow earthquake data acquisition system (DAS)s; Each analog input channel contains simple component wave detector interface, capacitance-resistance buffer circuit, programmable amplifying circuit, amplification buffer circuit and 24 high-speed a/d change-over circuits, described program control gain amplifier shelves are designed to 0dB, 24dB, 36dB and 48dB, and the sampling interval of A/D change-over circuit is designed to the multiple of 16 microseconds; Trigger control circuit contains and trigger to start interface, preposition trigger pip buffer circuit, triggering mode and select circuit, activation threshold value circuit to be set, to trigger and start comparator circuit and rearmounted trigger pip buffer circuit, realizes internal trigger, external trigger, has no progeny and shortly trigger and lack earlier the four kinds of optional triggering modes of triggering that afterwards break earlier; Sampled data storer and read-write control logic circuit thereof contain 2 256kBx16 high-speed cmos SRAM, 8 and have eight bus transceivers of direction pin, 1 bus buffer, 1 four logical AND gate chip and pull-up resistor, and the capacity of sampled data storer is 1MB.

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