CN201054239Y - Display control circuit and display system using this circuit - Google Patents
Display control circuit and display system using this circuit Download PDFInfo
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- CN201054239Y CN201054239Y CNU2007201497568U CN200720149756U CN201054239Y CN 201054239 Y CN201054239 Y CN 201054239Y CN U2007201497568 U CNU2007201497568 U CN U2007201497568U CN 200720149756 U CN200720149756 U CN 200720149756U CN 201054239 Y CN201054239 Y CN 201054239Y
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Abstract
The utility model relates to a display controlling circuit used for generating and outputting a pulse signal and a display system including a display controlling circuit. The display controlling circuit comprises a data receiving module used for receiving a clock signal and a display signal; a memory module used for intercepting and buffer-memorizing part of the display signal from the data receiving module; and a processing module used for receiving the clock signal and part of the display signal on the memory module, dividing the display cycle of the display signal into a plurality of sub cycles, determining the pulse width of the pulse signal in each sub cycle according to the partial display signal, and outputting the pulse signal. In addition, the utility model also discloses a display system including a display controlling circuit.
Description
[technical field]
The utility model relates to a kind of pulse signal production method, the control circuit of generation and output pulse signal, and the system that uses this control circuit, relate in particular to the luminous pulse signal production method of control light-emitting component, be used to the display system that generates and export the display control circuit of this pulse signal and comprise this display control circuit.
[background technology]
Along with being extensive use of of LED, adopting LED emission three primary colors to be made in a large number, and be used for message panel or billboard in sports ground, side of buildings, the railway station with the LED display device that forms image according to pixel.
The LED display device comprises driving circuit and some pixels of being made up of different glow color LED.Driving circuit receives shows signal and control signal, carry out according to the brightness that is applied to the shows signal on this pixel by LED in the control pixel luminous, thereby make the people who watches this display screen can discern shown image.
At present, nearly all LED screen all is to adopt width modulation to control brightness degree.Realize brilliance control with pulse duration modulation method, periodically-varied light impulse length (being dutycycle) just, as long as this cycle that repeats to light is enough short, human eye is that imperceptible light emitting pixel is in shake.
But, use in the luminous process of pulse-width modulation method control LED in reality, can appear at the situation of brightness irregularities in the display cycle.For example, usually, the display frequency of LED display is 300 hertz, be to be about 3 milliseconds the display cycle, if in this display cycle, the waveform of pulse signal in continuous several cycles of output all is PWMa waveform as shown in Figure 1, as it being taken with video camera, the aperture time of supposing this video camera is 1 millisecond, promptly this pulse waveform is sampled, and the sampling period is 1 millisecond, approximately sample three times in the display cycle at this LED, then the signal that might adopt is low level entirely or is high level entirely, and like this, uneven phenomenon will appear in the LED display brightness that photographs.If the display cycle is long, also can produce the flicker that human eye can be distinguished.
Therefore, provide a kind of technical scheme that overcomes above defective to become the technical task that present urgent need solves.
[summary of the invention]
The purpose of this utility model is to provide a kind of uniform pulse signal generating method of controlling light-emitting component.May further comprise the steps: step 1, display cycle T is divided into N subcycle (N is the integer more than or equal to 1), determine the Cycle Length of this each subcycle; Step 2, (A is for more than or equal to 0 according to the recurrent pulse width A of each this period T correspondence that receives, and the integer smaller or equal to T) determine the pulse width of output pulse signal in this each subcycle, make the pulse width of the interior pulse signal of exporting of this each subcycle equate or approximately equal; Step 3 is exported this pulse signal.
Compared with prior art, the production method of this uniform pulse signal of the present utility model, by the whole display cycle is divided into the experimental process cycle, and the pulse width of definite each pulse signal of in each subcycle, exporting, make the pulse width of pulse signal of the interior output of each subcycle T ' equate or approximately equal, thereby obtain a uniform pulse signal.
Another purpose of the present utility model is to provide a kind of and produces and the display control circuit of output uniform pulse signal, by generating uniform pulse signal, makes that the signal that obtains of at every turn sampling all is more or less the same when sampling with the sampled signal pulse signals.This control circuit comprises: data reception module, receive clock signal and shows signal; Memory module, this shows signal of intercepting and buffer memory part from this data reception module; Processing module, receive the part shows signal in this clock signal and this memory module, the display cycle of this shows signal is divided into the plurality of sub cycle, determines the pulse width of pulse signal in each subcycle, and export this pulse signal according to this part shows signal.
Compared with prior art, display control circuit of the present utility model is divided into the experimental process cycle to the cycle of shows signal, determines the pulse width of pulse signal in each subcycle according to shows signal, guarantees that the pulse signal of output is uniform.
A purpose more of the present utility model is to provide a kind of display system of using this display control circuit.This display system comprises driving circuit and the display unit that is connected with this driving circuit respectively; This display unit comprises the light-emitting component of at least a glow color; This display system also comprises control circuit, the pulse signal of this light-emitting component of the corresponding every kind of glow color of this control circuit output, and this pulse signal sent to this driving circuit that is attached thereto, luminous in order to drive this light-emitting component, this control circuit comprises: data reception module, receive clock signal and shows signal; Memory module, this shows signal of intercepting and buffer memory part from this data reception module; Processing module, receive the part shows signal in this clock signal and this memory module, to be divided into the plurality of sub cycle display cycle according to this part shows signal, get the Cycle Length of fixed each subcycle, and determine the pulse width of pulse signal in each subcycle, and export this pulse signal according to this part shows signal.
Compared with prior art, this uniform pulse signal control light-emitting component of display system utilization of the present utility model is luminous, can make this light-emitting component uniformly light-emitting in a display cycle.
[description of drawings]
Fig. 1 is the pulse waveform of not handling through homogenising.
Fig. 2 is the schematic block diagram that comprises the utility model embodiment display system.
Fig. 3 is the structural representation of control circuit among the utility model embodiment.
Fig. 4 is the concrete structure synoptic diagram of control circuit among the utility model embodiment.
Fig. 5 is this concrete structure figure that controls periodic Control unit and pulse processing unit in the circuit among the utility model embodiment.
Fig. 6 is the workflow diagram of control circuit.
[embodiment]
Below in conjunction with accompanying drawing the utility model is elaborated.
Pulse signal production method, display control circuit among the utility model embodiment and the display system that comprises this display control circuit.The luminosity that is mainly used in the control light-emitting component averages in time, but is not limited thereto.
As shown in Figure 2, a kind of display system 10 among the utility model embodiment comprises: control circuit 30, driving circuit 20 and the display unit 40 that is connected with this driving circuit.Wherein, this control circuit 30 receive clock signals 50 and shows signal 60 are to generate the luminous pulse signal of control different colours light-emitting component.
In the present embodiment, this display unit 20 comprises the light emitting diode (hereinafter to be referred as LED) of three kinds of glow colors of red, green, blue, and these three kinds of glow color LED constitute a pixel.Certainly, this display unit 20 can comprise the light-emitting component except that LED, as other controlled light-emitting components etc.Three kinds of glow color LED of this red, green, blue also can not constitute a pixel, and controlled luminous separately, so that different needs to be provided.
In the present embodiment, this shows signal 60 meets DMX512 (DMX512/1990 Digital DataTransmission Standard for Control Dimmers and Controllers) agreement.Video data DR, the DG, the DB that comprise corresponding three kinds of glow color light emitting diodes in this shows signal 60.The structure of this video data DR, DG, DB is identical.Certainly, this shows signal 60 also can be set according to other agreement.If also comprise the light emitting diode of other glow colors except that red, green, blue in the display unit, then in shows signal 60, also to comprise planting the video data of glow color LED.
As shown in Figure 4, this control circuit 30 comprises data reception module 31, memory module 32a, 32b, 32c and processing module 33.This control circuit 30 also comprises clock signal input pin CLK, shows signal input pin Data and output pin 01,02,03.
This data reception module 31 receives this clock signal 50 and shows signal 60, and video data DR, DG, the DB of corresponding different glow color LED in the shows signal 60 is cached to respectively among memory module 32a, 32b, the 32c.Processing module 33 reads the video data of corresponding different glow color light emitting diodes respectively from memory module 32a, 32b, 32c, after treatment, output drives the pulse signal of this difference glow color light emitting diode.Below this processing module 33 is elaborated.
As shown in Figure 5, this drive control module 33 comprises periodic Control unit 331, pulse data processing unit 332a, 332b, 332c and pulse generation unit 333a, 333b, 333c.Wherein, pulse data processing unit 332a, 332b, 332c structure are identical with principle of work, below only introduce pulse data processing unit 332a; The structure of pulse generation unit 333a, 333b, 333c is also identical with principle of work, below pulse generation unit 333a only is described.
This periodic Control unit 331 receives these clock signals 50 and Cycle Length T, subcycle number N, recurrent pulse width A, determines the length of subcycle in this display cycle, the output cycle control signal.This pulse data processing unit 332a receives this cycle control signal and read wherein video data from memory module 32a, after handling, and the output pulse control signal.This pulse generation unit 333a receives this pulse control signal, and generates the corresponding pulse signal 334a that drives red light emitting diodes according to this pulse control signal, is sent to driving circuit by output pin 01, and is luminous in order to drive red LED.
The concrete structure figure of this periodic Control unit 331 and pulse data processing unit 332a as shown in Figure 5.This periodic Control unit 331 comprises following a few part.First counter 3311, the periodic signal S5 of receive clock signal 50, subcycle number N and 3321 outputs of first comparer determines the number of subcycle, output count signal S1.First divider 3312, receiving cycle length T and subcycle number N calculate T/N, export its quotient M to first adder 3314, export its remainder values n to first selector 3313.First selector 3313 receives this remainder values n and count signal S1, and signal S2 is selected in output; First adder 3314, receive clock signal 50, this quotient M and should select signal S2 are determined the pulse width of each subcycle.By this first selector 3313 and first adder 3314, can obtain in whole period T, the pulse width that n subcycle arranged is M+1, the pulse width of all the other N-n subcycle is M, output cycle control signal S3.
This pulse processing unit 332a comprises following components.Second counter 3321, receive clock signal 50 is counted each subcycle length, output count signal S4.First comparer 3322, receive described cycle control signal S3 and count signal S4, this cycle control signal S3 and count signal S4 are compared, when its value equates, export a duration and the pulse that the value of this cycle control signal S3 equates, the number of exporting this pulse equates with count value S1; When it is unequal, do not export pulse, output periodic signal S5 is formed in the pulse of these comparer 3322 outputs, simultaneously this periodic signal S5 is fed back to first counter 3311.Second divider 3323, receiving cycle pulse width A and described subcycle number N calculate A/N, export its quotient B to second adder 3325, export its remainder values n ' to second selector 3324.Second selector 3324 receives this remainder values n ' and described count signal S1, and signal S6 is selected in output; Second adder 3325, receive clock signal 50, this quotient B and select signal S6 are determined the pulse width of each subcycle.By this second selector 3324 and second adder 3325, can obtain in whole period T, the pulse width that the individual subcycle of n ' is arranged is B+1, the pulse width of the individual subcycle of all the other N-n ' is B, output cycle control signal S7.Second comparer 3326, count pick up signal S4 and cycle control signal S7 compare this cycle control signal S7 and count signal S4, when its value equates, export a duration and the pulse that the value of this cycle control signal S7 equates, the number of exporting this pulse equates with count value S1; When it is unequal, do not export pulse, pulse control signal S8 is formed in the pulse of these comparer 3326 outputs.This pulse control signal S8 is outputed in the middle of the pulse signal generating unit 333a, this pulse signal generating unit 333a is according to periodic signal S5 and this pulse control signal S8 production burst signal 334a, export driving circuit 20 to from output pin 01, be used for controlling the brightness of this red LED.
In the present embodiment, the particular flow sheet of this processing module work as shown in Figure 6.May further comprise the steps:
Step 701, beginning;
Step 702, read cycle length T, the subcycle number N that needs division and the pulse width A in whole cycle, A is the integer smaller or equal to T;
Step 703 is calculated T/N, judges whether it is integer;
Step 704, when T/N is an integer, promptly T can be divided exactly by N, and the Cycle Length of each subcycle is T/N;
Step 705 judges whether A/N is integer;
Step 706, when A/N was integer, promptly A can be divided exactly by N, and then the pulse width of each subcycle is A/N;
Step 707, when A/N was not integer, promptly A can not be divided exactly by N, calculated its merchant and was B, and remainder is n ';
Step 708, in the whole cycle, the pulse width that the individual subcycle of n ' is arranged is B+1, the pulse width of the individual subcycle of all the other N-n ' is B;
Step 709, when T/N is not an integer, promptly T can not be divided exactly by N, calculates its merchant and is M, and remainder is n;
Step 710, in the whole cycle, the Cycle Length that n subcycle arranged is M+1, the Cycle Length of all the other N-n subcycle is M;
Step 711 judges whether A/N is integer;
Step 712, when A/N was integer, promptly A can be divided exactly by N, and then the pulse width of each subcycle is A/N;
Step 713, when A/N was not integer, promptly A can not be divided exactly by N, calculated its merchant and was B, and remainder is n ';
Step 714 judges that whether B+1 is greater than M;
Step 715, as B+1 during greater than M, its Cycle Length of subcycle that pulse width is set is B+1 is M+1, and remaining subcycle pulse width is B;
Step 716, as B+1 during less than M, in the then whole cycle, the pulse width that the individual subcycle of n ' is arranged is B+1, the pulse width of the individual subcycle of all the other N-n ' is B.
Below be elaborated for example.The aperture time of supposing video camera is 1 millisecond, and promptly the sampling period is 1 millisecond, approximately samples 3 ~ 4 times in the whole display cycle.Basic identical for the waveform that guarantees to sample at every turn, the whole display cycle is divided into the experimental process cycle, the pulse width of each subcycle equates or approximately equal, and the number that guarantees subcycle in each sampling period is more than 4 or 4.In the present embodiment, be provided with the display cycle is divided into 16 subcycles, i.e. N=16.
It is 4080 * 10 that this display cycle is set
-6Second, i.e. T=4095; The pulse width of this display cycle is 1536 * 10
-6Second, i.e. A=1536, A is the integer smaller or equal to T.At first, whether the length T of judging the display cycle can be divided exactly by N.4080/16=255, then the Cycle Length of each subcycle is 255.Then, determine the pulse width of each subcycle.Whether the pulse width A that judges the whole display cycle can be divided exactly by N.When A=1536, A/N=96, promptly the pulse width of each subcycle is 96.When A can not be divided exactly by N, for example, when A=1533,1533/16 merchant B was 95, and remainder n ' is 13, and then in the whole display cycle, the Cycle Length that 13 subcycles are arranged is B+1=96, and the Cycle Length of all the other 3 subcycles is 95.
When the length T of display cycle can not be divided exactly by N, for example, this display cycle was 4095 * 10
-6Second, i.e. T=4095,4095/16 merchant M is 255, remainder n is 15.In 16 subcycles dividing, the Cycle Length that 15 subcycles are arranged is M+1=256, and the Cycle Length of 1 remaining subcycle is 255.When the pulse width A of whole display cycle can be divided exactly by N, the pulse width of each subcycle was A/N.When A can not be divided exactly by N, the merchant of A/N is B, and remainder is n '.If B+1≤M, then as long as in the whole cycle pulse width of the individual subcycle of n ' being arranged is B+1, the pulse width of the individual subcycle of all the other N-n ' is that B gets final product.If B+1＞M, its pulse width of subcycle that then needs to be provided with Cycle Length and be M+1 is B+1.For instance, during A=4094,4094/16 merchant is 255, and remainder is 14, and the pulse width that 14 subcycles are then arranged is 256, and the pulse width of all the other two subcycles is 255.The T=4095 of manifest cycle length, the Cycle Length that 15 subcycles are arranged is M+1=256, the Cycle Length of 1 remaining subcycle is 255.Therefore, Cycle Length need be set be its pulse width of subcycle of 256 is 256, the error situation of the pulse width of subcycle greater than this subcycle length can not occur.
Adopting the technical solution of the utility model, is that 1 millisecond sampled signal is sampled to the pulse signal of control circuit output with the cycle, and the signal that each sampling obtains is basic identical, and like this, the LED display brightness that photographs is even.
Although by above embodiment the utility model is disclosed, the utility model is not limited to the driven for emitting lights diode.For example, it also can be applied to the control circuit of organic EL.In addition, generally speaking, the utility model also can use in other electronic equipments that adopt the time average pulse signal.
Claims (9)
1. display control circuit that is used to generate with output pulse signal comprises:
Data reception module, receive clock signal and shows signal;
Memory module, this shows signal of intercepting and buffer memory part from this data reception module;
Processing module, receive the part shows signal in this clock signal and this memory module, the display cycle of this shows signal is divided into the plurality of sub cycle, determines the pulse width of pulse signal in each subcycle, and export this pulse signal according to this part shows signal.
2. display control circuit as claimed in claim 1 is characterized in that, this processing module comprises:
The periodic Control unit receives described clock signal, and this display cycle is divided into the experimental process cycle, and determines the Cycle Length of each subcycle, the output cycle control signal;
At least one pulse data processing unit receives the shows signal in this cycle control signal and the corresponding described memory module, determines the pulse width in this each subcycle, the production burst control signal;
At least one pulse generation unit receives this clock signal and this pulse control signal, exports described pulse signal.
3. display control circuit as claimed in claim 2 is characterized in that, described periodic Control unit comprises:
First counter receives the periodic signal S5 that described clock signal, subcycle number N and first comparer feed back, and determines the number of subcycle, output count signal S1;
First divider, receiving cycle length T and this subcycle number N calculate T/N, export its quotient M to first adder, export its remainder values n to first selector;
First selector receives this remainder values n and count signal S1, and signal S2 is selected in output;
First adder receives this clock signal, this quotient M and this selection signal S2, determines the Cycle Length of each subcycle, output cycle control signal S3;
By this first selector and first adder, can obtain in the whole display cycle, the pulse width that n subcycle arranged is M+1, the pulse width of all the other N-n subcycle is M.
4. display control circuit as claimed in claim 2 is characterized in that, described pulse data processing unit comprises:
Second counter receives described clock signal, described each subcycle length is counted output count signal S4;
First comparer, this cycle control signal S3 and this count signal S4 that receive are compared, when its value equates, export the pulse that a duration equates with the value of this cycle control signal S3, the number of exporting this pulse equates with the value of described count signal S1, when it is unequal, does not export pulse, periodic signal S5 is formed in the pulse of this first comparer output, simultaneously this periodic signal S5 is fed back to described first counter;
Second divider, receiving cycle pulse width A and described subcycle number N calculate A/N, export its quotient B to second adder, export its remainder values n ' to second selector;
Second selector receives this remainder values n ' and described count signal S1, and signal S6 is selected in output;
Second adder receives this clock signal, this quotient B and this selection signal S5, determines the pulse width of each subcycle, output cycle control signal S7;
By this second selector and second adder, can obtain in the whole display cycle, the pulse width that the individual subcycle of n ' is arranged is B+1, the pulse width of the individual subcycle of all the other N-n ' is B;
Second comparer, this cycle control signal S7 and this count signal S4 that receive are compared, when its value equates, export the pulse that a duration equates with the value of this cycle control signal S7, the number of exporting this pulse equates with the value of described count signal S1, when it is unequal, do not export pulse, pulse control signal is formed in the pulse of this second comparer output.
5. display system, this display system comprises driving circuit and the display unit that is connected with this driving circuit respectively;
This display unit comprises the light-emitting component of at least a glow color;
It is characterized in that, this display system also comprises control circuit, and this control circuit is exported the pulse signal of this light-emitting component of corresponding every kind of glow color, and this pulse signal is sent to this driving circuit that is attached thereto, luminous in order to drive this light-emitting component, this control circuit comprises:
Data reception module, receive clock signal and shows signal;
Memory module, this shows signal of intercepting and buffer memory part from this data reception module;
Processing module, receive the part shows signal in this clock signal and this memory module, to be divided into the plurality of sub cycle display cycle according to this part shows signal, get the Cycle Length of fixed each subcycle, and determine the pulse width of pulse signal in each subcycle, and export this pulse signal according to this part shows signal.
6. display system as claimed in claim 5 is characterized in that, described light-emitting component is a light emitting diode.
7. as claim 5 or 6 described display systems, it is characterized in that this processing module comprises:
The periodic Control unit receives described clock signal, and this display cycle is divided into the experimental process cycle, and determines the Cycle Length of each subcycle, the output cycle control signal;
At least one pulse data processing unit receives the shows signal in this cycle control signal and the corresponding described memory module, determines the pulse width in this each subcycle, the production burst control signal;
At least one pulse generation unit receives this clock signal and this pulse control signal, exports described pulse signal.
8. display system as claimed in claim 7 is characterized in that, described periodic Control unit comprises:
First counter receives the periodic signal S5 that described clock signal, subcycle number N and first comparer feed back, and determines the number of subcycle, output count signal S1;
First divider receives the Cycle Length T and the subcycle number N that store, calculates T/N, exports its quotient M to first adder, exports its remainder values n to first selector;
First selector receives this remainder values n and count signal S1, and signal S2 is selected in output;
First adder receives this clock signal, this quotient M and this selection signal S2, determines the Cycle Length of each subcycle, output cycle control signal S3;
By this first selector and first adder, can obtain in the whole display cycle, the pulse width that n subcycle arranged is M+1, the pulse width of all the other N-n subcycle is M.
9. display system as claimed in claim 7 is characterized in that, described pulse data processing unit comprises:
Second counter receives described clock signal, described each subcycle length is counted output count signal S4;
First comparer, this cycle control signal S3 and this count signal S4 that receive are compared, when its value equates, export the pulse that a duration equates with the value of this cycle control signal S3, the number of exporting this pulse equates with the value of described count signal S1, when it is unequal, does not export pulse, periodic signal S5 is formed in the pulse of this first comparer output, simultaneously this periodic signal S5 is fed back to described first counter;
Second divider, receiving cycle pulse width A and described subcycle number N calculate A/N, export its quotient B to second adder, export its remainder values n ' to second selector;
Second selector receives this remainder values n ' and described count signal S1, and signal S6 is selected in output;
Second adder receives this clock signal, this quotient B and this selection signal S5, determines the pulse width of each subcycle, output cycle control signal S7;
By this second selector and second adder, can obtain in the whole display cycle, the pulse width that the individual subcycle of n ' is arranged is B+1, the pulse width of the individual subcycle of all the other N-n ' is B;
Second comparer, this cycle control signal S7 and this count signal S4 that receive are compared, when its value equates, export the pulse that a duration equates with the value of this cycle control signal S7, the number of exporting this pulse equates with the value of described count signal S1, when it is unequal, do not export pulse, pulse control signal is formed in the pulse of this second comparer output.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201497568U CN201054239Y (en) | 2007-06-21 | 2007-06-21 | Display control circuit and display system using this circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2007201497568U CN201054239Y (en) | 2007-06-21 | 2007-06-21 | Display control circuit and display system using this circuit |
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| CN201054239Y true CN201054239Y (en) | 2008-04-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436794A (en) * | 2011-12-27 | 2012-05-02 | 深圳市明微电子股份有限公司 | Method and system for realizing clock control by use of pulse modulation |
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2007
- 2007-06-21 CN CNU2007201497568U patent/CN201054239Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102436794A (en) * | 2011-12-27 | 2012-05-02 | 深圳市明微电子股份有限公司 | Method and system for realizing clock control by use of pulse modulation |
| CN102436794B (en) * | 2011-12-27 | 2014-08-06 | 深圳市明微电子股份有限公司 | Method and system for realizing clock control by use of pulse modulation |
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Assignee: Shenzhen Zhongqingwei Technology Development Co., Ltd. Assignor: Beijing Jushu Digital Technology Development Co., Ltd. Contract fulfillment period: 2009.3.10 to 2015.3.10 Contract record no.: 2009990000266 Denomination of utility model: Display control circuit and display system using this circuit Granted publication date: 20080430 License type: Exclusive license Record date: 20090402 |
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