CN201025670Y

CN201025670Y - Dual and/or protection outlet error tolerance mechanism

Info

Publication number: CN201025670Y
Application number: CNU2006201650328U
Authority: CN
Inventors: 陆于平; 李莉
Original assignee: Guodian Nanjing Automation Co Ltd
Current assignee: Guodian Nanjing Automation Co Ltd
Priority date: 2006-12-11
Filing date: 2006-12-11
Publication date: 2008-02-20
Anticipated expiration: 2016-12-11

Abstract

The utility model relates to a double and maybe protection outlet fault-tolerant mechanism which comprises a dual CPU system, an outlet relay and four middle relays. The outlet signal and the fault signal of the system (CPUA, CPUB) respectively control the four middle relays and an side often opening contact point of the four middle relays are connected in a cross and parallel way. The part which is connected in a parallel way is connected with the negative pole of the input end of the outlet relay in series. The positive pole of the input end of the outlet relay is connected with a power supply and the other end of the control circuit is connected with grounding. The utility model can process the 'and gate' control by connecting the outlet signals of the dual CPU system in series, which can ensure to avoid the error movement of the system. At the same time the fault signal of the CPU system closes and lock the the outlet signals of the CPU system, which can process the 'or gate' control, which can ensure to avoid the refusing movement of the system. Therefore the utility model gives attention to redundancy and fault-tolerant designing principle, which in deed lives up to an organic unity of the anti error movement and refusing movement of the protection device.

Description

Two with or protection outlet fault tolerant mechanism

Technical field

The utility model relates to technical field of industrial automatic control, particularly relates to a kind of two and or protection outlet fault tolerant mechanism.

Background technology

Along with the integrated level of protective relaying device in the electric power system is more and more higher; the defencive function that single protective device is born is more and more; that have even all main protections and backup protection a unit all concentrate on the protective device; this just makes that protected object had the possibility that loses some or all of protection when any one link of the interior hardware system of device went wrong.

The single cpu system of the use that existing protective device has, when any link of this system broke down, whole device all can't move on request, caused malfunction or tripping easily; Though the device that has uses dual-CPU system; but the total starting relay of outlet of one of them cpu system control protective device; another cpu system is used for control protection tripping operation outlet; this still is a kind of thinking of simple serial design; when these two any one links of cpu system break down, still can cause the protective device tripping.

More than device all can not well solve the fault-tolerance and the reliability requirement of relaying protection.

Summary of the invention

The purpose of this utility model is the problem that exists at above prior art; a kind of protective device malfunction problem that both can solve is proposed; can increase the technology of device fault-tolerant ability again, thereby satisfy in the practical application the reliability of protective device and the requirement on the fault-tolerance.

In order to address the above problem, the utility model is realized by taking following technical scheme:

In order to strengthen fault-tolerance, in the utility model two with or protection outlet fault tolerant mechanism designed dual-CPU system identical and separate on the loop, all sampling is independent separately exports for two cpu systems.When two cpu systems all operate as normal the time, guarantee to have only two CPU to judge that simultaneously the protection action just can make exit relay effective, is the AND gate outlet, as shown in Figure 1; When one of them cpu system fault, guarantee that it withdraws from the outlet logic combination automatically, control exit relay separately by another normal cpu system, be the OR-gate outlet, as shown in Figure 2.So just take into account redundant and fault-tolerant design principle, really accomplished the organic unity of anti-tripping of protective device and faulty action preventing.

In the utility model two with or protection outlet fault tolerant mechanism comprise: system CPU A, system CPU B, the first auxiliary relay K1, the second auxiliary relay K2, the 3rd auxiliary relay K3, the 4th auxiliary relay K4 and exit relay K.The first auxiliary relay K1 is by the outlet signal ESGA control of CPUA, the second auxiliary relay K2 is by the outlet signal ESGB control of CPUB, the 3rd auxiliary relay K3 is by the fault-signal DERA control of CPUA, and the 4th auxiliary relay K4 is by the fault-signal DERB control of CPUB.First pair of the described first auxiliary relay K1 is often opened first pair of the node and the second auxiliary relay K2 and is often opened the node parallel connection, second pair of the described first auxiliary relay K1 is often opened first pair of node and the 3rd auxiliary relay K3 and is often opened the node parallel connection, second pair of the described second auxiliary relay K2 is often opened first pair of node and the 4th auxiliary relay K4 and is often opened the node parallel connection, part series connection with above-mentioned parallel connection, with one end ground connection GND, the other end links to each other with the negative pole of exit relay K input, and the positive pole of exit relay K input meets power vd D.As shown in Figure 3.

Aforementioned two with or protection outlet fault tolerant mechanism, it is characterized in that: normally closed node (K4-2) parallel connection of the normally closed node (K3-2) of described the 3rd auxiliary relay (K3) and the 4th auxiliary relay (K4), and being connected in the control loop of exit relay (K).

Aforementioned two with or protection outlet fault tolerant mechanism; it is characterized in that: each diode (D) in parallel of the input of described first auxiliary relay (K1), second auxiliary relay (K2), the 3rd auxiliary relay (K3), the 4th auxiliary relay (K4) and exit relay (K); the positive pole of diode (D) is succeeded the negative pole of electrical equipment input, and the negative pole of diode (D) is succeeded the positive pole of electrical equipment input.

Useful purpose of the present utility model is: when CPUA and CPUB all just often, the 3rd auxiliary relay K3 and the 4th auxiliary relay K4 are all invalid, exit relay K is subjected to " with door " control of the first auxiliary relay K1 and the second auxiliary relay K2, only under both all effective situations, exit relay K can be effective, improved the faulty action preventing performance of device; When one of them CPU (for example CPUA) fault, DERA is effective, and the 3rd auxiliary relay K3 is effective, and first auxiliary relay is bypassed, and the 4th auxiliary relay K4 is invalid, and exit relay K only receives the control of the second auxiliary relay K2, and vice versa.Exit relay K is subjected to the disjunction gate control of the first auxiliary relay K1 and the second auxiliary relay K2 in this case, as long as the auxiliary relay of normal CPU is effective, exit relay K just can be effective, has improved the fault-tolerance of device, thereby has satisfied requirement.

Description of drawings

Below in conjunction with accompanying drawing the utility model is further described:

Fig. 1 and Fig. 2 are conceptual schematic view of the present utility model;

Fig. 3 is the circuit theory diagrams of the utility model embodiment one;

Fig. 4 is the circuit theory diagrams of the utility model embodiment two;

Fig. 5 is the circuit theory diagrams of the utility model embodiment three.

Embodiment

Embodiment one

Present embodiment two with or protection outlet fault tolerant mechanism as shown in Figure 2, form by the first auxiliary relay K1, the second auxiliary relay K2, the 3rd auxiliary relay K3, the 4th auxiliary relay K4 and exit relay K etc.The first auxiliary relay K1 is by the outlet signal ESGA control of CPUA, the second auxiliary relay K2 is by the outlet signal ESGB control of CPUB, the 3rd auxiliary relay K3 is by the fault-signal DERA control of CPUA, the 4th auxiliary relay K4 is by the outlet signal DERB control of CPUB, first pair of the described first auxiliary relay K1 is often opened first pair of the node and the second auxiliary relay K2 and is often opened the node parallel connection, second pair of the described first auxiliary relay K1 is often opened first pair of node and the 3rd auxiliary relay K3 and is often opened the node parallel connection, second pair of the described second auxiliary relay K2 is often opened first pair of node and the 4th auxiliary relay K4 and is often opened the node parallel connection, part series connection with above-mentioned parallel connection, with one end ground connection GND, the other end links to each other with the negative pole of exit relay K coil, and the positive pole of exit relay K coil meets power vd D.According to the operating state of CPUA, CPUB, have three kinds of situations, make a concrete analysis of as follows:

1, CPUA, CPUB are all working properly: this moment, DERA and DERB were invalid, and the 3rd auxiliary relay K3 and the 4th auxiliary relay K4 are all invalid, and exit relay K is subjected to " with door " control of the first auxiliary relay K1 and the second auxiliary relay K2.Only under K1 and all effective situation of K2, exit relay K can be effective;

2, CPUA is working properly, the CPUB fault: this moment, DERA was invalid, DERB is effective, the first chromaffin body point K4-1 closure of the 4th auxiliary relay K4, bypass the node of the second auxiliary relay K2, exit relay K only is subjected to the control of the first auxiliary relay K1, and successful separates CPUB from control loop;

3, CPUA fault, CPUB is working properly.This moment, DERB was invalid, and DERA is effective, the first chromaffin body point K3-1 closure of the 3rd auxiliary relay K 3, bypass the node of the first auxiliary relay K1, exit relay K only is subjected to the control of the second auxiliary relay K2, successful separates CPUA from control loop;

By last surface analysis as can be seen, under first kind of situation, exit relay K has prevented the malfunction that single cpu fault causes by CPUA and CPUB " with door " control, has improved the faulty action preventing performance of system; Under second and third kind situation, fault CPU separates from control loop, has avoided having improved the fault-tolerance of system because the tripping of the protective device that fault CPU tripping causes is controlled disjunction gate control;

Embodiment two

Exemplified above the two of signal circuit with or protection outlet fault tolerant mechanism; under the occasion stricter to export requirement; can use the more strict technical scheme of control; as shown in Figure 4; with the normally closed node K4-2 parallel connection of normally closed node K3-2 and the 4th auxiliary relay K4 of described the 3rd auxiliary relay K3, and be connected in the control loop of exit relay K.

Like this, when CPUA and CPUB all break down, DERA and DERB are all effective, the normally closed node of the normally closed node of the 3rd auxiliary relay K3 and the 4th auxiliary relay K4 is all opened, control loop forever disconnects, exit relay K has been stopped because the malfunction that cpu fault may cause by locking.

Embodiment three

Present embodiment is at the above embodiment enterprising step refining in basis and improves the technical scheme that forms, show as Fig. 5, it specifically improves part and is each the diode D in parallel of input at the first auxiliary relay K1, the second auxiliary relay K2, the 3rd auxiliary relay K 3, the 4th auxiliary relay K4 and exit relay K, the positive pole of diode D is succeeded the negative pole of electrical equipment input, the negative pole of diode D is succeeded the positive pole of electrical equipment input, to avoid unexpected reverse voltage destruction work circuit.

In addition to the implementation, the utility model can also have other execution modes.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection range of the utility model requirement.

Claims

1. two with or protection outlet fault tolerant mechanism, comprised system, system, the first auxiliary relay K1, the second auxiliary relay K2, the 3rd auxiliary relay K3, the 4th auxiliary relay K4 and exit relay K, it is characterized in that the outlet signal ESGA control of the first above-mentioned auxiliary relay K1 by above-mentioned CPUA, the second above-mentioned auxiliary relay K2 is by the outlet signal ESGB control of above-mentioned CPUB, the 3rd above-mentioned auxiliary relay K3 is by the fault-signal DERA control of above-mentioned CPUA, and the 4th above-mentioned auxiliary relay K4 is by the fault-signal DERB control of above-mentioned CPUB; First pair of the first above-mentioned auxiliary relay K1 is often opened first pair of the node and the above-mentioned second auxiliary relay K2 and is often opened the node parallel connection, second pair of the first above-mentioned auxiliary relay K1 is often opened first pair of node and above-mentioned the 3rd auxiliary relay K3 and is often opened the node parallel connection, second pair of the second above-mentioned auxiliary relay K2 is often opened first pair of node and above-mentioned the 4th auxiliary relay K4 and is often opened the node parallel connection, part series connection with above-mentioned parallel connection, with one end ground connection GND, the other end links to each other with the negative pole of exit relay K input, and the positive pole of exit relay K input meets power vd D.

According to claim 1 described two with or protection outlet fault tolerant mechanism, it is characterized in that: the normally closed node K3-2 of described the 3rd auxiliary relay K3 and the normally closed node K4-2 parallel connection of the 4th auxiliary relay K4, and be connected in the control loop of exit relay K.

According to claim 1 or 2 described two with or protection outlet fault tolerant mechanism; it is characterized in that: each diode D in parallel of the input of the described first auxiliary relay K1, the second auxiliary relay K2, the 3rd auxiliary relay K3, the 4th auxiliary relay K4 and exit relay K; the positive pole of diode D is succeeded the negative pole of electrical equipment input, and the negative pole of diode D is succeeded the positive pole of electrical equipment input.