CN200997185Y - Electronic digital number plate of vehicle - Google Patents

Abstract

An automobile electronic numeral licence is provided, which comprises a power supply circuit (1), and is characterized in that: the utility model also comprises an LCD (2) positioned on the cab dashboard, a keying circuit (3), a UIM card interface circuit (4) including identity and qualification contents of each automobile, and a simulating sending voice circuit (5). The circuits are connected with a central microprocessor and a logic control circuit (6), and the central microprocessor and the logic control circuit (6) are respectively connected with a transmitting circuit (7), a receiving circuit (8), a PLL frequency synthesis circuit (9) and an irreversible instruction control circuit (10); the receiving circuit (8) is connected with a receive signal processing circuit, and the transmitting circuit (7) is connected with a transmitting signal processing circuit.

Description

The automotive electronics digit plate shines

Technical field

The utility model relates to a kind of automotive electronics digital photographing.

Background technology

Present license plate is optic type, promptly discerns by the car plate that is suspended on the vehicle front and rear part.This recognition method exists in a lot of problems, as: car plate was difficult for watching at night, be difficult for after the traffic accident tracing, pay the road toll vehicle for breaking rules and regulations, being late for and be difficult for control inspection, can not solve the cover board phenomenon of many shared licence plates of car, be robbed the unable especially solution of stolen problem, therefore for vehicle supervision department for vehicle, along with increasing of vehicle, existing license plate way to manage can not adapt to development form.

Summary of the invention

The purpose of this utility model is exactly in order to solve present vehicle license management function singleness, can not carry out problems such as synthesization, automatic management to vehicle, provide a kind of have can better be used for monitoring car nationality, car to, without a licence driving, break in traffic rules and regulations, hit-and-run, realize the automotive electronics digit plate photograph of the advantages such as round-the-clock monitoring, management, commander and service of operation automobile.

For achieving the above object, the utility model has adopted following technical scheme:

A kind of automotive electronics digit plate shines, it comprises power circuit, it comprises that also the UIM card interface circuit of LCD, the key circuit that is arranged on bridge instrumentation Pan Chu and the identity that comprises each automobile, qualification content, simulation send sound circuit, and these circuit are connected with central little processing and logic control circuit; Central little processing simultaneously and logic control circuit also are connected with radiating circuit, receiving circuit, phase-locked loop frequency combiner circuit, irreversible instruction control circuit respectively, receiving circuit then is connected with the received signal treatment circuit, and radiating circuit is connected with emissioning signal treatment circuit U812.

Described radiating circuit comprises UIM card data-signal memory circuit U713, UIM clock circuit U712, logical circuit U610, high frequency power amplification module U811 and power amplification control module U810, unidirectional loop device F811, Hi-pass filter F810, emitter follower Q810, diplexer F910, radio frequency adaptation U912, antenna CHIP-ANT, UIM card supply voltage is adjusted mu balanced circuit U765; Wherein, logical circuit U610 input end is connected with key circuit, also sending sound circuit through K switch H with simulation simultaneously is connected, output terminal then meets UIM card data-signal memory circuit U713 respectively, UIM clock circuit U712, UIM card supply voltage is adjusted mu balanced circuit U765, UIM card interface circuit CN711, output terminal also is connected with Hi-pass filter F810 through emissioning signal treatment circuit U812 simultaneously, Hi-pass filter F810 is connected with high frequency power amplification module U811, high frequency power amplification module U811 output terminal is through unidirectional loop device F811, diplexer F910, radio frequency adaptation U912 is connected with antenna CHIP-ANT, its output terminal also is connected with power amplification control module U810 simultaneously, power amplification control module U810 is connected with emitter follower Q810, and emitter follower Q810 is connected with logical circuit U610.

Described emissioning signal treatment circuit U812 adopts the RFT3100 chip, it is with the UIM digital signal of licence plate, the voice signal of the digital signal of keyboard circuit output and process simulation process converts the transmission baseband signal to and modulates and up-converter circuit, convert high frequency to and send the modulated wave signal, send into high frequency power amplification module U811 again and carry out high frequency power control.

Described receiving circuit comprises that high frequency electromagnetic wave signal receives network, radio frequency adaptation U912, diplexer F910, amplifier U910, low noise amplifier Q910, reactive power supply filtering circuit, gain control circuit Q912, mixting circuit U913, high freguency bandpass filter F911, receiving demodulation device U939, intermediate-frequency filter F912, triode Q911, logic control circuit U610, gain control element U911 forms; Wherein, receiving antenna is at first sent the high frequency electromagnetic wave signal that receives into the reception network, radio frequency adaptation U912 reinjects, by it signal is sent into diplexer F910 more then, high-frequency signal injection low noise amplifier Q910 amplifies then, its output signal is injected high freguency bandpass filter F911, the output terminal of high freguency bandpass filter F911 is connected with mixting circuit U913, the intermediate-freuqncy signal of mixting circuit U913 output is injected triode Q911 base stage, base stage also is connected with gain control element U911 simultaneously, triode Q911 collector signal exports intermediate-frequency filter F912 input end to, delivers to receiving demodulation device U939 by its output terminal; Simultaneously, low noise amplifier Q910 also is connected with gain control circuit Q912, gain control circuit Q912 is connected with logic control circuit U610, mixting circuit U913 input end is connected with radio frequency VCO buffer amplifier U814 in the phase-locked loop frequency combiner circuit, radio frequency VCO buffer amplifier U814 then is connected with PLL module U816 with radio frequency VCO circuit U 815, and PLL module U816 is connected with logic control circuit U610.

Described high frequency electromagnetic wave signal receives network by inductance L 1155, L1156 capacitor C 930, and C931 forms; Reactive is powered filtering circuit by capacitor C 911, L1159, and C916 forms; Diplexer F910 only allow centre frequency be 881MHZ up and down the signal in each 12.5MHZ scope pass through, it is the 836MHZ signal output of each 12.5MH scope up and down that its transmitting filter then can only allow centre frequency; Low noise amplifier Q910 is a field effect transistor, and it has the gain amplifier of 17db to the signal of 800MHZ frequency range; Mixting circuit U913 gets their difference frequency signal with high-frequency received signal and reception high-frequency local oscillation signal, becomes intermediate-freuqncy signal output, and its centre frequency is 85.38MHZ; Intermediate-frequency filter F912 then separates intermediate-freuqncy signal, becomes two signal outputs of 90 ° of phase phasic differences.

Described received signal treatment circuit is made up of receiving demodulation device U939, and its model is IFR3000-488CCF; It is connected with local oscillator, and oscillation frequency is 170.76MHZ.

Described phase-locked loop frequency combiner circuit comprises reference clock oscillator OSC810, PLL module U816, and radio frequency VCO circuit U 815, radio frequency VCO buffer amplifier U814, amplifier Q811, impact damper U936 forms; Wherein, the reference clock oscillator OSC810 both provided 19.68MHZ base reference signal to frequency synthesizer, provides logic clock signal to logic control circuit U610 again; Integrated two groups of phase detectors in the PLL module U816, frequency divider, it carries out mutually bit comparison by its inner integrated phase detector to two input signals with the 19.68MHZ reference clock oscillator signal of reference clock oscillator OSC810 input and the high frequency VCO oscillator signal of radio frequency VCO circuit U 815 outputs, export single-ended property control voltage, through resistance R 1092, R1094, capacitor C 869, the filter network that C866 constitutes injects radio frequency VCO circuit U 815 by link resistance R1091; Simultaneously, the phase detector that is provided with in the PLL module U816 combines in receiving demodulation device U939 chip with radio frequency VCO circuit U 815, constitute two groups of phase-locked loop frequency synthesizer systems, the intermediate-freuqncy signal of receiving demodulation device U939 output is through coupling capacitor C 953, resistance R 1183, inductance L 1066 is injected PLL module U816, the reference clock oscillator signal is also sent into the intermediate frequency phase detector, the intermediate frequency phase detector carries out the phase bit comparison to two input signals, the output direct-current control voltage, through resistance R 849, R1095, capacitor C 874, C875, the low-pass filter that C871 forms carries out obtaining a voltage after the smothing filtering and sends into receiving demodulation device U939, output intermediate frequency VCO local oscillation signal is sent into PLL module U816 as sampled signal, and radio frequency VCO circuit U 815 produces the radio frequency VCO local oscillation signal of centre frequency 967MHZ, this signal has two whereabouts, a process capacitor C 867, resistance R 1090 is sent into PLL module U816, obtains the direct current error controling signal after the processing, through resistance R 1092, R1094, R1091, capacitor C 869, C866 becomes direct-current control voltage and injects radio frequency VCO circuit U 815 behind the external dual-time constant of the C865 low-pass filter; Another Lu Zejing capacitor C 867, C856 sends into radio frequency VCO buffer amplifier U814, radio frequency VCO buffer amplifier U814 is provided with two local oscillation signal output terminals, the radio-frequency (RF) local oscillator signal of one of them output is through capacitor C 853, inductance L 1064 is injected impact damper U936, output signal is made the transmission local oscillation signal of up-conversion to up-converter circuit again, and another delivers to mixting circuit by radio frequency VCO buffer amplifier U814 output radio-frequency (RF) local oscillator signal, signal is made the reception local oscillation signal of frequency mixer and is used.

Little processing of described central authorities and logic control circuit comprise logical circuit U610, external storage U640, storer U620; Wherein, logical circuit U610 model is ARM7TDMI, external storage U640 is that model is AT24C2566-10U1, storer U620 is DS42533, its chip comprises two kinds of storeies, the i.e. SRAM static memory of 32 FLASH flash memorys and 4M byte, storer U620 and external storage U640 pass through I ²The C bus is carried out message exchange, clock circuit and reset circuit are arranged in the logical circuit U610, and send sound circuit MIC with simulation and be connected, this circuit is made up of two transmitters, one be in the machine transmitter another be other local transmitters in car of hiding, logical circuit U610 chip carries out digitized processing to voice analog signal, is combined into a place with the license plate digital signal then and forms the transmission baseband signal, and injection radio-frequency (RF) power amplification circuit becomes frequency electromagnetic waves and radiate from emitting antenna; Simultaneously, logical circuit U610 with the signal Processing that receives after by liquid crystal display displays, read at one's leisure for it.

Described power circuit (1) comprises power converting circuit U510, the output of automobile 12V accumulator is sent into power converting circuit U510 through the bridge power polarity identification decision circuitry that D511-D514 forms, become the 4.8V direct current after capacitor C 513, C514 filtering is sent into into isolating diode D515, the output termination five terminal voltage stabilizer U765 of isolating diode D515 or three-terminal voltage-stabilizing voltage stabilizer U918-U924 are the D.C. regulated power supply of circuitry 2.5V-3.0V; Irreversible instruction control circuit (10) comprises irreversible instruction control unit U511, its model is LH002A, it is connected with the base stage of triode Q511 with triode Q510, their collector then is connected with U923 with voltage stabilizer U924 respectively, the base stage of triode Q512 is connected with circuit output end mouth controller U916, collector is connected with relay J 1 coil winding and GND with R744 respectively, and emitter is connected with three-terminal voltage-stabilizing voltage stabilizer U924.

The driver that both is convenient to that the utility model is installed in the pilothouse above the panel board watches command information on the LCDs, is convenient to the driver again and keys in relevant numerical data before driving, also is convenient to the place that its transmitted radio signal is not stopped.

Emission electric signal of the present utility model is without manually-operated, and it will be launched the numerical information of representing this identity of automobile certificate content automatically as long as the driver opens automobile key.Mechanical transport command centre receives the recognition of qulifications of travelling of information input traffic administration command centre Computer Database that network (also claiming the cellular information network) will receive first by its signal base station, judging this car by authentication, identification does not hand over road toll just not set out on a journey the qualification of travelling, if determine the qualification of travelling of this car through assert, traffic control center will be given this car emission permission driving instruction of setting out on a journey by the signal base station.In fact the utility model has just designed special circuit monitoring and ignition switch on the automobile, and the circuit of this special Control of Automobile ignition switch is grasped by traffic control center, as long as traffic control center is examined out automobile and do not possessed the qualification of travelling, launch the grant instruction of travelling just can not for this car.Obviously, automobile can not get the setting out on a journey grant instruction of travelling is not just started automobile yet.

The beneficial effects of the utility model are: can be used for monitoring car nationality, car to, without a licence driving, break in traffic rules and regulations, hit-and-run, realize round-the-clock monitoring, management, commander and the service of operation automobile.

Description of drawings

Fig. 1 is an electrical diagram of the present utility model;

Fig. 2 is the electrical schematic diagram of radiating circuit;

Fig. 3 is the electrical schematic diagram of emissioning signal treatment circuit;

Fig. 4 is the electrical schematic diagram of receiving circuit;

Fig. 5 is the electrical schematic diagram of received signal treatment circuit;

Fig. 6 is the electrical schematic diagram of phase-locked loop frequency combiner circuit;

Fig. 7 is central little processing and logic control circuit electrical schematic diagram;

Fig. 8 is power supply and irreversible instruction control circuit.

Wherein, 1, power circuit, 2, LCD, 3, key circuit, 4, UIM card interface circuit, 5, simulation sends sound circuit, 6, central little processing and logic control circuit, 7, radiating circuit, 8, receiving circuit, 9, the phase-locked loop frequency combiner circuit, 10, irreversible instruction control circuit.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing and embodiment.

Among Fig. 1, circuit of the present utility model comprises radiating circuit 7, emissioning signal treatment circuit, receiving circuit 8, received signal treatment circuit, phase-locked loop frequency combiner circuit 9, little processing of central authorities and logic control circuit 6, formations such as power circuit 1 and irreversible instruction control circuit 10.The signal that the utility model is launched is each identity of automobile of representative of producing according to national mechanical transport administrative authority fixed point, the special UIM card of qualification content numerical information, this jig has authoritative weight and uniqueness, this is just as the telephone number of every family, the individual can not change and replace, and this has just effectively prevented the unlicensed of automobile, false-trademark, of inferior brand, or the situation of a licence plate of quantity shared motor takes place.To the utility model, though circuit is identical unification, because the UIM the core of the card sheet data difference of each automobile, the digital signal that causes each automobile to be launched also is inequality.The utility model is carried out a machine one card, separation between machine and card.Circuit has special UIM card, and traffic control command centre will instruct the professional to be responsible for installing the sealing debugging.The time that the utility model transmits is two seconds, be 20 seconds interval time that transmits, this quiescent interval of 20 seconds also is the time that the utility model receives the information base station, the utility model will be by the transport information instruction of receiving, read on the LCD 2 that is presented at oneself, for driver's reference.

Among Fig. 2, radiating circuit 7 comprises UIM card data-signal memory circuit U713, UIM clock circuit U712, logical circuit U610, high frequency power amplification module U811 and power amplification control module U810, unidirectional loop device F811, Hi-pass filter F810, emitter follower Q810, diplexer F910, radio frequency adaptation U912, antenna CHIP-ANT, UIM card supply voltage is adjusted mu balanced circuit U765 etc.

U713 is the data circuit of UIM card, and this circuit is subjected to the driving of supply voltage UIM-PWR and V-MSMP, and the D14 pin of U610 is connected with U713 the 5th pin, and supply voltage UIM-PWR the 5th pin voltage output end is connected with U713 the 4th pin through R1005.The input signal of U713 the 5th pin derives from the data-signal that UIM-MSM-TXXD sends here, and this signal is the D14 pin from U610, AUX-PCU-OUT, and the paraphase of two triodes is amplified in the U713 module, exports from the 6th pin.The UIM-TXD data-signal is added to CN711 the 6th pin, and another road and domestic R987 are connected in the E16 pin of U610.Supply voltage UIM-PWR is added to card interface circuit 4CN711 the 1st pin of UIM card.Be added to the 3rd pin of CN711 from the clock signal UIM-CLK of U712 the 4th pin output, send digital data by the UIM card data-signal UIM-TXD of U713 the 6th pin output and be added on CN711 the 6th pin.The reset signal UIM-RESET of the V1 pin GP107 output of U610 is connected to CN711 the 2nd port through link resistance R986, CN711 the 6th pin is the data information exchange port between U610 and the UIM in fact, the transmission data UIM-TXD of U610 can inject the storage of UIM card through this port, also the interface data UIM-RXD of UIM card can be injected the E16 pin of U610 through this port.R895 is the upper offset resistance of U713, and R988 is a below-center offset resistance.

U712 is the clock circuit of UIM card, and after the 1st pin of U712 added supply voltage UIM-PWR, the C12 pin of U610 output YAMN clock signal was delivered to U712 the 2nd pin, after U712 handles, takes out UIM card clock UIM-CLKO and sends into CN711 the 3rd pin.

U765 is that the supply voltage of UIM card is adjusted mu balanced circuit, when the U1 of U610 pin GPIO output UIM-PWR-EN-N signal, and when delivering to U765 the 3rd pin-EN, U765 starts working, by the 5th pin OUT output 2.5v voltage, input U713 the 4th pin, U712 the 1st pin, the power supply of CN711 the 7th pin.

Key circuit 3 of the present utility model is signal exchange instruments of driver and traffic control command centre, the driver can be according to the menu instructions of traffic control command centre on LCD before driving, key in various digital data, for the identification audit of traffic control command centre, U610 provides the key scan signal for the numeric keypad circuit, key-press matrix circuit SCAN[0:5], and KEYSESN[0:3], be respectively the rank scanning line of matrix circuit.These controlled sweep traces are connected to the E3 of U610, D2, and D1 and G1 pin, standard is KEYSENS[0:3], M3, K1, L3, A2, B3 and M14 pin are labeled as SCAN[0:5].When pressing some numerical keys, by sweep trace coded pulse is introduced in the logical circuit U610 chip, remove to control the units corresponding circuit through U601 decoding output command adapted thereto.

Simulation sends sound circuit 5, and to be the utility model be subjected to the warning circuit of requiring assistance under the criminal hijack situation for the automobilist.In case open silently when automobile by criminal hijack, only needs the driver to take advantage of the ruffian not note, have only Ben Che driver oneself to know the installation site.Require assistance after the alarm switch KH, it is required assistance to report to the police and has just realized.MIC is highly sensitive transmitter among the figure, and the utility model circuit is provided with two transmitters, and one is random installation, and another is to be installed in the place that other are hidden by driver oneself.The G17 of the U610 that its transmitter connects respectively, J16, K17, the relevant circuit of H14 pin, R908 provides the resistance of bias voltage for receiver MIC+ in the utility model car, this road analogue voice signal is sent into the G17 pin of U610 by the J16 pin of U610 through C660, MIC2P and enter audio amplifier circuit in the U610 chip.Alarm switch KH is switched in case the utility model is required assistance, this circuit enters alarm status, be also referred to as the irreversible command status of U511, its U511 will be following working in coordination with of U610, control circuit is in continuous transmit status, transfer speech simulated audio signal and the digital signal of ruffians in the car to continuous bus location signal that the police provides, so that the police implements to deploy to ensure effective monitoring and control of illegal activities rescue.

The utility model compresses above-mentioned digital signal voice analog signal through adc data, convolution and interweaving encoding, and processing such as QPSK coding obtain and send baseband signal TXI/Q, and are sent to intermediate-frequency circuit and TXI/Q modulation circuit and obtain modulated intermediate frequency and send signal.This signal is an intermediate frequency modulated carrier signal, and centre frequency is 130.38MHZ.And the local oscillation signal that is used for TXI/Q frequency modulation is produced by a special intermediate frequency VCO circuit that sends.The signal that this circuit produces is that 2 frequency-doubled signals of the modulated intermediate-freuqncy signal of transmission are the local oscillation signal of 260.76MHZ.It is delivered to the TXI/Q modulation circuit after 2 frequency divisions, amplifies sending modulated intermediate-freuqncy signal earlier, and then to sending up-converter circuit.In sending up-converter circuit, will send modulated intermediate-freuqncy signal and carry out mixing in the RXVCO local oscillation signal and obtain high frequency modulated carrier signal, and again high frequency modulated wave signal be carried out high frequency power and amplify and just launch afterwards.

High-frequency power amplifying circuit of the present utility model is to be made of U811 high frequency power amplification module and U810 power amplification control module.The connect with the mains input end of V-RTNG of U811 power amplifier module the 4th pin.U812 sends the high frequency modulated signal of up-converter circuit output, and RF-IN is through L1058, C831, and C838, R1080, R1067, the impedance that R1071 forms becomes the moding circuit networking and injects the C839 coupled circuit, and enters the 2nd pin IV of Hi-pass filter F810 through coupled circuit.Signal from the 5th pin OUT output, is added to C830 and delivers to power amplifier module U811 the 2nd pin RFIN input end after F810 filtering.C832 is the output waveform shaping capacitance, and C830 is the signal input capacitance.Signal from the 5th pin RFOUT output, injects emission filter F811 the 6th pin by coupling capacitance C834 after high frequency power amplification module U811 amplifies.F811 is actually a unidirectional loop device, input signal inside can only transmit forward and can not transmit backward, transmission can produce the above decay of 20db backward, L1057 is the output load inductance, through of the 1st pin OUT output of emission filter high-frequency signal from F811, directly inject the 3rd pin of diplexer F910, the input pin that promptly transmits, the 18th pin is the output pin that transmits.The 13rd pin is the output pin of received signal.Transmit and transmit by the F910 transmit band pass filter.Then by the reception bandpass filter received signal of F910, F910 also is the subassembly of 2 bandpass filter to received signal, is that it is effectively separated sending out with two channels of receipts of circuit, is independent of each other.Send the bandpass filter output terminal directly to be connected at diplexer F910 the 18th human hair combing waste with U912 radio frequency adaptation input end the 1st pin.Radiofrequency signal is exported from U912 the 2nd pin, through L1176, and L1173, C976, the emission matching network that C977 forms is sent into the CN911 antennal interface.CHIP-ANT radiate radio frequency electromagnetic by antenna.

Power control of the present utility model is because be mobile with the fast moving of automobile in real work.It then is fixed bearing the signal base station that receives launch mission, more signal base station and information transmission of the present utility model have increased interference to add the urban skyscraper, having general situation is, the transmission signal nearer apart from the base station is stronger, and apart from a little less than the transmission signal far away of base station, transmission attenuation.This signal that just causes the signal of remote emission closely to be launched is fallen into oblivion.For addressing this problem, the utility model is provided with power control circuit in circuit, and when the utility model transmitted, by the minimal power emission, reduced other input base station and co-channel interference of the present utility model earlier by this way the base station in the control base station.Although for the signal far and near distance difference of the oriented base station of institute, it is all similar to arrive reception signal of base station size.So the utility model is provided with transmission power control circuit in circuit.

U811 is a power control module, and the 3rd pin VREF is the power control voltage input terminal, as long as the voltage swing of this pin of control just can be controlled the emission output power of U811.U810 the 3rd pin+IN is the input end of control voltage, the control voltage of this pin is the A12 pin from logic control circuit U610, U610 controls voltage TX-AGC-ADJ with power and is added to the Q810 transistor base, export by emitter, through R1061, inject U810 control voltage and form module the 3rd pin+IN, export from the 1st pin OUT through the processing of U810 chip.Control voltage is injected into functional module U811 the 3rd pin VREF through R1054.C814, C813 is the filter capacitor of control voltage.Because U610 power control voltage has at first been regulated the conducting degree of Q810 emitter follower, changes thereby changed U810 the 3rd pin DC potential, reached the output power of regulating U811 and changed, finished the control of emission output power.The 3rd, 4 pin of U810 are the inverting input of two power control voltages, what the utility model was taked is single-ended input, by the VREF of output the 1st pin OUT to power amplifier module U811 output control voltage, import negative feedback voltage through resistance R 1064 to input end the 4th pin-IN simultaneously, can improve the job stability of U810.U810 the 5th pin SHUT is the power amplifier start-up control end, and this start-up control signal PA ON is from logical circuit U610.

Power supply V-RFTX provides quiescent biasing voltage can provide the basic controlling of starting working voltage through the resistor network of R1058, R1061 dividing potential drop to the U811 power amplifier module when U810 the 3rd pin provides initialization voltage in the U810 initialization to the input stage of U810.

Among Fig. 3, emissioning signal treatment circuit U812 adopts RFT3100 as the process chip that transmits.The composition that transmits is the UIM digital signal of licence plate, the digital signal of keyboard circuit output and convert to through the voice signal of simulation process and to send baseband signal TXI/Q and send into that U812 modulates and up-converter circuit, convert high frequency to and send the modulated wave signal, send into radio frequency power amplifier control module U811 again and carry out high frequency power control.Play crucial effects at this U812.The RFT3100 chip has 36 pins, and chip comprises TXI/Q modulation transtation mission circuit VCO, sends up-conversion, bus interface and mode control circuit etc.1st, 2 pin TX-Q/QN and the 3rd, 4 pin TXI/IN import the four tunnel parallel baseband signals that send, and enter two TXI/Q modulators arranged side by side and modulate TX-I/IN and TX-Q/QN respectively.Two modulators also need input to send the intermediate frequency local oscillator signal respectively, they are to obtain 0 ° of quadrature in phase and 90 ° of two intermediate frequency local oscillator signals by the transmission intermediate-freuqncy signal that sends the output of frequency P LL phase-locked loop system by 2 frequency divisions and phase-shift circuit, send into corresponding modulator respectively, two groups of modulator output phase quadrature send the intermediate frequency modulated wave and deliver to adder circuit, obtain unified transmission intermediate frequency modulated wave through addition, again the intermediate frequency modulated wave is amplified through the AGC intermediate frequency amplifier, the intermediate frequency modulated wave of amplitude stabilization is sent to the AGC amplifying circuit of up-converter circuit, its AGC control voltage is that it is from U610 by the 8th pin VCO NTROL input.In addition, processing circuitry of intermediate frequency is provided with if bandpas filter, at the 6th pin IF-BPF1, and the 7th pin IF-BPF2, the periphery is provided with the effect that the low reactance-resistance ratio resonant network plays the if bandpas filter device.

Sending local oscillation circuit in the U812 chip is a phase-locked loop frequency synthesizer, by the 30th pin TXVCO-T1, and the 31st pin TXVCO-T2, the 28th pin PD-OUT, the 27th pin PD-ISET, the 26th pin LOCK-DET, the inside and outside circuit of the 25th pin TCXO is formed.By the self-excitation IFVCO circuit that external circuit in the 30th, 31 pin constitutes the medium-frequency oscillator signal that produces is sent into modulation circuit through frequency division on the one hand, deliver to phase detector behind the frequency division on the other hand.The intermediate frequency phase detector also will be imported the benchmark oscillator signal by the input of the 25th pin.Allow phase detector that two input signals are carried out the phase bit comparison, obtain corresponding error controling signal, the low-pass filter output direct-current control voltage that the error control voltage of the 28th pin output is formed through this pin peripheral cell, similar AFC function, send on the voltage-controlled element of the 30th, 31 pin peripheries, can adjust the oscillation frequency of IFVCO circuit.The phase-locked loop locking signal of the 26th pin output is delivered to U610 as detection signal.In fact, U812 chip up-converter circuit need be imported two signals, one is to send the intermediate frequency modulated wave, another is to send high-frequency local oscillation signal RF-LD, send high-frequency local oscillation signal RF-LD and after amplifying, send into upconverter by the input of the 19th pin, by upconverter two input signals are carried out mixing, output high energy sends the modulated wave signal.If signal is that they of 900MHZ frequency range are through the 15th pin, the 14th pin, subordinate's circuit is delivered in CELLA/B-OUT output, if signal is the transmission modulated wave signal of 1900MHZ frequency range then delivers to high frequency power amplifier through the 13rd pin, the 12nd pin PCSA/B-OUT output high frequency modulated wave.Certainly, as for chip operation in any pattern entirely with the control of serial bus interface and mode control circuit.Its external leading foot the 24th pin SBCK, the 23rd pin SBDJ, the 22nd pin SBST, the 21st pin AB-SEL, the 17th pin PA-ON etc., their main and logic control circuit U610, the relevant leading foot connection of MSM3100, wherein, SBCK, SBDT, SBST are the clocks of control bus, data and reset signal; PA-ON is the emissive power control signal of external power amplifier, and AB-SEL is the selection signal of circuit output end, when this pin connects when obtaining power positive end through pull-up resistor, and can be by the 14th, 15 pin output signals.The 33rd pin DAC-IREF connects the reference current input end of the high-frequency amplifier circuit of DAC circuit in being.

Emission medium-frequency VCO is also finished by U812.Be integrated with intermediate frequency VCO circuit, phase detector, frequency divider, the phase-locked loop VCO system of sending in the U812 25-31 pin chip.The 30th pin TXVCO-T1, the 31st pin TXVCO-T2, peripheral cell L1062, C846, C851, C848 are tank elements, its varactor D811, D812 can be equivalent to the variable capacitance that is connected in parallel on resonant capacitance C848 two ends.Self-excited oscillator of the common composition of circuit and peripheral circuit element in it, the transmission intermediate frequency local oscillator signal of output 260.76MHZ is sent into the intermediate frequency phase detector through frequency division.By 16.89MHZ reference (benchmark) clock oscillation signal of crystal OSC810 output, also to inject U812 the 25th pin TCXO simultaneously through C837.By phase detector two input signals being carried out the phase bit comparison obtains error control voltage and exports from the 28th pin PO-OUT, through peripheral circuit dual-time constant low-pass filter smothing filtering, become dc error AFC control voltage, this wave filter is by R1075, R1076, R1086, C842, C843, compositions such as C847.The output direct-current control voltage is added to varactor D811, the negative pole of D812, two varactors are under the effect of negative polarity Dc bias, equivalence is that the electric capacity of certain numerical value is controlled under the effect of voltage at overlay error, change along with the variation of resonant capacitance, thereby realized the frequency adjustment of VCO circuit.Make the more stable 260.76MHZ oscillation signal frequency of the output that sends intermediate frequency VCO circuit more accurate.This phase-locked loop is controlled by logical circuit U610, and its control signal comprises the 22nd pin, SBST, and the 23rd pin SBDT, the 24th pin SBCK etc., they are reset signals of serial data bus, data-signal and clock signal.

The TXI/Q modulator is to send baseband signal by U610 output to deliver to the TXI/Q modulation circuit that the 1-4 pin of U812 enters chip, it is converted to the base band digital signal and sends the intermediate frequency modulated wave, two signals of TXI/Q modulation circuit input, the transtation mission circuit carrier signal that except that the TXI/Q baseband signal, also has the IFVCO circuit to send here.The transmission intermediate frequency modulated wave signal of modulation circuit output center frequency 130.38MHZ has contained the TXI/Q base-band information, and up-converter circuit is delivered in the processing behind its process adder circuit and the AGC intermediate-frequency circuit.On the processing circuitry of intermediate frequency through the 6th, 7 pin outward element C840, R1077, L1060, L1061, the if bandpas filter filtering that C844, C845 form, further this has been apt to the frequency characteristic of intermediate-freuqncy signal.

Sending up-conversion in fact also realizes in the U812 module, be provided with the transmission up-converter circuit in the U812 module, be the frequency mixer that moves on the carrier frequency in fact, the modulated intermediate-freuqncy signal of the transmission of 103.38MHZ is carried out mixing with transmission oscillation signals according TX-LO in chip, export their difference frequency signal, send the dominant frequency modulated wave from U812 the 15th pin LELLA-OUT output, inject high frequency power amplifier input capacitance C838's.The required local oscillation signal of its up-conversion is by the 19th pin RF-LO, 814 inputs of process capacitor C, its sends the mixing of up-converter circuit through participation after amplifying.

Among Fig. 4, receiving circuit 8 comprises that high frequency electromagnetic wave signal receives network, radio frequency adaptation U912, diplexer F910, amplifier U910, low noise amplifier Q910, reactive power supply filtering circuit, gain control circuit Q912, mixting circuit U913, high freguency bandpass filter F911, receiving demodulation device U939, intermediate-frequency filter F912, triode Q911, logic control circuit U610, gain control element U911 forms.

Receiving antenna is at first sent the high frequency electromagnetic wave signal of accepting into L1155, C930, C931, the reception network that L1156 forms injects the 2nd pin IN of U912, export the 18th pin ANT that signal is sent into again duplexer filter F910 by the 1st pin OUT, exported from the 13rd pin RX by the high-frequency received signal that F910 separates, F910 is a reception bandpass filter, it only allow centre frequency be 881MHZ up and down the signal in each 12.5MHZ scope pass through, and do not allow other signal to come in circuit is caused interference.It is the 836MHZ signal output of each 12.5MH scope up and down that the transmitting filter of F910 then can only allow centre frequency, and does not allow the noise signal in the radiating circuit to radiate the interference that causes other circuit.High-frequency signal is by C926, and L1163 injects Q910 the 2nd pin low noise amplifier.Q910 is field effect transistor has 17db to the signal of 800MHZ frequency range a gain amplifier.L1166, C926, L1163, L1174 etc. have constituted the LNA high-pass filtering circuit, and C923 is the signal output coupling capacitor.The working power V-SYNTH of Q910 is from U921 mu balanced circuit module, and C911, L1159, C916 etc. constitute reactive power supply filtering circuit.L1159 promptly is that the direct current supply inductance of Q910 is again the AC load of Q910 simultaneously.C931, C934 are that electric capacity is gone on the side of source circuit, and be very little to the high-frequency signal capacitive reactance, can equivalence be high frequency earthing, Q910 is connected into the common source amplifying circuit, input signal be gone into grid from the 2nd footnote, high-frequency signal after the amplification is by drain electrode output, by L1175, C923 injects F911 the 2nd pin, and Q910 adopts the self-bias mode, its bias voltage is by drain electrode, grid, R1163, generations such as R1164.R1163, R1164, R1165 can stablize the dc point of this amplifying circuit.C934, C931 can eliminate the negative feedback of source resistance to high-frequency signal.

On the source circuit of Q910, be provided with gain control based on Q912, Q912 is that triode adds control voltage PA-RO on its basis, this voltage is realized the gain amplifier of Q910 field effect transistor is controlled by adjusting this voltage PA-RO from logic control circuit U610.For example, when control voltage PA-RO is main level, the Q912 saturation conduction, collector to the equivalent resistance between the emitter diminishes, and it is directly in parallel to be equivalent to R1164 and R1163, and the comprehensive source resistance of Q910 is reduced, drain current strengthens, thereby has transferred the circuit gain amplifier big.In addition, also be provided with gain control element based on Q910 at the input circuit of low noise amplifier circuit, be added with control voltage on the base circuit of U910, this voltage of LNA-GAIN also is from the U610 logic control circuit.When control voltage reduced, the conducting degree variation of U910 and then reduced the diode D910 conducting degree of emitter circuit, the equivalence conducting resistance becomes big, shunting action to high-frequency signal reduces, and the amplitude output signal of Q910 is increased, and output voltage gain improves.On the Q910 signal output apparatus, be provided with and receive high freguency bandpass filter F911, its effect be allow the high-frequency signal that needs by and unwanted high-frequency signal does not pass through, a high-frequency signal that need only to allow enters mixting circuit.

Mixting circuit MIX is born by U913, and the high-frequency received signal of Q910 the 4th pin is through L1175, and C923 injects F911 the 2nd pin, from the output of the 5th pin, enters the 1st pin of U913 by coupling capacitance C921.So-called mixing is exactly simultaneously at U913 input high-frequency received signal and reception high-frequency local oscillation signal, utilizes the nonlinear characteristic of U913 to obtain the difference frequency signal of two signals.The high frequency of U814 the 4th pin output receives local oscillation signal RX-LO through C853, L1167 injects the 3rd pin of U913, meanwhile high-frequency received signal is also sent into U913 the 1st pin through C921, and these two signals difference frequency after the mixing in chip becomes intermediate-freuqncy signal and exports from U913 the 6th pin.The frequency of intermediate frequency received signal is changeless, and centre frequency is 85.38MHZ, and intermediate-freuqncy signal is through L1162, and the intermediate-frequency filter that C928 forms is delivered to subordinate's signal processing circuit of intermediate frequency by coupling capacitance C922.The working power V-SYNTH of mixting circuit is provided by the U921 Voltage stabilizing module.C912, the feed circuit of the frequency mixer that L1157 etc. form.

Receiving intermediate frequency amplification IFAMP is finished by the Q911 triode, the Q911 base stage injects intermediate-freuqncy signal, this circuit has the amplifying power of 12db to intermediate-freuqncy signal, its peripheral cell R1155, R1156, R1159 are base biasing resistor, and R1160 is an emitter resistance, the interchange negative feedback is arranged, be used for determining the dc point of this circuit.U911 is a gain control element, be used to adjust the gain amplifier of intermediate frequency amplifier, import from U911 the 5th pin when regulating control voltage PA-RO, the output of the 4th pin is added on the tie point of R1155 and R1156, pass through R1156, L1159 injects the Q911 base stage, thereby has regulated the gain amplifier of Q911, has compensated the signal filtering loss that intermediate-frequency filter F912 is caused.The output of Q911 collector signal makes coupling capacitance C917 inject F912 the 9th pin IN one end, by F912 intermediate-freuqncy signal is carried out filtering, realizing reducing the mirror image that mixing caused disturbs, also intermediate-freuqncy signal is separated by F912, become two the signal RX-IF1 and the RX-IF0 of 90 ° of phase phasic differences, output of the 5th pin and the 2nd pin OUT from F912 exports respectively.Through L1161, waveform collating elements such as C920 enter coupled transfer capacitor C 914 thereafter, and C915 introduces U939 receiving demodulation device (IFR3000) with signal and is for further processing.

Among Fig. 5, the received signal treatment circuit is to be finished by receiving demodulation device U939.Its model is IFR3000-488CCF, and this is the special-purpose intermediate frequency process chip that connects with central microprocessor U610, and its chip circuit comprises the AGC intermediate frequency amplifier, and the PXI/Q detuner receives intermediate frequency VCO circuit, low-pass filter, analog to digital converter, functions such as ADC.Chip is provided with 48 leading foots.

The IFR3000 chip is provided with the binary channels intermediate frequency and amplifies and the RXI/Q demodulator circuit.Have one the tunnel to be signalling channel under the CDMA pattern, another road is FM, the signalling channel under the FDMA pattern.11st, 12 pin are CDMA intermediate frequency modulated wave RXI/Q input pins, and standard is CDMA-IF and CDMA-

9th, 10 pin are FM signal input pins, are labeled as FM-IF and FM-

The input utmost point of two passages all is provided with the AGC intermediate frequency amplifier, and the two-way amplifier is under the effect of the 7th pin VCONTRCL input control voltage, and two-way is shared, realizes that the control intermediate frequency amplifies automatically.RX-AGC-ADJ is equivalent to AFC control voltage.Above-mentioned two paths of signals is all delivered to channel switching circuit.Also be provided with pattern-recognition and control circuit in the chip, the CDMA that the parallel RXI/Q demodulator circuit of two-way is exported respectively, or the RXI of FM pattern and RXQ two paths of signals, determine that actually which corpse road signal goes to the back newspaper, is determined by pattern-recognition and control circuit.Baseband signal is delivered to CDMA low-pass filter arranged side by side or the FM low-pass filter has 4 the tunnel, they are provided with the gain circuit for regulating and controlling in the back level respectively, control voltage Q-0FFSET and I-OFFSET are imported by the 27th, 28 pin respectively, this two-way control voltage all is from logic control circuit U610, the baseband signal of CDMA or FM pattern is respectively through separately A/D change-over circuit ADC, analog baseband signal is converted to digital baseband signal, and in fact the utility model is not used the FM passage free time.CDMA baseband signal through demodulation output is 8 tunnel parallel digital signals, by 39-42 pin output base band component WXQD (3:0), by 45-48 pin output base band component RXID (3:0).Deliver to logic/baseband circuit U610 and go to do further digital processing.

U939 is provided with the RXIFVCO local oscillator, and the 21st, 22 pin are the peripheral cell incoming end.Oscillation frequency is 170.76MHZ, the frequency signal that becomes 85.38MHZ after the oscillator signal two divided-frequency is sent into the RXI/Q demodulator circuit, and U939 delivers to the sampled signal of outside PLL module U816 as frequency synthesizer from the 25th pin output intermediate frequency local oscillator signal RX-IFVCO-OUT.This signal is carried out bit comparison mutually by frequency division and reference clock signal and obtains direct current control voltage RX-IF-DO in the PLL module, its DC level is about 1.4v, export by U816 phase-locked loop module the 20th pin, through resistance R 1184, R1187 is added to the D911 of two varactors, the D912 negative pole is used to regulate the numerical value of intermediate frequency local oscillator frequency.

Among Fig. 6, phase-locked loop frequency combiner circuit 9 comprises reference clock oscillator OSC810, PLL module U816, and radio frequency VCO circuit U 815, radio frequency VCO buffer amplifier U814, amplifier Q811, impact damper U936 forms.

It both provided 19.68MHZ base reference signal to frequency synthesizer reference clock oscillator OSC810, provided logic clock signal to logic control circuit again.When automobile key is just opened, when the utility model feed circuit become " opening " attitude from " pass " attitude moment, its power circuit reference clock control voltage is connected to U923 the 5th pin OUT, 2.8v on the supply voltage, its power supply power supply enters Q811 the 3rd pin, V-IF power supply Q811 saturation conduction the 4th pin exports voltage on the 4th pin VCC of reference clock OSC810 to, makes the OSC810 circuit must establish beginning work by cable, from the 3rd pin OUT output 19.68MHZ logic clock signal of OSC810.This signal is exported through C864, and one road signal is delivered to the 8th pin of PLL module U816, and another road signal is delivered to the 36th pin of processing circuitry of intermediate frequency U939.In fact the 19.68MHZ clock signal also will be delivered to base band/logical circuit U610 and make logical timer.

Like this after OSC810 starts, because U610 exports one road high level signal TCXO-EN, even automobile is because other reasons is flame-out, needing to make motor continuously starts up the car, when being descended, automobile 12V cell voltage then can not disappear owing to the TCXD-EN high level signal at once, can continue to keep Q811 the 3rd, 4 pin to be in conducting state, so can not allow the utility model think shutdown by mistake, remove the trouble that automobilist's licence number is re-entered in start again from because the automobile batteries voltage instantaneous reduces.Need to prove that as long as the driver do not shut down (pulling up car key), equal starter motor at once behind automobile flameout need not be imported licence number.Otherwise,, insert key again and start shooting again and then must examine licence number and just allow startup in case pull up key shutdown.After the OSC810 circuit start, U610 is also to OSC810 the 1st pin input high level TRK-LO-ADJ control level, and the similar AFC voltage that works can play automatic frequency control and complete machine control is synchronous with phase-locked loop systems.

PLL module U816 is the core of phase-locked loop, and its chip is provided with phase detector, frequency divider.Two signals that the integrated phase detector of high frequency need be imported, one is the 19.68MHZ reference clock oscillator signal of U816 the 8th pin TCXO-IN input, from the OSC810 module; Another is the high frequency VCO oscillator signal from U816 the 5th pin RX-IN input.It is from radio frequency VCO module U815 the 4th pin OUT, this signal is in chip behind the programmable frequency divider frequency division, add to another input end of phase detector with fractional frequency signal, by this phase detector two input signals are carried out the phase bit comparison, output ripple dc error control voltage, has the both-end output characteristics, charge pump power supply (pump circuit) converts the both-end current output signal to single-ended property control voltage in chip again, this direct current control voltage is exported through U816 the 3rd pin DO-RF, through R1092, C869, C866, the filter network that R1094 constitutes is by the 1st pin VC of link resistance R1091 injection U815.The frequency division of the programmable frequency divider of U816 in-core certainly will be come by U610, control.The signal that U610 sends here is respectively by the 12nd pin PLL-CLK, and the 14th pin PLL-DATA is in the 15th pin PLL-EN injection U816 chip.They are respectively the clock signals of frequency synthesizer circuit, data-signal and enable (permission) signal.

The U816 in-core is provided with two groups of phase detectors, and respectively with radio frequency VCO circuit, U815 intermediate frequency VCO circuit combines in the U939 chip, constitutes two groups of phase-locked loop frequency synthesizer systems.U816 the 18th pin RF-IN input receive intermediate frequency VCO oscillator signal RX-IFVCO-OUT it be from intermediate frequency process chip receiving demodulation device U939 the 25th pin RXVCO-O through coupling capacitor C 953, R1183, L1066 inject the intermediate frequency phase detector of U816 in-core; Meanwhile, the TXCO-IN input reference clock oscillator signal of U816 the 8th pin also is added to the intermediate frequency phase detector.The intermediate frequency phase detector carries out the phase bit comparison to two input signals, also export an error controling signal, carry out current/voltage through charge pump circuit, export direct-current control voltage by the 20th pin DOIF after both-end/single-ended conversion, through R849, R1095, C874, C875, the low-pass filter of compositions such as C871 carries out obtaining after the smothing filtering AFC voltage to be sent into the 21st pin RXVCO-T1 and the 22nd pin RXVCO-T2 of U939 export intermediate frequency VCO local oscillation signal by the RXVCO-O of the 25th pin through inter-process after, sends into the 18th pin IF-IN of U816 as sampled signal.

U815 is the core parts of radio frequency VCO circuit, and four leading foots are arranged, and is respectively the VCC power end, VC control end, OUT output terminal and a plurality of earth terminal.Radio frequency VCO, PLL module U816 and peripheral cell have formed radio frequency VCO phase-locked loop systems, produce the radio frequency VCO local oscillation signal of centre frequency 967MHZ, and this signal has two whereabouts, and one is that the up-converter circuit of delivering to radiating circuit is made the TXRFVCO local oscillation signal; Another is that the mixting circuit of delivering to receiving circuit is made the RXRFVCO local oscillation signal.By the radio frequency VCO signal process C867 of U815 the 4th pin output, R1090 sends into PLL module U816 the 5th pin RX-IN, makes the sampled signal of radio frequency VCO local oscillation signal, delivers to the radio frequency phase detector of U816 in-core again through frequency division.This phase detector carries out bit comparison mutually to reference clock signal with the fractional frequency signal of radio frequency VCO, obtain the direct current error controling signal, and after charge pump for processing, export by the 3rd pin DO-RF, through R1092, C869, R1094, C866, R1091 becomes direct-current control voltage and injects U815 the 1st pin VC behind external dual-time constant such as the C865 low-pass filter, realize the output local oscillation signal of control radio frequency VCO circuit automatically.

Radio frequency VCO local oscillation signal by the output of U815 the 4th pin is not only sent into U816, and it also will pass through C867, and C856 sends into the 1st pin IN of radio frequency VCO buffer amplifier U814, and U814 is provided with two local oscillation signal output terminals.Wherein the radio-frequency (RF) local oscillator signal of the 4th pin OUT output is through C853, and L1064 injects U936 the 2nd pin RF-IN of impact damper, by the 3rd pin out output TX-LO signal, delivers to the transmission local oscillation signal that up-converter circuit is made up-conversion again.Deliver to mixting circuit by U814 the 2nd pin OUT output radio-frequency (RF) local oscillator signal, signal RX-LO is made the reception local oscillation signal of frequency mixer and use.

Among Fig. 7, central little processing and logic control circuit 6 comprise logical circuit U610, external storage U640, storer U620.Little processing of central authorities and logic control are to be finished by logical circuit U610, its chip has 208 each leading foots, become matrix form to arrange, can be divided into two parts by function, one is the baseband signal processing of circuit, can carry out digitized processing to transmitting and receiving baseband signal, logic control is monitored and implemented to another logic control circuit to the machine system circuit.

The memory of central microprocessor need of work, the identification process data signal is the ROM by being provided with in the U610 chip only, the memory space of RAM is not enough, also to increase storer at the U610 peripheral circuit, U620 (DS42533) and U640 (AT24C2566-10U1) carry out information interchange because U610 control and data signal with external storage to U620 output multichannel, U610 exports 16 signal D[0:15 that read and write data], 21 bit address data-signal A[0:20], be connected to each relevant leading foot of U620.U610 is also to U620 output chip selection signal CS, reset signal RESET and read-write control signal LWR etc.And getting in touch of U620 and external storage U640 is to pass through I ²The C bus is carried out message exchange.U610 16 position datawires mark D0-D15 on chip port, address wire is labeled as A0-A20.Chip GRIO15, N14, GPIO31, M14 port also are address wires.GPIO of the present utility model is used for general input/output terminal.P14, N4 pin are the chip selection signal ports of RAM storer.P14 pin output RAM-CS1 signal, N4 pin output RAM-CS2 signal, the PA14 pin is the chip selection signal of output RAM storer, the N4 pin then is connected to composite memory LB port.The R14 port signal is used for the control of reading of storer, and the P16 port is used for the control of writing of storer.Reportedly defeated three control signals of data bus upper domination number are respectively RD-N, LWR-N and HWR-N, and wherein HWR-N is that the high byte that 8bit visits is write the control signal, LWR-N is that low byte is write the control signal.

The U620 chip comprises two kinds of storeies, i.e. the SRAM static memory of 32 FLASH flash memorys and 4M byte.Flash memory is used for the application storing code, and static memory uses as the ephemeral data storage space, and it can preserve inner marker information, calls deal with data and chronometric data.

U640 EEPROM is the 256K EROM, be used to store ESN, information such as NAM or in running car the storage record traffic control command centre address title brevity code that provides of each earth signal base station on the way, for China in the future domestic automobile carry out to have the records of distance by the log and hand over the charge foundation of road toll.Traffic control center be can also store at this and the telephone number of service and service short message etc. provided for the driver.For traffic control center collection information service fee as the charge foundation, certainly country also can be used as a kind of to the automobile owner a kind of welfare and be free of charge.

U610 microprocessor ARM7TDMI, 32 bit processors can provide the support of serial I storer interrupt control and multiple circuit, 16 D0-D15 of the data bus of chip, and address bus is 23, A0-A22 provides the searching space of maximum 16M for each connecting circuit.Address wire A21, A22 also can be used as the GPIO line (GPIO15, GPIO31) little processing has six special-purpose sheets choosings, wherein connect be used for the RAM storer (RAM-CS1, RAM-CS2), two are used for ROM/FALSH storer (ROM-CS1, ROM-CS2), two are used for the 1cd display circuit.

Logic control circuit mainly is that the circuit by two aspects constitutes, the one, and clock circuit, the 2nd, reset circuit.

Clock circuit of the present utility model both had been provided with the special clock circuit, the clock circuit that has also adopted chip to set up simultaneously.In the U610 chip, TCXO and CH2PX8 are arranged, two clock signals, be exactly these two clock signals be power circuit, radiating circuit, receiving circuit, base band signal process circuit etc. provides the clock signal of benchmark, with relevant timing signal.Every order is executed without fail to make complete machine work, in good order.The clock circuit of U610 is CPU, ARM7TDMI, 32 bit memories, emission and reception control, sleep clock, 32.768KHZ crystal oscillator; Clock TCXO, external 19.68MHZ signal, the numerical coding demoder, speech codec, interface circuit, reset circuit, address bus (A0-A21), data bus (AD0-AD15), internal memory control, A/D, D/A conversion etc. all plays crucial effects.

Reset circuit of the present utility model is the initial unification of circuitry, the assurance of the rhythm of following the prescribed order running, and this circuit not only provides reseting controling signal to central microprocessor, also provides reseting controling signal to other chips.Make the utility model can in time send the control signal that restarts to central microprocessor when start, make operation procedure at the beginning, the timely zero clearing of counter values is 0000, and operation system is started anew, and carries out the program command that grows with each passing hour.

Voice transmission baseband circuit in the microprocessor setting uses this circuit as specific use.Shine under the RST at the normal transmission digit plate, it is idle that its voice send baseband circuit, only is subjected to criminal hijack the automobilist, and the driver opens when requiring assistance alarm switch KH, voice send base band and just start working, and the simulated voice electric signal that ruffian in the car speaks is sent into circuit in the U610.The utility model has used two transmitters, and one is transmitter in the machine, represents with MIC+, and another is hidden in car other local transmitters and represents with EAR-MIC+.The G17 pin of U610, MCBIAS provides Dc bias for above-mentioned two transmitters.R909 transmitter MIC+ in machine provide bias voltage, allows this analogue voice signal through C660, injects the J16 pin MICIP of U610, enters the chip audio amplifier circuit.R921 provides bias voltage to the transmitter EAR-MIC+ that hides in car, and this road speech is through the H14 pin of C663 injection U610, and MIC2P enters the audio amplifier circuit of chip.In fact the G14 pin MICFBN of U610, G15 pin MICFBP is the output pin that the two-way simulation sends the feedback circuit of voice amplifier, peripheral cell R894, R899 are feedback resistance, and H17 pin MICINP and G16 pin MICINN are the input ends of audible feedback signal, J17 pin MICOUTN connects the external network C 651 of output, H16 pin MICOUTP meets C654, C655, C653, R898, feedback signal resonant earthed systems such as R899.Send into the U610 chip voice analog signal is carried out digitized processing, in the U610 chip, include pcm encoder (A/D conversion), vocoder (voice digital compression), convolutional encoding and block interleaving coding (error correction is anti-interference) and channelizing circuit such as (spread spectrums) that is to say that the base-band digital processing capacity that is amplified between the TXI/Q modulator from analogue audio frequency all finishes in the U610 chip.Voice signal carried out after the digitized processing and is combined into a place forming and sending baseband signal TXI/Q from the license plate digital signal of CN711 the 6th pin.This signal is by A6 pin Q-OUT-N, AT pin I-OUT, and B6 pin I-OUT-N, B5 pin Q-OUT exports side by side, delivers to a back level TXI/Q modulation circuit and handles, and injects the radio-frequency (RF) power amplification circuit at last and becomes frequency electromagnetic waves and radiate from emitting antenna.

Reception baseband circuit in the microprocessor setting is to be used for traffic control center, transmits traffic instructions for the driver, and the service of character message breath is provided, and is shown by the utility model LCDs LCD.Receiving demodulation device U939 chip receives, and demodulated base band signal RXI/Q is 8 digital signals arranged side by side, its leading foot is labeled as RX-QDATA[0:3 respectively] and RX-IDATA[0:3], they enter the D13 pin C-RX-QDATA0 of U610, C13 pin C-RX-QDATA1, B13 pin C-RX-QDATA2 side by side, A13 pin C-RX-QDATA3, B14 pin FM-RX-IDATA0, B15 pin FM-RX-QDATA1, C17 pin, C-RX-IDATA2, C16 pin C-RX-IDATA3.The compressed extender of receiving baseband signal RXI/Q (vocoder) is separated spread spectrum (channelizing) error correction (convolution decoder, deinterleaving), PCM decoding processing such as (D/A conversions) is afterwards read demonstration at LCDs LCD the traffic instructions and the service short message of traffic control center is offered the driver.But when read for the driver and to watch instruction not make hard regulation.Entirely by the driver do not influence under the driving safety situation at one's convenience.Certainly be provided with the caller identification circuit on circuit, central microprocessor U610 injects the Q712 base stage with incoming telephone signal ALERT-LEDEN level, and its triode saturation conduction is lighted light emitting diode signal driver LCD will have command information to assign, and read in the time of please selecting.

Among Fig. 8, the power supply of power circuit 1 derives from automobile 12V accumulator, can be divided into three parts according to the function of power circuit, 1 voltage transformation, 2 power supply voltage stabilizings, the control of 3 power supplys.Automobile 12V accumulator injects R754 insurance resistance through automobile key switch and enters the 2nd pin that bridge power polarity identification decision circuitry that D511-D514 forms enters power converting circuit U510, charge to C510 simultaneously, the U510 integrated circuit modules is transformed into the 4.8V DC voltage to input+12V, export from the 8th pin, through C513, C514 filtering enters isolating diode D515, realizes giving voltage stabilizing circuit V-RING power supply.Its R757 is the output feedback resistance of U510, and R758, R759 are output voltage transform sampling resistance, and R756, C511, C512 are the peripheral vibrationproof network element of U510.

Power supply stabilization circuit of the present utility model is that five terminal voltage stabilizer or three terminal regulator are set up in requirement respectively according to the circuit each several part, U765, and mu balanced circuit modules such as U918-U924 realize the D.C. regulated power supply power supply to circuitry 2.5V-3.0V.U918, U919 voltage stabilizing output 2.8V give V-MSMP respectively, V-MSMC and PON-RESET-N power supply.U923 voltage stabilizing output 2.8V give the V-IF circuit supply, U922 five terminal Voltage stabilizing module output 2.5V powers to V-MSMA, U921 output 3.V give the V-SYNTH circuit supply, U920 output 2.5V powers to TCXO-ON, U924 voltage stabilizing output 3.0V powers to V-RFTXD, and U765 voltage stabilizing output 2.8V powers to UIM card digital signal interlock circuit.Above-mentioned each five terminal supply voltage Voltage stabilizing module IN the 1st pin is the input end of power supply power supply, and OUT the 5th pin is the output pin of stabilized voltage supply, and is connected the input of five terminal Voltage stabilizing module or three-terminal voltage-stabilizing module, and the electric capacity on the output port is power filtering capacitor.EN the 3rd pin is the input end of output voltage switching signal level.Switch control voltage TCXO-ON (ON represents that high level is effective) this control level (2.4v) is used for the trigger switch power circuit from the U610 logic control circuit, makes power supply export or not export supply voltage by the instruction of U610.

Irreversible instruction control circuit 10 comprises irreversible instruction control unit U511, the instruction of commander U511 operation is assigned by U610, the U610 logic control circuit injects Monitoring and Controlling signal SLEEPN for respectively U511 chip timing circuit at U511 the 8th, 10 pin, intermittently control signal IDLEN is reception holding state, stand-by time 20 seconds when being this pin low level, operate as normal is a high level, signal transmission time is 2 seconds, changes the standby low level state thereafter again over to, and is continuous and so forth.This is a normal operation, but irreversible instruction control is to control the state of can not realizing in the IDLED of U610 standby level and SLEEPN detection control level, also be that automobile is by criminal hijack, the driver alarm switch KH that requires assistance is opened, the irreversible instruction control circuit of U511 will no longer receive the control of U610 level, the time that it will also overturn and transmit for contact 20 second time of having a rest of intermittence its objective is to cooperate the police to monitor the vehicle location of being held as a hostage, and helps the police to find out and stop and deploys to ensure effective monitoring and control of illegal activities.The chip LH002A of U511 has two-way time-delay (regularly) circuit, BG510, BG511, be respectively the conversion of signals output element of this two-way timing circuit, the collector of Q510 is connected in U924 the 3rd pin EN end, the collector of Q511 is connected in the 3rd pin EN end of U923, cooperates irreversible instruction control circuit to close or open power supply output.Peripheral cell C515, C516 is for discharging and recharging timing capacitor, and W1, W2 are gang potentiometer, and with R762, R763 constitutes the time-delay output of timing signal circuit together and closes.Regulate W1, W2 can make the time of opening or closing more accurate near actual scientific.

Central authorities little processing and logic control circuit 6 realizes that traffic control centers are to be controlled the approval of the various audit recognition instructions that U916 the 1st, 3,4,5 pin incoming level that represent traffic command centres come this car transmission respectively or do not approved by the relevant circuit output end mouth of U610 to the control of automobile igniting circuit.Such as, it is correct that on behalf of the driver, U916 the 1st pin high level import licence number, approval.The low level representative is incorrect, does not approve.It is correct that on behalf of road toll, the 3rd pin high level hand over money to key in number, approval.Low level is represented incorrect, does not approve.The 4th pin high level is represented the automobile annual examination, and the check mark number is correct, approval.The low level representative is incorrect, does not approve ... the 2nd pin of U916 is connected with the Q512 base stage, and the Q512 collector is connected with relay J 1 coil winding and GND with R744 respectively.If the signal that U916 the 1st, 3,4, each pin of 5...... are sent here from the U610 interlock circuit all is a high level, then Q512 is idle, so do not have electric current among the R744, relay J 1 is failure to actuate, its relay tip K2-1 is in off-state, J2 also is failure to actuate, and J2 relay tip K3-1 then is in the state of connection, and also equaling the car engine ignition circuit is the state that is in connection.Start up the car and can start this moment.If the driver does not hand over road toll, perhaps the driver driving license number of Jian Ruing is incorrect etc.As long as the little processing logic control circuit of U610 central authorities has a port to be in low level for U916 level input port, then the Q512 base stage can have low level signal input conducting because of base stage, cause the J2 relay to disconnect the action of control contact, make contact K3-1 disconnect the automobile igniting circuit power supply, automobile can't be started.

Claims (9)

1, a kind of automotive electronics digit plate shines, it comprises power circuit (1), the UIM card interface circuit (4), the simulation that it is characterized in that: further comprising LCD (2), key circuit (3) that is arranged on bridge instrumentation Pan Chu and the identity that comprises each automobile, qualification content send sound circuit (5), and these circuit are connected with central little processing and logic control circuit (6); Central little processing simultaneously and logic control circuit (6) also are connected with radiating circuit (7), receiving circuit (8), phase-locked loop frequency combiner circuit (9), irreversible instruction control circuit (10) respectively, receiving circuit (8) then is connected with the received signal treatment circuit, and radiating circuit (7) is connected with emissioning signal treatment circuit.

2, automotive electronics digit plate according to claim 1 shines, it is characterized in that: described radiating circuit (7) comprises UIM card data-signal memory circuit U713, UIM clock circuit U712, logical circuit U610, high frequency power amplification module U811 and power amplification control module U810, unidirectional loop device F811, Hi-pass filter F810, emitter follower Q810, diplexer F910, radio frequency adaptation U912, antenna CHIP-ANT, UIM card supply voltage is adjusted mu balanced circuit U765; Wherein, logical circuit U610 input end is connected with key circuit (3), also sending sound circuit (5) through K switch H with simulation simultaneously is connected, output terminal then meets UIM card data-signal memory circuit U713 respectively, UIM clock circuit U712, UIM card supply voltage is adjusted mu balanced circuit U765, UIM card interface circuit (4) CN711, output terminal also is connected with Hi-pass filter F810 through emissioning signal treatment circuit U812 simultaneously, Hi-pass filter F810 is connected with high frequency power amplification module U811, high frequency power amplification module U811 output terminal is through unidirectional loop device F811, diplexer F910, radio frequency adaptation U912 is connected with antenna CHIP-ANT, its output terminal also is connected with power amplification control module U810 simultaneously, power amplification control module U810 is connected with emitter follower Q810, and emitter follower Q810 is connected with logical circuit U610.

3, automotive electronics digit plate according to claim 1 and 2 shines, it is characterized in that: described emissioning signal treatment circuit U812 adopts the RFT3100 chip, it is with the UIM digital signal of licence plate, the voice signal of the digital signal of keyboard circuit output and process simulation process converts the transmission baseband signal to and modulates and up-converter circuit, convert high frequency to and send the modulated wave signal, send into high frequency power amplification module U811 again and carry out high frequency power control.

4, automotive electronics digit plate photograph according to claim 1 is characterized in that: described receiving circuit (8) comprises that high frequency electromagnetic wave signal receives network, radio frequency adaptation U912, diplexer F910, amplifier U910, low noise amplifier Q910, reactive power supply filtering circuit, gain control circuit Q912, mixting circuit U913, high freguency bandpass filter F911, receiving demodulation device U939, intermediate-frequency filter F912, triode Q911, logic control circuit U610, gain control element U911 forms; Wherein, receiving antenna is at first sent the high frequency electromagnetic wave signal that receives into the reception network, radio frequency adaptation U912 reinjects, by it signal is sent into diplexer F910 more then, high-frequency signal injection low noise amplifier Q910 amplifies then, its output signal is injected high freguency bandpass filter F911, the output terminal of high freguency bandpass filter F911 is connected with mixting circuit U913, the intermediate-freuqncy signal of mixting circuit U913 output is injected triode Q911 base stage, base stage also is connected with gain control element U911 simultaneously, triode Q911 collector signal exports intermediate-frequency filter F912 input end to, delivers to receiving demodulation device U939 by its output terminal; Simultaneously, low noise amplifier Q910 also is connected with gain control circuit Q912, gain control circuit Q912 is connected with logic control circuit U610, mixting circuit U913 input end is connected with radio frequency VCO buffer amplifier U814 in the phase-locked loop frequency combiner circuit, radio frequency VCO buffer amplifier U814 then is connected with PLL module U816 with radio frequency VCO circuit U 815, and PLL module U816 is connected with logic control circuit U610.

5, according to claim 1 or 4 described automotive electronics digit plate photographs, it is characterized in that: described high frequency electromagnetic wave signal receives network by inductance L 1155, L1156 capacitor C 930, and C931 forms; Reactive is powered filtering circuit by capacitor C 911, L1159, and C916 forms; Diplexer F910 only allow centre frequency be 881MHZ up and down the signal in each 12.5MHZ scope pass through, it is the 836MHZ signal output of each 12.5MH scope up and down that its transmitting filter then can only allow centre frequency; Low noise amplifier Q910 is a field effect transistor, and it has the gain amplifier of 17db to the signal of 800MHZ frequency range; Mixting circuit U913 gets their difference frequency signal with high-frequency received signal and reception high-frequency local oscillation signal, becomes intermediate-freuqncy signal output, and its centre frequency is 85.38MHZ; Intermediate-frequency filter F912 then separates intermediate-freuqncy signal, becomes two signal outputs of 90 ° of phase phasic differences.

6, automotive electronics digit plate photograph according to claim 1, it is characterized in that: described received signal treatment circuit is made up of receiving demodulation device U939, and its model is IFR3000-488CCF; It is connected with local oscillator, and oscillation frequency is 170.76MHZ.

7, shine according to claim 1 or 4 described automotive electronics digit plates, it is characterized in that: described phase-locked loop frequency combiner circuit (9) comprises reference clock oscillator OSC810, PLL module U816, radio frequency VCO circuit U 815, radio frequency VCO buffer amplifier U814, amplifier Q811, impact damper U936 forms; Wherein, the reference clock oscillator OSC810 both provided 19.68MHZ base reference signal to frequency synthesizer, provides logic clock signal to logic control circuit U610 again; Integrated two groups of phase detectors in the PLL module U816, frequency divider, it carries out mutually bit comparison by its inner integrated phase detector to two input signals with the 19.68MHZ reference clock oscillator signal of reference clock oscillator OSC810 input and the high frequency VCO oscillator signal of radio frequency VCO circuit U 815 outputs, export single-ended property control voltage, through resistance R 1092, R1094, capacitor C 869, the filter network that C866 constitutes injects radio frequency VCO circuit U 815 by link resistance R1091; Simultaneously, the phase detector that is provided with in the PLL module U816 combines in receiving demodulation device U939 chip with radio frequency VCO circuit U 815, constitute two groups of phase-locked loop frequency synthesizer systems, the intermediate-freuqncy signal of receiving demodulation device U939 output is through coupling capacitor C 953, resistance R 1183, inductance L 1066 is injected PLL module U816, the reference clock oscillator signal is also sent into the intermediate frequency phase detector, the intermediate frequency phase detector carries out the phase bit comparison to two input signals, the output direct-current control voltage, through resistance R 849, R1095, capacitor C 874, C875, the low-pass filter that C871 forms carries out obtaining a voltage after the smothing filtering and sends into receiving demodulation device U939, output intermediate frequency VCO local oscillation signal is sent into PLL module U816 as sampled signal, and radio frequency VCO circuit U 815 produces the radio frequency VCO local oscillation signal of centre frequency 967MHZ, this signal has two whereabouts, a process capacitor C 867, resistance R 1090 is sent into PLL module U816, obtains the direct current error controling signal after the processing, through resistance R 1092, R1094, R1091, capacitor C 869, C866 becomes direct-current control voltage and injects radio frequency VCO circuit U 815 behind the external dual-time constant of the C865 low-pass filter; Another Lu Zejing capacitor C 867, C856 sends into radio frequency VCO buffer amplifier U814, radio frequency VCO buffer amplifier U814 is provided with two local oscillation signal output terminals, the radio-frequency (RF) local oscillator signal of one of them output is through capacitor C 853, inductance L 1064 is injected impact damper U936, output signal is made the transmission local oscillation signal of up-conversion to up-converter circuit again, and another delivers to mixting circuit by radio frequency VCO buffer amplifier U814 output radio-frequency (RF) local oscillator signal, signal is made the reception local oscillation signal of frequency mixer and is used.

8, automotive electronics digit plate photograph according to claim 1 is characterized in that: little processing of described central authorities and logic control circuit (6) comprise logical circuit U610, external storage U640, storer U620; Wherein, logical circuit U610 model is ARM7TDMI, external storage U640 is that model is AT24C2566-10U1, storer U620 is DS42533, its chip comprises two kinds of storeies, the i.e. SRAM static memory of 32 FLASH flash memorys and 4M byte, storer U620 and external storage U640 pass through I ²The C bus is carried out message exchange, clock circuit and reset circuit are arranged in the logical circuit U610, and send sound circuit MIC with simulation and be connected, this circuit is made up of two transmitters, one be in the machine transmitter another be other local transmitters in car of hiding, logical circuit U610 chip carries out digitized processing to voice analog signal, is combined into a place with the license plate digital signal then and forms the transmission baseband signal, and injection radio-frequency (RF) power amplification circuit becomes frequency electromagnetic waves and radiate from emitting antenna; Simultaneously, logical circuit U610 with the signal Processing that receives after by liquid crystal display displays, read at one's leisure for it.

9, automotive electronics digit plate according to claim 1 shines, it is characterized in that: described power circuit (1) comprises power converting circuit U510, the output of automobile 12V accumulator is sent into power converting circuit U510 through the bridge power polarity identification decision circuitry that D511-D514 forms, become the 4.8V direct current after capacitor C 513, C514 filtering is sent into into isolating diode D515, the output termination five terminal voltage stabilizer U765 of isolating diode D515 or three-terminal voltage-stabilizing voltage stabilizer U918-U924 are the D.C. regulated power supply of circuitry 2.5V-3.0V; Irreversible instruction control circuit (10) comprises irreversible instruction control unit U511, its model is LH002A, it is connected with the base stage of triode Q511 with triode Q510, their collector then is connected with U923 with voltage stabilizer U924 respectively, the base stage of triode Q512 is connected with circuit output end mouth controller U916, collector is connected with relay J 1 coil winding and GND with R744 respectively, and emitter is connected with three-terminal voltage-stabilizing voltage stabilizer U924.

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