CN200976156Y

CN200976156Y - Multimedia processing system on self-reconstruction slice

Info

Publication number: CN200976156Y
Application number: CN 200620015447
Authority: CN
Inventors: 朱明程; 徐渊; 曹捷; 田志东
Original assignee: 朱明程
Priority date: 2006-10-26
Filing date: 2006-10-26
Publication date: 2007-11-14
Anticipated expiration: 2016-10-26

Abstract

The utility model relates to a self reconstruction chip multi-media processing system, which comprises: a processor, which is used in the operation and process scheduling of the whole program; a memory, which is used to store the running program and the intermediate numerical; an on-chip bus which is used in the communication of all the parts in the system; a multi-media processing module, a reconstruction configuration file storage and a reconstruction controller which are separately connected with the on-chip bus, wherein, the total or partial of the multi-media processing module can be reconstructed; when the reconstruction controller receives the reconstruction signals from the processor, the reconstruction controller readouts the specified configuration file from reconstruction configuration file storage, and writes in the reconstruction parts of the multi-media processing module by the on-chip bus. When the self reconstruction on-chip multi-media processing system of the utility model is carried out, the utility model has the advantages that: the system has fast processing speed and strong flexibility, can use the equipment to process multiple multi-media signals, can achieve time division multiplexing of the hardware, and can save the hardware sources greatly.

Description

From the reconstruct on-chip multimedia processing system

Technical field

The utility model relates to multimedia processing system, more particularly, relate to a kind of on the reconstruct sheet (SOCsystem on chip) multimedia processing system.

Background technology

The codec of image/video is widely used in television broadcasting, video conference, digital camera, mobile phone, the first-class various fields in life of making a video recording.In order to satisfy requirement real-time, to the scrambler of image acquisition end, and the requirement of the demoder of image receiving terminal is more and more higher.Traditional codec mainly contains two kinds of solutions: a kind of is software solution, utilizes software to realize the encoding and decoding processing.Characteristics such as the advantage of this method is that software has the dirigibility height, and the construction cycle is short, and is scalable.Shortcoming is that speed is subject to processing the restriction of device dominant frequency, usually can't satisfy real-time requirement in portable equipment, therefore uses DSP (Digital SignalProcessor) chip to come raising speed usually; Another kind is a hardware solution, promptly uses ASIC (ApplicationSpecific Integrated Circuit) chip to realize the encoding and decoding processing.The advantage of this method is that speed is fast, and stability is high, and shortcoming is that the construction cycle is long, and very flexible only is applicable to a kind of or a class codec usually.

The utility model content

The technical problems to be solved in the utility model is, the defective of, very flexible slow at the above-mentioned speed of prior art, provide that a kind of speed is fast, dirigibility is strong from the reconstruct on-chip multimedia processing system.

The technical scheme that its technical matters that solves the utility model adopts is: construct a kind ofly from the reconstruct on-chip multimedia processing system, comprising:

Be used for the operation of whole procedure, the processor 5 of process scheduling;

Be used to deposit the program moved and the storer 7 of intermediate value;

Be used for carrying out the on-chip bus 10 of communication between system's each several part,

Also comprise:

Be connected multimedia processing module 8 on the described on-chip bus, that be used for multi-media signal is carried out coding/decoding, all or part of restructural of this module;

Be connected the reconstruct configuration file reservoir 9 of configuration file on the described on-chip bus, that be used to deposit at least two reconstructed module;

Be connected the reconfigurable controller 6 on the described on-chip bus, described reconfigurable controller 6 is when receiving the reconstruction signal that described processor 5 sends, read appointed configuration file from reconstruct configuration file reservoir 9, write the restructural part 81 of multimedia processing module 8 by described on-chip bus 10.

In system described in the utility model, described multimedia processing module 8 comprises fixed part 82 and reconstruct part 81.

In system described in the utility model, described on-chip bus 10 comprises CORECONNECT bus (SOC (system on a chip) of a kind of IBM Corporation special use (SoC system on chip) bus); Described restructural part 81 is connected by BUS MACRO (a kind of internal resource of FPGA device) 83 with signal between the fixed part 82.

In system described in the utility model, but described multimedia processing module 8 comprises FPGA (the Field Programmable Gate Array) device of field programming; Area after described restructural part 81 each reconstruct on described FPGA is all identical, and the border and the interconnection resource of its shared area immobilize.

In system described in the utility model, described restructural part 81 comprises functional module and IPIF (IPInterface) module, described functional module links to each other with the IPIF module, and described IPIF module also links to each other with described on-chip bus 10 except that with functional module links to each other.

In system described in the utility model, described reconfigurable controller 6 comprises HWICAP (Hardware Internal Configuration Access Port) module or the independent MCU that is embedded among the FPGA.

In system described in the utility model, described HWICAP module writes restructural part 81 by the IPIF module with the reconstruct configuration file content.

In system described in the utility model, described HWICAP module writes the reconstruct configuration file content of the configurable logic row of 1bit at every turn.

In system described in the utility model, the multimedia form of described system handles comprise JPEG, JPEG2000, MPEG-2, MPEG-4, H.263, H.264 or among the RM/RMVB one or multinomial.

Implement of the present utility modelly, have following beneficial effect from the reconstruct on-chip multimedia processing system:

Because the hardware capability module changes with the format change of the multi-media signal of receiving in the utility model, promptly adopted self-reconstruction system, so its processing speed is fast, dirigibility is strong, can be with the multiple multi-media signal of a kind of device processes, can realize the time division multiplex of hardware, save hardware resource greatly.

Description of drawings

The utility model is described in further detail below in conjunction with drawings and Examples, in the accompanying drawing:

Fig. 1 is the structural representation of the utility model from reconstruct on-chip multimedia processing system embodiment;

Fig. 2 is the utility model structural representation that restructural or stuck-module are connected with on-chip bus in the multimedia processing module in reconstruct on-chip multimedia processing system embodiment;

Fig. 3 is the logic diagram of the utility model reconfigurable controller HWICAP module in reconstruct on-chip multimedia processing system embodiment.

Embodiment

In the utility model, realization is as follows from the process of reconstruct: the needed hardware configuration of the processing of the multimedia form that may run into earlier (coding/decoding) is divided into fixed part and restructural part, wherein, fixed part is an all identical hardware configuration in processing (coding/decoding) process at different-format, the restructural part then is the processing (coding/decoding) at different-format. the hardware configuration that has nothing in common with each other in the process, for example, functional modules such as DCT coding (discrete cosine coding) that exists at JPEG with in the coding moderate of MPEG-1/2 form and quantification can be divided into fixed part; And the distinctive huffman coding of JPEG functional modules such as (huffman coding, a kind of Variable Length Code modes) can divide the restructural part into, as the content of first configuration file; Distinctive motion compensation of MPEG-1 and motion prediction functional module can divide the restructural part into, as the content of second configuration file; By that analogy, we can define the content of a plurality of configurable files, for example about JPEG2000, MPEG-2, MPEG-4, H.263, H.264, the configuration file content of multimedia form such as RM/RMVB.The content of these configuration files that define is described out (as VHDL) with hardware description language, and to being distinguished (constraint) respectively between other parts in the total system and a plurality of restructural part, with crossing synthesis tool software, obtain the net table of foregoing description.Carry out the NGDbuild (instrument that Xilinx company provides then, its basic function is exactly that the logic netlist file that will be comprehensively generates etc. is translated into Xilinx bottom hardware primitive NGD file), generate NGD (NativeGeneric Database) file separately, assembling at last, set pin etc., the software of packing into and designing obtains system described in the utility model.

As shown in Figure 1, of the present utility model in reconstruct on-chip multimedia processing system embodiment, comprise processor 5, storer 7, profile memory 9, reconfigurable controller 6, multimedia processing module 8 and the on-chip bus 10 that links to each other respectively with above-mentioned each parts, wherein, 8 kinds of multimedia processing modules by comprise restructural part 81, fixed part 82 and be connected restructural part 81 and fixed part 82 between BUSMARCO 83.As seen from Figure 1, have two storeies to be connected on the on-chip bus 10, storer 7 is deposited the code of processor 5 and processor 5 creation facilities program (CFP) spaces and system cache space is provided.Profile memory 9 is deposited at least two configuration files that need the user logic of reconstruct.In the time of need reconfiguring, initiate to reconfigure sequential by processor 5, earlier read configuration file from profile memory 9, send this file and corresponding configuration information to reconfigurable controller 6, user logic resource by 6 pairs of restructural parts 81 of reconfigurable controller reconfigures, and constitutes new logic module.

Virtex-II Pro XC2VP40 in the present embodiment among the use platform-type FPGA of Xilinx (Field Programmable Gate Array) is as hardware platform, in the present embodiment, described processor 5, storer 7, profile memory 9, reconfigurable controller 6, multimedia processing module 8 and all be positioned on the same chip with on-chip bus 10 that above-mentioned each parts link to each other respectively constitute SOC (system on a chip) (SOC systemon chip).The characteristics of the platform-type FPGA maximum of Xilinx are exactly integrated PowerPC stone processor on the sheet, cooperate the CoreConnect bus of IBM special use can conveniently make up SOC (system on a chip).The CoreConnect bus provides the connecting bus of three kinds of fundamental types, is respectively peripheral bus OPB on processor internal bus PLB (processor local bus), the sheet (on chip peripheral bus) and device control bus DCR (device control register bus).So in the present embodiment, on-chip bus 10 is CoreConnect buses.

In embodiment of the present utility model, restructural part 81 can realize the decoding of two kinds of multimedia forms, that is to say to store two kinds of configuration files in profile memory 9, a kind of is the jpeg format decode configuration file, and another kind is the decode configuration file of MPEG-2 form; These two kinds of configuration files can be according to the forms of input code flow and are accessed, and be used to dispose restructural part 81, and its default configuration are the MPEG-2 formats.The formation process of present embodiment is as follows:

The formation of the goal systems of present embodiment is made up of processor 5, on-chip bus 10 and the multimedia processing module 8 that is connected on this bus.Wherein multimedia processing module 8 comprises three parts: fixed part 81, jpeg format decoder module and MPEG-2 formats module, latter two part is with by reconstruct (these two systems be timesharing use).The jpeg format decoder module will appear in the self-reconstruction system in different time segments with MPEG-2 formats module, because the difference of these two restructural parts, two different configurations of total system be can constitute, jpeg format system and MPEG-2 format system are referred to as.For for simplicity, will be referred to as system except the SoC components of system as directed jpeg format decoder module and the MPEG-2 formats module.

Below in conjunction with the development process of the ISE instrument and the EDK instrument of Xilinx company, do detailed explanation with regard to the design cycle of self-reconstruction system.

Front-end Design at first will make up the framework of SoC system.After the flow process according to the EDK regulation generates the template of a SoC system, add the needed HWICAP of self-reconstruction system (HardwareInternal Configuration Access Port) module and some other SoC needed IP of system therein, this moment, the VHDL of generation system described.The logic diagram of described HWICAP is seen Fig. 3.

Design the functional circuit of jpeg format decoder module and MPEG-2 formats module respectively, will make up jpeg format system and MPEG-2 format system in these two IP adding systems respectively according to the requirement of CoreConnect bus specification.Xilinx company provides the connecting interface between IP and the bus, is used to simplify being connected of User IP and bus.By the import tool of EDK, utilize the IPIF module funtion part of jpeg format decoder module and MPEG-2 formats module can be connected in on-chip bus 10, promptly on the Coreconnect bus, see Fig. 2.What deserves to be mentioned is that above-mentioned HWICAP module connected by the IPIF module with being connected also of on-chip bus 10.

So far, the VHDL that has obtained the front end system framework of jpeg format system and MPEG-2 format system and system describes.Simultaneously, the VHDL that also obtains jpeg format decoder module and MPEG-2 formats module describes.

Will make amendment this moment to the top document of jpeg format system and MPEG-2 format system.With doing a clear and definite division between jpeg format decoder module and MPEG-2 formats module and the system, take out interconnected signal each other, remodify the content of Port of system and the logic that is associated according to this interconnected signal.Use the design source language of Xilinx simultaneously, add Bus Marco, make that the signal of (except clock signal) is interconnected through Bus Marco between all jpeg format decoder modules and MPEG-2 formats module and the system.

Through synthesis tool software, VHDL is described by the comprehensive net table that is.Obtain the net table statement separately of jpeg format system and MPEG-2 format system and system.Need in the top layer design, system module, jpeg format decoder module or MPEG-2 formats module module be constrained to black_box when comprehensive.Simultaneously the VHDL description of jpeg format decoder module and MPEG-2 formats module is carried out separately comprehensively, obtained the net table statement separately of these two modules.

The starting point of rear end flow process be designed the net table.What at first need to do is that position to system retrains, simultaneously also to retrain out the reconstruct that fixing position is used for jpeg format decoder module and MPEG-2 formats module at chip internal, to retrain and generate a UCF file (the pin binding file among the FPGA), it should be noted that, jpeg format decoder module and MPEG-2 formats module need be deferred to the physical constraint condition of Xilinx VirtexII Pro chip reconstruct as the part reconfiguration unit.That is, minimum reconfiguration unit is a reconstruct Frame, and but the scope of a reconstruct Frame is the configurable logic of the whole row of 1bit, comprises I/O logic module (IOB) up and down and constitutive logic module (CLB) wherein.Therefore, jpeg format decoder module and MPEG-2 formats module must be made of several Frame, that is to say, jpeg format decoder module and MPEG-2 formats module need occupy the chip position of plurality of continuous permutation, and, retrain the border of above-mentioned two decoder modules, output signal, output pin etc., make it identical, so that be unlikely to lossing signal during reconstruct.

Next step carries out NGDbuild to jpeg format system and MPEG-2 format system respectively, generates NGD file separately, and this NGD file is a description to the total system configuration.Simultaneously, also need system, jpeg format decoder module and three modules of MPEG-2 formats module are carried out respectively the flow process of Xilinxmodular design, according to the wiring of chip constraint carrying out Butut, finally jpeg format decoder module and MPEG-2 formats module are generated the bitstream file.This bitstream file is the part reconstruct configuration flow that these two bitstream files are modules with the difference that downloads to the bitstream file among the FPGA usually.Can not be as the configuration of whole FPGA, the common configuration flow file of its size much smaller than whole FPGA.

At last,, assemble (Assemble), comprise whole MAP the starter system of MPEG-2 format system as system, the Butut wiring, the I/O pin is determined to wait work, and makes up final initialization system configuration flow file.

After The Hardware Design is finished, also need design software, make condition that PowerPC can response external and carry out normal SoC system operation.

With generate reconfigurable module the part configuration file as the deposit data that can supply PowerPC to call in the data segment of internal memory, the data that need have access to as program.In the suitable moment, triggered by some trigger condition, cause the reconstruct action, by software transfer HWICAP, the part configuration file is converted into hardware circuit.

What deserves to be mentioned is; the foregoing description is an application commonly used of the present utility model; protection domain of the present utility model is not limited to this embodiment; for example; can be three or 4 or more reconfigurable module in actual applications; relate to more multimedia form etc.; also be not limited to the hardware platform in the foregoing description; for example; reconfigurable controller can serve as that (this MCU is independent of above-mentioned FPGA with an independent MCU; and link to each other with FPGA) by bus; and without HWICAP among the embodiment etc.; all in spirit of the present utility model and principle scope, any modification of being done; improve; be equal to replacement etc., all should be included in the protection domain of the present utility model.

Claims

1, a kind of from the reconstruct on-chip multimedia processing system, comprising:

Be used for the operation of whole procedure, the processor of process scheduling (5);

Be used to deposit the program moved and the storer (7) of intermediate value;

Be used for carrying out the on-chip bus (10) of communication between system's each several part,

It is characterized in that, also comprise:

Be connected multimedia processing module (8) on the described on-chip bus, that be used for multi-media signal is carried out coding/decoding, all or part of restructural of this module;

Be connected the reconstruct configuration file reservoir (9) of configuration file on the described on-chip bus, that be used to deposit at least two reconstructed module;

Be connected the reconfigurable controller (6) on the described on-chip bus, described reconfigurable controller (6) is when receiving the reconstruction signal that described processor (5) sends, read appointed configuration file from reconstruct configuration file reservoir (9), write the restructural part (81) of multimedia processing module (8) by described on-chip bus (10).

2, according to claim 1ly it is characterized in that described multimedia processing module (8) comprises fixed part (82) and reconstruct part (81) from the reconstruct on-chip multimedia processing system.

3, according to claim 2ly it is characterized in that from the reconstruct on-chip multimedia processing system described on-chip bus (10) comprises the CORECONNECT bus; Described restructural part (81) is connected by BUS MACRO (83) with signal between the fixed part (82).

4, according to claim 3ly it is characterized in that from the reconstruct on-chip multimedia processing system, described multimedia processing module (8) but comprise the FPGA device of field programming; Area after the each reconstruct of described restructural part (81) on described FPGA is all identical, and the border and the interconnection resource of its shared area immobilize.

5, according to claim 4 from the reconstruct on-chip multimedia processing system, it is characterized in that, described restructural part (81) comprises functional module and IPIF module, described functional module links to each other with the IPIF module, described IPIF module also links to each other with described on-chip bus (10) except that with functional module links to each other.

6, according to claim 5ly it is characterized in that described reconfigurable controller (6) comprises the HWICAP module that is embedded among the FPGA or independent MCU from the reconstruct on-chip multimedia processing system.

7, according to claim 6ly it is characterized in that described HWICAP module writes restructural part (81) by the IPIF module with the reconstruct configuration file content from the reconstruct on-chip multimedia processing system.

8, according to claim 7ly it is characterized in that described HWICAP module writes the reconstruct configuration file content of the configurable logic row of 1bit at every turn from the reconstruct on-chip multimedia processing system.

9, according to each is described from the reconstruct on-chip multimedia processing system among the claim 1-8, it is characterized in that, the multimedia form of described system handles comprise JPEG, JPEG2000, MPEG-2, MPEG-4, H.263, H.264 or among the RM/RMVB one or multinomial.