CN200956590Y

CN200956590Y - Bus type addressing digital public broadcasting device

Info

Publication number: CN200956590Y
Application number: CNU200620017174XU
Authority: CN
Inventors: 曾海波
Original assignee: Individual
Current assignee: Individual
Priority date: 2006-05-26
Filing date: 2006-05-26
Publication date: 2007-10-03
Anticipated expiration: 2016-05-26

Abstract

The utility model discloses a bus-typed addressable digital public broadcasting device; the main radio station uses the PCI radio control card; the signal transmission equipment uses the CAN bus and signal repeaters; the radio terminal includes a decoder and a control part of the CAN connection; the device encodes the audio signal into the digital signal, and does the serial transmission of the signal through the bus of the two lines of the PCI-CAN; the terminal equipment receives, decodes and revives the audio signal; the transmitted signal also includes various necessary terminal control signal. The broadcasting device is a simplified and functionally integrated pure digital public broadcasting device, and can meet the public broadcasting in the large public places.

Description

The digital public broadcasting device of bus-type addressing

Technical field

The utility model relates to a kind of public broadcasting device, the digital public broadcasting device of especially a kind of bus-type addressing.

Background technology

The public broadcasting device mainly is with in public places, as factories and miness, school, military camp, supermarket etc.In the prior art, audio signal (as MIC microphone accepted call signal, sources of sound such as VCD) is amplified in advance by the prime signal, deliver to high power amplifier again and amplify level pressure output, connect loudspeaker, can realize broadcast playback (way of output has two kinds: fixed resistance and level pressure), as shown in Figure 1.

As seen, realize that (background music) play in simple high tone quality public broadcasting has been very ripe framework, but accomplish fixed point or the broadcasting of subregion property, just can't realize based on top broadcasting framework, so the designer has proposed " zonal device ", and successful Application is in the public broadcasting device, as shown in Figure 2.

The public broadcasting device that is constituted as Fig. 2 framework, though can satisfy sectorization broadcast, but accomplish that spot radio is just cumbersome, can only be that a zonal device connects load loudspeaker, and adopt a lot of zonal devices, be worthless from overall cost, and equipment burden, it is big to take up space, and is difficult to adapt to modern small room and places.So public broadcasting device producer has proposed the addressing public broadcasting again, and perfect many other functions, as shown in Figure 3.

By the block diagram of Fig. 3 as can be known, existing ripe digital timing, subregion addressing public broadcasting device, the function that is realized is leading at last, but when running into big demand, big place requires power big, a lot of peripheral equipments such as the high power amplifier etc. of superposeing of just having to, can meet the demands, same so uneconomical, method is inadvisable.

The utility model content

The purpose of this utility model is for a kind of simplification is provided, and the pure digi-tal public broadcasting device that function is integrated can satisfy large-scale public place and realize that public broadcasting plays.

For reaching above purpose, the utility model adopts the PCI-CAN solution, and (PCI is Peripheral Component Interconnection, by the standard that is used to define local bus of Inter company release; CAN is Controller Area Network, controller local area network), realize the digital public broadcasting device of this bus-type addressing, based on data processing function strong multimedia computer platform, utilize the transmission of PCI-CAN bus two lines, its overall architecture is as shown in Figure 4.PCI main website among the figure represents the assembly after PCI broadcast main control card has inserted multimedia computer host PC I groove the inside, and node is represented terminal equipment (the band small-power is amplified decoder and the audio amplifier that absolute address is arranged).The broadcasting main website adopts PCI broadcast main control card, and signal transmission apparatus adopts CAN bus and signal repeater, and broadcast terminal comprises decoder and CAN Communication Control part; This device becomes digital signal with audio-frequency signal coding, transmits by PCI-CAN two-wire system bus serial ports, and is reduced into audio signal by terminal equipment reception and decoding, also contains the terminal control signal of various necessity in the signal that is transmitted.

The PCI broadcast main control card of the digital public broadcasting device of this bus-type addressing comprises microprocessing systems, multipath audio signal input interface, audio frequency gating switch, a/D converter circuit (Analog toDigital Converter, be designated hereinafter simply as ADC), digital signal processing circuit (Digital SignalProcessing, be designated hereinafter simply as DSP), also comprise waveform buffering area RAM (Random AccessMemory, random asccess memory), two-way RAM; Waveform buffering area RAM is located between ADC and the DSP; Audio analog signals is imported from audio input interface, microprocessing systems instruction audio frequency gating switch, audio analog signals delivered to be converted to digital signal among the ADC, digital signal divides hardwood to be input to waveform buffering area RAM to cushion, select one or more Processing Algorithm then, audio digital signals is called in dsp chip inside carry out computing, the audio signal of handling well is sent to each broadcast terminal decoder by the CAN bus, receive the decode reduction by it, and through amplifying output; Or deposit data in two-way RAM buffering.The purpose of utilizing buffering area is to handle in real time, each module is handled simultaneously in the device, part signal is changed in ADC, another part signal is with then carry out algorithm process simultaneously in dsp processor, be that whole device is to carry out work in the mode of streamline, main frame is read up data by two-way RAM, gives upper computer software and handles, as the picture recording storage.

Signal repeater in the CAN bus of the digital public broadcasting device of this bus-type addressing comprises CAN communication interface and signal drive part.The CAN Communication Control part of broadcast terminal is made up of CAN transceiver, CAN protocol controller 2 parts; Decoder comprises microprocessor, and this microprocessor and CAN Communication Control part, digital audio DAC (Digital to Analog Converter, D-A converter), memory, peripheral control unit and volume switch are connected; Digital audio DAC part is converted to simulated audio signal with digital audio and video signals, and this audio output signal is inserted connected power amplifier.

The digital public broadcasting device of bus-type addressing of the present utility model, adopt ripe two-wire system Bus PC I-CAN serial communication solution (widespread usage communicate by letter with the airport etc.), have following characteristics: adopt the network system of this technology to have high stability and reliability to power scheduling; Up to the bus speed of 1Mbps, the high-quality voice signal of system transmissions is become a reality; Can reach the transmission range of 10Km farthest, make remote, large-scale network engineering be able to light realization; Low-cost; Each node has self-test function, can make things convenient for the enforcement of actual engineering and the maintenance in later stage; System can connect 110*n node (more than 10000) in theory, and this makes system have maximum extensibility; Laborsaving repeater easily adds interface, makes system can transmit farther distance; Communication media cheaply, as: twisted-pair feeder, netting twine etc., also can in original twisted-pair wire net (Ethernet) circuit, reequip; Realization easily is connected with fire-fighting system, safety-protection system.As seen, above technical scheme makes the many-sides such as stability, the maintainability in later stage, the system expandability of feasibility, technology maturity, production simplification, engineering wiring of function, performance requirement and product of this system all reach effect as scheduled.

Description of drawings

Fig. 1 is the most basic public broadcasting device block diagram of tradition;

Fig. 2 is the public broadcasting device block diagram of tradition band zonal device;

Fig. 3 is existing addressable public broadcasting device block diagram;

Fig. 4 is the digital public broadcasting device of bus-type addressing of the present utility model overall architecture figure;

Fig. 5 is the terminal equipment hardware capability block diagram of an embodiment of the utility model;

Fig. 6 is the signal repeater hardware block diagram in the CAN bus of an embodiment of the utility model;

Fig. 7 is the PCI broadcast main control card hardware block diagram of an embodiment of the utility model;

Fig. 8 is the hardware connection figure of the A/D circuit chip PCM1800 and device acp chip of an embodiment of the utility model ' C5402 (being TMS320VC5402);

Fig. 9 is the clocked sequential circuit figure of an embodiment of the utility model;

Figure 10 be an embodiment of the utility model PCM1744 with ' the hardware connection figure of C5402.

Embodiment

Below in conjunction with the drawings and specific embodiments the utility model is described in further detail.

As shown in Figure 4, the figure shows the device overall architecture of an embodiment of the utility model, comprise PCI main website 1, CAN bus 2, repeater 3 and a plurality of node 4: the PCI main website 1 expression PCI broadcast main control card among the figure has inserted the assembly behind the multimedia computer host PC I groove the inside, node 4 expression terminal equipments (the band small-power is amplified decoder and the audio amplifier that absolute address is arranged).In the process of transmission, the coding of audio signal can adopt PCM or MP3 coded format; Audio stream is the speed of 128Kbps, can transmit the distance of 1000m; Make full use of the identifier of CAN, each node distributes a message identifier (being equivalent to node address) physically; Node receives only the message and the broadcasting packet of address own, and wherein address message own is a control signal, and broadcasting packet is a digital audio and video signals; Utilize the message filter of CAN, easily discriminating digit audio broadcast signal, digital controlled signal.

Fig. 5 is the terminal equipment hardware capability block diagram of an embodiment of the utility model, and terminal equipment has the decoding function of digital audio and video signals, receives the control signal function that main website sends, and the enlarging function of analogue audio frequency.Wherein CAN Communication Control part 5 is made up of CAN transceiver, CAN protocol controller 2 parts, wherein the CAN transceiver mainly is to be used for driving the CAN signal so that the farther distance of transfer of data, and the CAN protocol controller mainly is to be used for receiving and sending the serial digital signal that meets the CAN standard; The decoder 6 of broadcast terminal comprises microprocessor 7, this microprocessor 7 is the core of this terminal equipment, and inside solidification has control program, data communication encryption and decryption program of setting program, the ancillary equipment of CAN communication driver, audio decoder controlling and driving program, various variable elements etc.; Microprocessor 7 is connected with CAN Communication Control part 5, digital audio DAC 9, memory 11, peripheral control unit 12 and volume switch 13; Power supply changeover device 8 directly is converted into alternating current 220V the needed various direct voltages of terminal equipment; Digital audio DAC 9 parts are converted to simulated audio signal with digital audio and video signals, can be directly with this audio output signal access power amplifier 10; Power amplifier 10 amplifies for the audio frequency small-power, and the way of output is fixed resistance output, and power is optional 10-120W; Memory 11 is EEPROM (Electronic Erasable Programmable Read Only Memory, EEPROM (Electrically Erasable Programmable Read Only Memo)), possessing the function of power down storage data, mainly is the configuration information that is used for preserving terminal equipment, as the group at address, place etc.; Peripheral control unit 12 is mainly some switching circuits, digital volume control circuit etc., is used for control terminal, to realize specific function; Volume switch is controlled the volume intensity of 13 terminal equipments, can be manually control or digital volume potentiometer network control.

Repeater in the CAN bus is very simple, is divided into intelligent repeater and non intelligent repeater: wherein intelligent repeater is for having microprocessor function, but can realize heterogeneous networks interconnectedly have certain delay; Non intelligent repeater is that pure hardware constitutes the signal driving that can only be used for consolidated network, but the more intelligent repeater of speed is fast, and present embodiment adopts non intelligent repeater.Relay amplifier is amplified to suitable amplitude with signal, again to farther circuit transmission.Fig. 6 is the signal repeater hardware block diagram in the CAN bus of an embodiment of the utility model.

Fig. 7 is the PCI broadcast main control card hardware block diagram of an embodiment of the utility model: PCI broadcast main control card comprises microprocessing systems 16, multichannel voice frequency input interface 17, audio frequency gating switch 18, a/D converter circuit (ADC) 19, digital signal processing circuit (DSP) 20, also comprises waveform buffering area RAM 21, two-way RAM 22; Waveform buffering area RAM 21 is located between ADC and the DSP; Audio analog signals is from audio input interface 17 inputs, microprocessing systems 16 instruction audio frequency gating switches 18, audio analog signals delivered to be converted to digital signal among the ADC, digital signal divides hardwood to be input to waveform buffering area RAM 21 to cushion, select one or more Processing Algorithm then, audio digital signals is called in dsp chip inside carry out computing, the audio signal of handling well is sent to the decoder 6 of each broadcast terminal 4 by CAN bus 2, receive the decode reduction by it, and through amplifying output; Or deposit data in two-way RAM 22 bufferings.The purpose of utilizing buffering area is to handle in real time, each module is handled simultaneously in the device, part signal is changed in ADC, another part signal is with then carry out algorithm process simultaneously in dsp processor, be that whole device is to carry out work in the mode of streamline, main frame is read up data by two-way RAM 22, gives upper computer software and handles (as number recording storage).

PCI broadcast main control card has with lower interface: microphone (MIC) input port, AUX (as VCD etc.) the source of sound input port, audio signal input port, digital audio signal decoding output monitor port, the automatic access port of phone (P2 of RJ11 and P3), fire protection warning broadcasting triggers mouth.PCI broadcast main control card also comprises an audio select output circuit, and this circuit is a D/A conversion circuit (seeing for details hereinafter to D/A conversion circuit description partly).

The audio devices of high-fidelity should have the dynamic range of broad, the audio signal that ADC that the present embodiment selection is 16 ~ 24 and DAC could catch or recover high-fidelity fully.The acp chip (DSP) of device selects for use the TMS320VC5402 of American TI Company (to be applicable to that hereinafter to be referred as ' C5402): as 16 fixed-point DSP chip of DSP family high performance-price ratio representative, ' C5402 voice communication etc. embeds the application scenario in real time.' C54X chip the same, ' C5402 has the operability of high flexible and disposal ability at a high speed (can with reference to the related data of American TI Company) with other.

Fig. 8 is the hardware connection figure of the A/D circuit chip PCM1800 and device acp chip of an embodiment of the utility model ' C5402 (being TMS320VC5402): PCM1800 is 20 ADC of dual track monolithic delta sigma type, the power supply of list+5V power supply, signal to noise ratio is 95dB, dynamic range is 95dB, its inside is embedded with high pass filter, have pcm audio interface and four kinds of data formats, be divided into master control and controlled two kinds of patterns, sample frequency is chosen as 32kHz, 44.1KHz and 48KHz.When PCM1800 constitutes the audio signal sample device, be mainly concerned with BCK (bit clock signal), LRCK (sampled clock signal), FSYNC (frame synchronizing signal), DOUT (digital signal output), these several pins that sequential had requirement of SYSCLK (system clock input).By pin MODE0 and MODE1 are programmed, can allow PCM1800 work in master mode (Master Mode).At this moment, BCK, LRCK, FSYNC are all as output, and its sequential produces circuit control by the PCM1800 clock internal.But (use here ' the TOUT pin output signal of C5402 provide) can only be provided by the outside SYSCLK.The system clock of PCM1800 can only be 256fs, 384fs or 512fs, and fs is the sampled audio signal frequency here.When master mode, FSYNC is used for indicating the valid data of the DOUT output of PCM1800, and its rising edge shows the initial of frame data, and trailing edge shows the end of frame data.The frequency of FSYNC is 2 times of sampling clock frequency LRCK.Under this pattern, the frequency of bit clock signal BCK is 64 times of sampling clock frequency LRCK.(FMT0=1, FMT1=0), the data format that PCM1800 output can be set is 20 an IIS form by FMT0, the programming of FMT1 two pins to PCM1800.In order to guarantee not influence the reception of new data when the data processing and when receiving data, do not interrupt ongoing data handling procedure, adopted multichannel buffer synchronous serial interface (McBSP).PCM1800 uses buffered serial port 0 to receive data with ' C5402 be connected after, ' C5402, and various synchronizing signals are produced by PCM1800, ' C5402 is the various information of passive reception.

The D/A conversion circuit of an embodiment of the present utility model (D/A circuit) comprises two parts, and a part is main control card audio select output D/A, and another part is a decoding terminals D/A audio conversion.The PCM1744 that present embodiment adopts is stereophony DAC, comprises digital filter and output amplifier, and dynamic range is 95dB, and it is optional to have multiple sample frequency, reaches as high as 96kHz.Adopt 24 IIS data entry format.The operation of PCM1744 is mainly concerned with LRCIN (sampled clock signal input), BCKIN (bit clock signal input), SCKI (system clock input), these several pins that sequential had requirement of DIN (data input).PCM1744 uses buffered serial port 1 to send data with ' C5402 be connected after, ' C5402, various clock signals by ' C5402 produces the various information of the passive reception of PCM1744.The clock signal of system of PCM1744 (SCKI) has stronger driving force by the timer output signal pin of ' the TOUT pin of C5402 provide, TOUT is ' C5402, can drive a plurality of chips.The data reception clock form of PCM1744 must be the IIS form, ' when C5402 is provided with various clock mode in the buffered serial port register, must satisfy the requirement of IIS form.' C5402 is as the active device work, can adjust its buffered serial port output signal.Sampled clock signal, the bit clock signal of output can be provided with in McBSP register SRGR1 and SRGR2, are provided with as shown in Figure 9.

Basic clock signal can be from cpu clock, also can be from the crystal oscillator clock, and this 13rd setting in the SRGR2 register.After the fundamental clock input, carry out frequency division first time, obtain bit clock signal (exporting) by the BCLKX1 pin through the set value of CLKGDV (SRGR1 the 7th to the 0th).It should be noted that bit clock signal is up to half of DSP frequency.Bit clock signal obtains sampled clock signal (by the output of BFSX1 pin) through the set further frequency division of value of FPER (SRGR2 the 11st to the 0th) and FWID (SRGR1 the 15th to the 8th), and FPER and FWID are provided with the low level of sampled clock signal and the time value of high level respectively.

' C5402 and PCM1744 hardware connection as shown in figure 10.After PCM1800 finishes audio signal sample, embed corresponding Processing Algorithm in the program storage extending out of DSP, voice signal is exported from PCM1744 after treatment again.

In this device, existing A/D has D/A again, constitutes a closed loop, but internal loopback; And algorithm concentrates on and carries out modularization in the dsp chip and handle, and this has brought very big convenience for Design of device and debugging.

Claims

1, the digital public broadcasting device of a kind of bus-type addressing, comprise broadcasting main website, signal transmission apparatus and broadcast terminal, it is characterized in that: the main control card of described broadcasting main website is a PCI broadcast main control card, signal transmission apparatus is CAN bus and signal repeater, and broadcast terminal comprises decoder and CAN Communication Control part; This device is by the transmission of PCI-CAN two-wire system bus serial ports, and receive and decoding is reduced into audio signal by terminal equipment, described PCI broadcast main control card comprises microprocessing systems, multichannel voice frequency input interface, audio frequency gating switch, a/D converter circuit, digital signal processing circuit.

2, the digital public broadcasting device of bus-type addressing according to claim 1, it is characterized in that: described PCI broadcast main control card also comprises the audio select output circuit, this circuit is a D/A conversion circuit.

3, the digital public broadcasting device of bus-type addressing according to claim 1, it is characterized in that: the signal repeater in the described CAN bus comprises CAN communication interface and signal drive part.

4, the digital public broadcasting device of bus-type addressing according to claim 1, it is characterized in that: the CAN Communication Control part of described broadcast terminal is made up of CAN transceiver, CAN protocol controller 2 parts, wherein the CAN transceiver drives the CAN signal so that the farther distance of transfer of data, and the CAN protocol controller receives and send the serial digital signal that meets the CAN standard.