CN200941625Y - FRU regulation and test apparatus based on ATCA rack - Google Patents
FRU regulation and test apparatus based on ATCA rack Download PDFInfo
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- CN200941625Y CN200941625Y CN 200620044439 CN200620044439U CN200941625Y CN 200941625 Y CN200941625 Y CN 200941625Y CN 200620044439 CN200620044439 CN 200620044439 CN 200620044439 U CN200620044439 U CN 200620044439U CN 200941625 Y CN200941625 Y CN 200941625Y
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Abstract
A FRU debugging and testing device based on ATCA frame, which comprises a main digital processor, a slave digital processor and a upper computer; the slave digital processor is used to collect IPMB1 data, and sends the data to the main digital processor; the main digital processor is used to receive site debugging order, and receives the IPMB1 data from slave digital processor; the main digital processor collects hardware address information through I/O port, and collect IPMB0 data through USI port, then send the collected IPMB0 data and the IPMB1 data from the slave digital processor to the upper computer. The upper computer is used to send the debugging order to the main digital processor, receives and analyses the IPMB0 and IPMB1 data transmitted by the main digital processor. The utility model makes the site operation FRU test or IPMC debugging become directly observable and convenient, the IPMB bus data receipt and analysis can be accomplished on the human-machine interface, and explains the whole datagram content according to user content.
Description
Technical field
The utility model belongs to advanced telecom counting system technical field of structures, particularly a kind of field replacement unit (FieldReplaceable Units, debugging FRU) and testing apparatus.
Background technology
At present, Ling Xian telecom equipment manufacturers and operator are supporting an architecture brand-new, open system in the industry, (Advanced Telecom Computing Architecture is called for short AdvancedTCA, ATCA) to advanced telecom counting system structure.ATCA has issued integrated circuit board, base plate and the software specifications that is used for telecommunication apparatus of future generation: the PICMG3.0 standard.It is by a core specification--and PICMG3.0 and a series of auxiliary standard are formed.Core specification in the ATCA family has defined mechanism, power supply, heat radiation, interconnected, the system management part in the ATCA series of canonical; Auxiliary normative content has then defined transmission means interconnected in core specification.
ATCA mainly is a hardware specification, and its platform structure as shown in Figure 1.Shelf Management Controller among the figure (ShMC) is responsible for finishing the management to the field replacement unit in the ACTA system such as veneer, power supply, fan, temperature sensor.IPMC is an intelligent platform management controller, mainly be positioned on the ATCA frame each on the physical space above the FRU, on each FRU on the ATCA frame IPMC controller is arranged all at present, these IPMC controllers are by two two redundant Intelligent Platform Management Bus (Intelligent Platform Management Bus, IPMB) and ShMC communicate, thereby realize the various management of IPMC to FRU.Platform cooling system (Fan Tray) is responsible for system radiating.Power board (Hub) is responsible for platform data exchange and exchange control.Business board (Node) then is responsible for system's control, applied business carrying and the software support etc. of platform.
Stipulate according to PICMG3.0, (Inter-Integrated Circuit is called for short I2C to IPMB, and this agreement is that Philips company puts forward the earliest based on the I2C bus protocol, the I2C agreement adopts two all apparatus interconnections of bundle of lines to get up, and these two lines are respectively data wire SDA and clock line SCL.According to I2C V2.1 standard code, the bus maximum drive ability of I2C is 400PF, and transmission rate reaches as high as 3.4Mbps, adopts 7 bit address addressing modes, and multipotency is realized 128 apparatus interconnections.), IPMC on each FRU on the ATCA frame must be equipped with the I2C interface, IPMC equipment has the I2C device address of oneself as the equipment on the I2C bus, can accept on the I2C bus the to one's name data message of (address) or broadcast address during as slave unit, and can respond it by analyzing; Certainly also can on bus, give other device transmission messages during as main equipment.
IPMB bus structures between IPMC and the ShMC generally are divided into bus-type (Bused) and star-like (Radial) two kinds.For bus-type ATCA frame, the data message that transmits on the IPMB bus whenever, IPMC all on the bus can both receive, are addressed to but at most only have an equipment, and respond.Whenever because I2C V2.1 agreement regulation, the address of the equipment on the I2C bus must be unique, can be addressed to so at most only have an equipment on the bus.
For telecom operators, if it is on-the-spot in operation, break down in FRU operation and the test process on the ATCA frame, because have a plurality of FRUs at the same time to move on the frame this moment, failure cause just exists much may, also unclear specifically is which FRU breaks down, if therefore just be not difficult to get rid of these faults by measuring equipment of special use (such as oscilloscope etc.) or special-purpose debugging acid (such as simulator).
For telecom equipment manufacturers, on the ATCA frame, when debugging or test FRU and IPMC, also there is same problem based on the ATCA framework.Because there are a plurality of FRU to move at the same time on the frame, this moment the whole system resource, comprise that power supply, management/data bus bandwidth etc. all are shared, if some problems in the analysis debug process, do not consider global resource, the situation of utilizing such as DC power supply power (IPMC need consult application with ShMC), IPMB bus (all IPMC and ShMC are shared) etc. also can make the debugging of IPMC or FRU and test become very difficult.
Very great at present equipment manufacturers, released the product of the Management Controller aspect under a lot of ATCA frameworks such as companies such as Intel, PigeonPoint, such as the AdvancedTCA IPM Controller of PigeonPoint company and ATCAManagement Exerciser Board, Management Controllers such as AdvancedMC Module Management Controller, CompactPCI IPMController.But on the problem that the FRU based on the ATCA frame debugs and tests, good solution and product are not arranged also.
The utility model content
At the problems referred to above, the utility model provides a kind of FRU debugging and testing apparatus based on the ATCA frame, by the data communication process on IPMB monitors to part or all of FRU and ShMC, with convenient on-the-spot operation test FRU or debugging test I PMC.
For reaching above-mentioned purpose, the utility model adopts following technical scheme:
A kind of FRU debugging and testing apparatus based on the ATCA frame, comprise main digital processing unit, from digital processing unit and host computer, described main digital processing unit and include a start bit observation circuit, stop bits observation circuit and one from digital processing unit and be used for simultaneously prolonging and descending and prolong the counter of counting to SCL
Describedly be used to gather data on the IPMB1, and send it to main digital processing unit from digital processing unit,
Described main digital processing unit is used to accept the field adjustable order, the data of reception from the IPMB1 of digital processing unit transmission, by its I/O mouth acquisition hardware address information, and by the data on its USI mouth collection IPMB0, again the data on the IPMB0 of its collection are reached the IPMB1 that transmits from digital processing unit and be sent to upper PC
Described host computer is used for sending described debug command to main digital processing unit, and accept and resolve on the described IPMB0 that main digital processing unit sends with IPMB1 on data.
As a kind of improvement of the present utility model, described main digital processing unit and be respectively equipped with SPI mouth (SerialPerpherial Interface, Serial Peripheral Interface (SPI)) from digital processing unit, described master and slave digital processing unit communicates by the SPI mouth.
Wherein, described main digital processing unit is provided with UART mouth (The Universal Asynchronous serial Receiverand Transmitter), communicates by letter with host computer by described UART mouth.
As another improvement of the present utility model, comprise that also (Zone1 has defined the address signal of IPMC to a Zone1 connector, the clock of IPMB bus and data-signal, defined two-way 48V dc power signal etc.) and a power transfer module, described main digital processing unit be connected with the Zone1 connector from digital processing unit, described Zone1 connector is used for the power taking of slave back-propping plate and obtains the IPMB bus data line and clock line and groove bit address information, described power transfer module is used to change the voltage that described Zone1 connector slave back-propping plate is obtained, and is respectively main digital processing unit and powers from digital processing unit.
One improve again as of the present utility model, also comprise two LED light that are connected with described main digital processing unit, be respectively applied for indication IPMB0 and IPMB1 bus and whether be in user mode.
One improve again as of the present utility model, also comprise two I2C buffers, described master and slave digital processing unit is provided with the USI interface, behind the IPMB0 of described collection and the process of the data on the IPMB1 I2C buffer, transfers to master and slave digital processing unit respectively by the USI interface.
One improve again as of the present utility model, also comprise a reset button that is connected with main digital processing unit reset pin.
One improve as of the present utility model, described reset pin from digital processing unit is connected with main digital processing unit again.Promptly finish by main digital processing unit from resetting of digital processing unit.
The utility model makes on-the-spot operation test FRU or debugging test I PMC become very directly perceived and convenient, can finish the acceptance and the parsing of IPMB bus data in the man-machine interface of host computer, and explain whole datagram content according to user content.Make test and research staff can make things convenient for, finish efficiently test and debugging to IPMC or FRU.
Description of drawings
Fig. 1 is existing ATCA platform structure schematic diagram;
Fig. 2 is FRU debugging and the testing apparatus embodiment schematic diagram of the utility model based on the ATCA frame;
Fig. 3 is the typical sequential chart of an activity on the bus under the I2C agreement.
Fig. 4 is the utility model embodiment based on master and slave digital processing unit SPI communication interface schematic diagram in the FRU debugging of ATCA frame and the testing apparatus.
Embodiment
As shown in Figure 2, a kind of FRU debugging and testing apparatus based on the ATCA frame, comprise main digital processing unit, from digital processing unit, host computer, (Zone1 has defined the address signal of IPMC to Zone1, the clock of IPMB bus and data-signal, defined two-way 48V dc power signal etc.) connector, with a power transfer module, two LED light, wherein, described main digital processing unit and from digital processing unit include one (Start) position observation circuit, an end (Stop) position observation circuit and one are used for prolonging the counter of counting to prolonging on the SCL and descending simultaneously; Described main digital processing unit be connected with the Zone1 connector from digital processing unit; Described Zone1 connector is used for the power taking of slave back-propping plate, and obtain IPMB bus data line and clock line and groove bit address information etc., described power transfer module is used to change the voltage that described Zone1 connector slave back-propping plate is obtained, and be respectively main digital processing unit and from digital processing unit power supply (for direct current-48V is converted to direct current 3.3V, power is 10W the present embodiment).Among Fig. 2, pin EARLY_A and-difference of 48V A is the sample different in size of pin, the EARLY_A pin-48V A pin is longer, so when FRU inserted ATCA frame backboard, EARLY_A will power on earlier, can pass through the pre-power taking of EARLY_A.Described two LED light are connected with described main digital processing unit, are used for indicating respectively IPMB0 and IPMB1 bus whether to be in user mode.
Describedly be used to gather data on the IPMB1, and send it to main digital processing unit from digital processing unit,
Described main digital processing unit is used to accept the field adjustable order, the data of reception from the IPMB1 of digital processing unit transmission, by its I/O mouth acquisition hardware address information, and by the data on its USI mouth collection IPMB0, again the data on the IPMB0 of its collection are reached the IPMB1 that transmits from digital processing unit and be sent to upper PC
Described host computer is used for sending described debug command to main digital processing unit, and accept and resolve on the described IPMB0 that main digital processing unit sends with IPMB1 on data.
Wherein, described master and slave digital processing unit can adopt 8 RISC Atmega169 of the low-power consumption family chip that has USI interface (USB (universal serial bus)) of Atmel company.Host computer can be one to have the PC or the notebook computer of RS232 interface.The IPMB bus detects and finishes by the USI interface of RISC Atmega169, and this USI interface is as the slave unit on the IPMB; But the addressing of USI interface is to adopt software control fully, all Frames on can controlling bus, and do not influence the proper communication of other I2C equipment on the bus.
Wherein, described main digital processing unit is provided with the UART mouth, communicates by letter with host computer by this mouth of described UART.
Wherein, described main digital processing unit and also be respectively equipped with the SPI mouth from digital processing unit, describedly data on the IPMB1 that collects are sent to described main digital processing unit by the SPI mouth, after described main digital processing unit is accepted and handled these data, send it to host computer from main digital processing unit.Described main digital processing unit and as shown in Figure 4 from the connected mode of the SPI mouth of digital processing unit.Main digital processing unit and be full-duplex communication from the communication between the digital processing unit, among Fig. 4, SCK is a clock line, mainly produces (when needing transmission, by internal firmware program running clocking) by main equipment; MOSI (Master Out and SlaveIn) line is the data wire of main frame dateout to slave; MISO (Master In and Slave Out) line is the data wire of slave dateout to main frame; SS (Slave Select) is that slave is selected signal, is mainly used in main many communications under mode.Also have two lines to receive respectively on the external interrupt INTO pin of principal and subordinate processor in addition, mainly be as the handshake in the communication (such as from the transmission request of processor and the transmission notice of primary processor), in addition in order to improve the communication benefit, principal and subordinate processor all will interrupt transmit leg after accepting to finish, accept to finish with expression, so that transmit leg can continue to give a number, this all finishes by these two lines.
In addition, when guaranteeing that on the ATCA frame our this device carried out hot plug, can not produce too much influence to other I2C devices communicatings on the IPMB bus, further, two I2C buffers that also comprise, described master and slave digital processing unit is provided with the USI interface, described two I2C buffers are located at respectively between the USI mouth of IPMB and master and slave digital processing unit, behind the IPMB0 of described collection and the process of the data on the IPMB1 I2C buffer, transfer to master and slave digital processing unit respectively by the USI interface.Wherein, the I2C buffer can adopt the LTC4300-1 of Linear company, the rise time effect that the main signal saltus step that plays on the acceleration I2C bus is prolonged, reach the maximum drive ability (in the PICMG3.0 standard this value being increased to 900pF) of the 400pF that requires in the I2C standard, the I2C bus is two lines altogether, one is data wire (SDA), and one is clock line (SCL), is connected respectively on the data wire and clock line of USI of digital processing unit.
Wherein, also comprise a reset button that is connected with main digital processing unit reset pin, described reset pin from digital processing unit is connected with main digital processing unit.Promptly finish by main digital processing unit from resetting of digital processing unit.
The above-mentioned FRU debugging and the testing apparatus course of work based on the ATCA frame is as follows:
1, the IPMB bus data reads
Host computer disposes and controls the USI mouth of master and slave digital processing unit, make it become TWI (Two Wire Interface, two line interfaces) pattern, and be modeled to the I2C bus slave, read all data on IPMB0 and the IPMB1 bus respectively, and the data that receive are put into circle queue in order.
According to the I2C agreement, any activity on the bus all is to begin with a Start initial signal, with the Stop signal ended.The centre is a Frame, and first 9bit data are 7bit address, the read-write direction position of 1bit and ack/nack signal of 1bit, and ensuing basis is specifically used difference, and the length of the Frame of transmission also is not quite similar.Its typical sequential chart as shown in Figure 3.
The USI mouth of digital processing unit has plenty hardware resources, such as having a start bit Start position observation circuit, Stop position observation circuit and energy to count simultaneously and the 4Bit counter that overflows interrupt function arranged prolonging on the SCL and descending to prolonging.The USI mouth that we can the configurable number word processor is so realized two line interfaces of the I2C interface of our needed compatible with Philips by the software assistance, i.e. a clock line SCL and a data lines SDA.We overflow interruption by monitoring Start position interruption, the interruption of Stop position, counter.Come the data on the bus are monitored, read all data on the IPMB0/IPMB1 bus, and pass to upper PC by the UART serial ports with this.
2, from the digital processing unit data upload
By the SPI mouth IPMB1 data that it reads are sent to main digital processing unit from digital processing unit.
The SPI interface schema of main equipment and slave unit is connected in the following way, adopts half-duplex real time communication mode.
Itself be to support full-duplex communication on the SPI hardware, and the clock of receiving and sending out is synchronous, promptly starts once transmission and can finish the main equipment data and move into slave unit that the data that can finish slave unit simultaneously move into main equipment.But used herein is half-duplex, i.e. synchronization can only have the transfer of data of an aspect.Here Chuan Shu data unit is the transmission of carrying out according to byte, and the data of transmission are organized by message.
3, master/slave digital processing unit data upload
Main digital processing unit monitors an IPMB0, monitors IPMB1 from digital processing unit, after slave unit monitors the data of IPMB1, gives main equipment by the SPI oral instructions, directly is dealt into serial ports by main equipment then.After if main equipment monitors the data of IPMB0, directly be dealt into serial ports.According to the PICMG regulation, on these two buses data can not be arranged simultaneously.
4, resolve the IPMB message
Packet parsing is that host computer is according to the IPMI protocol analysis at present.The man-machine interface of host computer, can adopt the Visaual C++6.0 of company of Microsoft (Micrsoft) to work out, the whole procedure resource mainly is made up of two threads and an interrupt service routine, and one is the working interface thread, and another is to show IPMB data thread.To finish the parsing and the storage of the IPMB message that host computer is read from the serial ports of IPMB bus monitoring controller.
By IPMB bus monitoring controller to the parsing of the collection of the message on the Bused IPMB and host computer to message, the user can be clearly seen that all active situation on the bus, comprise the overall negotiation process of all IPMC with ShMC, and it is various unusual on-the-spot, certainly, also can be targetedly the FRU of particular address be monitored.Like this, the FRU in the debug process power on and power process can monitor; Power on finish after, the FRU running status also can be monitored, and can also debug in conjunction with the ClI of ShMC, thereby makes the debugging of FRU promptly simple, the convenient very economical again that becomes, and can quick and accurate orientation problem.
Claims (8)
1, a kind of FRU debugging and testing apparatus based on the ATCA frame, it is characterized in that: comprise main digital processing unit, from digital processing unit and host computer, described main digital processing unit and include a start bit observation circuit from digital processing unit, stop bits observation circuit and one are used for prolonging the counter of counting to prolonging on the SCL and descending simultaneously, describedly be used to gather data on the IPMB1 from digital processing unit, and send it to main digital processing unit, described main digital processing unit is used to accept the field adjustable order, the data of reception from the IPMB1 of digital processing unit transmission, by its I/O mouth acquisition hardware address information, and by the data on its USI mouth collection IPMB0, again the data on the IPMB0 of its collection are reached the IPMB1 that transmits from digital processing unit and be sent to upper PC
Described host computer is used for sending described debug command to main digital processing unit, and accept and resolve on the described IPMB0 that main digital processing unit sends with IPMB1 on data.
2, a kind of FRU debugging and testing apparatus based on the ATCA frame according to claim 1 is characterized in that: described main digital processing unit and be respectively equipped with the SPI mouth from digital processing unit, described master and slave digital processing unit communicates by the SPI mouth.
3, a kind of FRU debugging and testing apparatus based on the ATCA frame according to claim 1, it is characterized in that: described main digital processing unit is provided with the UART mouth, communicates by letter with host computer by described UART mouth.
4, a kind of FRU debugging and testing apparatus according to claim 1 and 2 based on the ATCA frame, it is characterized in that: also comprise a Zone1 connector and a power transfer module, described main digital processing unit be connected with the Zone1 connector from digital processing unit, described Zone1 connector is used for the power taking of slave back-propping plate and obtains the IPMB bus data line and clock line and groove bit address information, described power transfer module is used to change the voltage that described Zone1 connector slave back-propping plate is obtained, and is respectively main digital processing unit and powers from digital processing unit.
5, a kind of FRU debugging and testing apparatus according to claim 1 and 2 based on the ATCA frame, it is characterized in that: also comprise two LED light that are connected with described main digital processing unit, be respectively applied for indication IPMB0 and IPMB1 bus and whether be in user mode.
6, a kind of FRU debugging and testing apparatus according to claim 1 and 2 based on the ATCA frame, it is characterized in that: also comprise two I2C buffers, described master and slave digital processing unit is provided with the USI interface, behind the IPMB0 of described collection and the process of the data on the IPMB1 I2C buffer, transfer to master and slave digital processing unit respectively by the USI interface.
7, a kind of FRU debugging and testing apparatus based on the ATCA frame according to claim 1 and 2 is characterized in that: also comprise a reset button that is connected with main digital processing unit reset pin.
8, a kind of FRU debugging and testing apparatus based on the ATCA frame according to claim 7, it is characterized in that: described reset pin from digital processing unit is connected with main digital processing unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200620044439 CN200941625Y (en) | 2006-08-01 | 2006-08-01 | FRU regulation and test apparatus based on ATCA rack |
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| CN 200620044439 CN200941625Y (en) | 2006-08-01 | 2006-08-01 | FRU regulation and test apparatus based on ATCA rack |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119224B (en) * | 2006-08-01 | 2010-08-18 | 上海未来宽带技术及应用工程研究中心有限公司 | ATCA frame based FRU debugging and testing device |
| CN102375769A (en) * | 2010-08-26 | 2012-03-14 | 鸿富锦精密工业（深圳）有限公司 | Test integrity control system and method |
| WO2017092184A1 (en) * | 2015-12-03 | 2017-06-08 | 英业达科技有限公司 | Fru read/write method and read/write system |
-
2006
- 2006-08-01 CN CN 200620044439 patent/CN200941625Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119224B (en) * | 2006-08-01 | 2010-08-18 | 上海未来宽带技术及应用工程研究中心有限公司 | ATCA frame based FRU debugging and testing device |
| CN102375769A (en) * | 2010-08-26 | 2012-03-14 | 鸿富锦精密工业（深圳）有限公司 | Test integrity control system and method |
| CN102375769B (en) * | 2010-08-26 | 2016-12-28 | 罗普特（厦门）科技集团有限公司 | Test completeness control system and method |
| WO2017092184A1 (en) * | 2015-12-03 | 2017-06-08 | 英业达科技有限公司 | Fru read/write method and read/write system |
| US10877744B2 (en) | 2015-12-03 | 2020-12-29 | Inventec (Pudong) Technology Corporation | Read/write method and read/write system for FRU |
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