CN1996488A - Memory structure and its writing method - Google Patents
Memory structure and its writing method Download PDFInfo
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- CN1996488A CN1996488A CN 200510137653 CN200510137653A CN1996488A CN 1996488 A CN1996488 A CN 1996488A CN 200510137653 CN200510137653 CN 200510137653 CN 200510137653 A CN200510137653 A CN 200510137653A CN 1996488 A CN1996488 A CN 1996488A
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Abstract
A storage structure and its writing comprises a power circuit and bridge circuit, driving the bridge circuit through the power circuit to generate several connected model, with the storage unit using only one set of power circuit, free from predicting its resistance value, hard to generate faulty signal while the storage structure switching positively or negatively.
Description
Technical field
The present invention relates to a kind of memory construction and wiring method thereof, more specifically, it relates to and is used for non-volatile magnetic RAM (Magnetic Random Access Memory, memory construction MRAM) and wiring method thereof.
Background technology
Non-volatile magnetic RAM (Magnetic Random Access Memory, MRAM) wiring method is the unit that utilizes two electric current lines (Bit Line and Write Word Line) induced magnetism place to occur simultaneously and select, the direction of magnetization of the magnetic material by changing this memory layer, in order to change its magnetoelectricity resistance, and when reading its data memory, by the magnetic mnemon inflow current of selecting, by the resistance value that is read to judge the digital value of its data memory.
Usually, as No. 583666 disclosed method that is used to change a magnetoresistive memory device of China's patent announcement, it provides a magnetoresistive memory assembly that closes on one first conductor and one second conductor, wherein, this magnetoresistive memory assembly comprises one first sector and one second sector, by a tunnel barriers separately, at least the one of this first and second sector comprises N strong magnetic material layer, this N strong magnetic material layer is non-ferromagnetism coupling, wherein N equals an integer of two at least, and wherein every layer has an adjusting magnetic moment to provide one to write pattern, and each this first sector and second sector have the magnetic moment of closing on this tunnel barriers, and it is positioned a preferred direction in a time t0; Connect one first electric current that passes this first conductor at a time t1; Connect one second electric current that passes this second conductor at a time t2; Cut off this first electric current that passes this first conductor at a time t3; And cut off this second electric current pass this second conductor at a time t4, and making that of the magnetic moment of closing on this tunnel barriers is positioned a direction, they are different with initial preferred direction when the time t0.
Usually the magnetoresistive memory device of usefulness is to adopt to fasten button-type and write pattern (Toggle Mode), in order to improving the write selectivity of this magnetoresistive memory, thereby makes this magnetoresistive memory can be near the stage of mass production.See also shown in Figure 14 A to 14E, for the sequential of the common embodiment of the magnetoresistive memory device of usefulness and write pattern diagram, this magnetoresistive memory device is to be used in magnetic field to apply a character electric current 30 and a digital current 40, makes effective magnetic moment Rotate 180 ° of this magnetoresistive memory device in order to cause a magnetic fluxes.Yet, owing to expose the interference in magnetic field, often make this magnetoresistive memory device when the t0 inceptive direction, be deflected, and cause writing easy mistake, therefore, in the disclosed magnetoresistive memory device of above-mentioned patent, be before writing, to utilize a negative current to flow through, and make this magnetoresistive memory can deflection return correct initial position at the t0 inceptive direction, expose the influence of magnetic interference with solution, thereby and increase and write accuracy.
Though advantages such as non-volatile, highly dense intensity that this magnetoresistive memory has, high read or write speed, radioresistance line, but, need the bigger magnetic field that writes, therefore owing to fasten the special pattern that writes of button-type, easily cause write current excessive, increase the degree of difficulty of using with the peripherals collocation.Yet, though can reduce its write current by the method that a magnetoresistive memory device is changed in above-mentioned being used to, and the rate that correctly writes that increases magnetoresistive memory, the positive and negative problem that is faced for relevant research staff to electric current in this method how to be produced.
Therefore, how to develop a kind of simple in structure, have fixed current and can produce positive and negative memory construction to electric current, be this required problem that urgently faces in relevant research and development field really.
Summary of the invention
In view of the shortcoming of above-mentioned known technology, fundamental purpose of the present invention is to provide a kind of memory construction and wiring method thereof, makes it simple in structure, only need use one group of power circuit.
Another object of the present invention is to a kind of memory construction and wiring method thereof that provides positive and negative to pulse.
Another object of the present invention is to provide a kind of memory construction and wiring method thereof, make its resistance that does not need to know in advance its bit line, can utilize power circuit to produce required current value.
Reach other relevant purpose in order to achieve the above object, the invention provides a kind of memory construction and wiring method thereof, be to comprise that one has the power circuit and a bridge circuit that is electrically connected with this power circuit of input end and output terminal, this bridge circuit is to have one first switch member, a second switch spare, one the 3rd switch member and one the 4th switch member, thereby forms quarter-phase circuit.
Memory construction of the present invention is to drive a bridge circuit by a power circuit, and in order to produce a plurality of conduction modes, this conduction mode comprises:
When this first switch member and the 3rd switch member are conducting (ON), this second switch spare and the 4th switch member are when disconnecting (OFF), the electric current of this input end output flows to this resistor assembly via this first switch member, to produce one first pulse, flow to this output terminal via the 3rd switch member again;
When this second switch spare and the 4th switch member are conducting, when this first switch member and the 3rd switch member are disconnection, the electric current of this input end output flows to this resistor assembly via this second switch spare, to produce one second pulse, flow to this output terminal via the 4th switch member again; And
When this first switch member, this second switch spare, the 3rd switch member and the 4th switch member when disconnecting, therefore the electric current that this input end is exported arbitrary switch member of not flowing through produces one the 3rd pulse.
Full bridge circuit of the present invention is the transmission lock (Transimission Gate) that can be made up of two P channel field effect transistors and two N channel field effect transistors or P channel field effect transistors and N channel field effect transistors, or P channel field effect transistors, all permutation and combination of N channel field effect transistors and transmission lock are formed, form a positive half cycle driving and a negative half period driving by this P channel field effect transistors and this N channel field effect transistors, and can be by the different qualities of this P channel field effect transistors and this N channel field effect transistors, make this memory construction when positive negative sense switches, be difficult for producing signal error, and this memory construction is simple in structure, only need use one group of power circuit, and do not need to know in advance the resistance of its bit line, also can utilize this power circuit to produce required current value, easy and its other peripherals collocation is used.
Description of drawings
Fig. 1 is the structural representation of memory construction of the present invention;
Fig. 2 A to 2C is the structural representation of the different conduction modes of memory construction of the present invention;
Fig. 3 is the conducting waveform synoptic diagram of memory construction of the present invention;
Fig. 4 A is the structural representation of first embodiment of memory construction of the present invention;
Fig. 4 B is the analog waveform synoptic diagram of first embodiment of memory construction of the present invention;
Fig. 5 A is the structural representation of second embodiment of memory construction of the present invention;
Fig. 5 B is the analog waveform synoptic diagram of second embodiment of memory construction of the present invention;
Fig. 6 A is the structural representation of the 3rd embodiment of memory construction of the present invention;
Fig. 6 B is the analog waveform synoptic diagram of the 3rd embodiment of memory construction of the present invention;
Fig. 7 A is the structural representation of the 4th embodiment of memory construction of the present invention;
Fig. 7 B is the analog waveform synoptic diagram of the 4th embodiment of memory construction of the present invention;
Fig. 8 A is the structural representation of the 5th embodiment of memory construction of the present invention;
Fig. 8 B is the analog waveform synoptic diagram of the 5th embodiment of memory construction of the present invention;
Fig. 9 A is the structural representation of the 6th embodiment of memory construction of the present invention;
Fig. 9 B is the analog waveform synoptic diagram of the 6th embodiment of memory construction of the present invention;
Figure 10 A is the structural representation of the 7th embodiment of memory construction of the present invention;
Figure 10 B is the analog waveform synoptic diagram of the 7th embodiment of memory construction of the present invention;
Figure 11 A is the structural representation of the 8th embodiment of memory construction of the present invention;
Figure 11 B is the analog waveform synoptic diagram of the 8th embodiment of memory construction of the present invention;
Figure 12 A is the structural representation of the 9th embodiment of memory construction of the present invention;
Figure 12 B is the analog waveform synoptic diagram of the 9th embodiment of memory construction of the present invention;
Figure 13 A is the structural representation of the tenth embodiment of memory construction of the present invention;
Figure 13 B is the analog waveform synoptic diagram of the tenth embodiment of memory construction of the present invention;
Figure 14 A is the sequential synoptic diagram of embodiment of the magnetoresistive memory device of common usefulness; And
Figure 14 B to 14E be common usefulness magnetoresistive memory device embodiment write pattern diagram.
The simple declaration of Reference numeral
10 power circuits
11 input ends
12 output terminals
13 first control signals
14 second control signals
20 bridge circuits
21 first switch member
22 second switch spares
23 the 3rd switch member
24 the 4th switch member
25 resistor assemblies
251 resistance
26 electric currents
261 first pulses
262 second pulses
263 the 3rd pulses
30 character electric currents
40 digit current
Embodiment
Below be that those of ordinary skill in the art can understand other advantage of the present invention and effect easily by the disclosed content of this instructions by specific instantiation explanation embodiments of the present invention.The present invention also can be implemented or be used by other different instantiation, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
See also shown in Figure 1ly, be the structural representation of memory construction of the present invention.As shown in the figure, memory construction of the present invention is to comprise a power circuit 10 and a bridge circuit 20, driving by this power circuit 10, in order to produce a plurality of conduction modes, this power circuit 10 has input end 11 and output terminal 12, and this bridge circuit 20 includes first switch member 21, second switch spare 22, the 3rd switch member 23 and the 4th switch member 24, thereby formation quarter-phase circuit, the two-phase docking point of this bridge circuit is to be connected with this input end 11 and this output terminal 12, and the two-phase docking point in addition of this bridge circuit is the current lead-through path.
See also shown in Fig. 2 A to 3, be the structure and the conducting waveform synoptic diagram thereof of the different conduction modes of memory construction of the present invention.As shown in the figure, memory construction of the present invention is to produce an electric current by this power circuit 10, in order to driving this bridge circuit 20, thereby produces a plurality of conduction modes.
Shown in Fig. 2 A, when this first switch member 21 and the 3rd switch member 23 are conducting, when this second switch spare 22 and the 4th switch member 24 are disconnection, input end 11 outputs one electric current 26 of this power circuit 10, this electric current 26 flows to this resistor assembly 25 via this first switch member 21, produce a basipetal electric current in this resistor assembly 25 (being also referred to as bit line (BitLine)), promptly be referred to as first pulse 261, this first pulse 261 also is positive pulse (Positive Pulse), flow to the output terminal 12 of this power circuit 10 again via the 3rd switch member 23.
Shown in Fig. 2 B, when this second switch spare 22 and the 4th switch member 24 are conducting, when this first switch member 21 and the 3rd switch member 23 are disconnection, input end 11 outputs one electric current 26 of this power circuit 10, this electric current 26 flows to this resistor assembly 25 via this second switch spare 22, in this resistor assembly 25 (also being bit line) generation one electric current from lower to upper, promptly be referred to as second pulse 262, this second pulse 262 also is negative pulse (Negative Pulse), flow to the output terminal 12 of this power circuit 10 again via the 4th switch member 24.
Shown in Fig. 2 C, when this first switch member 21, this second switch spare 22, the 3rd switch member 23 and the 4th switch member 24 are disconnection, the electric current 26 that the input end 11 of this power circuit 10 the is exported bit line (also being this resistor assembly 25) of not flowing through, therefore produce one the 3rd pulse, 263, the three pulses 263 for sharing pulse (Common Pulse).
In addition, memory construction of the present invention can be selected in response to actual demand to change, and sees also shown in Fig. 4 A to 6B, is the structure and the conducting waveform synoptic diagram thereof of the different embodiments of memory construction of the present invention.
Shown in Fig. 4 A to 4B, structure and simulation waveform synoptic diagram thereof for first embodiment of memory construction of the present invention, this switch member is made up of the transmission lock that P channel field effect transistors and N channel field effect transistors are made up, first switch member 21 of this full bridge circuit, the 3rd switch member 23,24 of second switch spare 22 and the 4th switch member are shared one first control signal (V_Ctrl_B) 13 and one second control signal (V_Ctrl) 14, when this memory construction when positive negative sense switches, because this full bridge circuit uses the first above-mentioned control signal and second control signal respectively, can adjust this first control signal and this second control signal respectively, to avoid this memory construction to produce positive negative sense handoff error, also i.e. not conducting simultaneously of this full bridge circuit makes it be difficult for producing signal error.
Shown in Fig. 5 A to 5B, structure and simulation waveform synoptic diagram thereof for second embodiment of memory construction of the present invention, first switch member 21 of this full bridge circuit and the 4th switch member 24 are the N channel field effect transistors, second switch spare 22 and the 3rd switch member 23 then are the P channel field effect transistors, by the different qualities of this P channel field effect transistors and N channel field effect transistors, positive pulse and negative pulse that its generation is varied in size.
Shown in Fig. 6 A to 6B, structure and simulation waveform synoptic diagram thereof for the 3rd embodiment of memory construction of the present invention, the memory construction of present embodiment and second embodiment are roughly the same, but its main difference is first switch member 21 of this full bridge circuit and the 4th switch member 24 and is the P channel field effect transistors, second switch spare 22 and the 3rd switch member 23 then are the N channel field effect transistors, by the different qualities of above-mentioned different channel field effect transistors, positive pulse and negative pulse that its generation is varied in size.
Shown in Fig. 7 A to 7B, structure and simulation waveform synoptic diagram thereof for the 4th embodiment of memory construction of the present invention, first switch member 21 and the second switch spare 22 of this full bridge circuit are the P channel field effect transistors, the 3rd switch member 23 and the 4th switch member 24 then are the N channel field effect transistors, and this first switch member 21 and the 4th switch member 24 common external one first control signals 13, this second switch spare 22 and the 3rd switch member 23 are then shared one second control signal 14, thereby produce time delay, and can produce the positive pulse and the negative pulse of symmetry.
Shown in Fig. 8 A to 8B, structure and simulation waveform synoptic diagram thereof for the 5th embodiment of memory construction of the present invention, the memory construction of present embodiment and first embodiment are roughly the same, but its main difference is that first switch member 21 of this full bridge circuit and the 3rd switch member 23 are the transmission lock that P channel field effect transistors and N channel field effect transistors are made up, this second switch spare 22 and the 4th switch member 24 then are the P channel field effect transistors, by the different qualities of above-mentioned different channel field effect transistors, positive pulse and negative pulse that its generation is varied in size.
Shown in Fig. 9 A to 9B, structure and simulation waveform synoptic diagram thereof for the 6th embodiment of memory construction of the present invention, the memory construction of present embodiment and first embodiment are roughly the same, but its main difference is the second switch spare 22 of this full bridge circuit and the 3rd switch member 23 and is the transmission lock, this first switch member 21 and the 4th switch member 24 then are the P channel field effect transistors, by the different qualities of above-mentioned different channel field effect transistors, positive pulse and negative pulse that its generation is varied in size.
Shown in Figure 10 A to 10B, structure and simulation waveform synoptic diagram thereof for the 7th embodiment of memory construction of the present invention, the memory construction of present embodiment and first embodiment are roughly the same, but its main difference is the 3rd switch member 23 of this full bridge circuit and the 4th switch member 24 and is the transmission lock, and this first switch member 21 is the P channel field effect transistors, 22 of this second switch spares are the N channel field effect transistors, by the different qualities of above-mentioned different channel field effect transistors, positive pulse and negative pulse that its generation is varied in size.
Shown in Figure 11 A to 11B, structure and simulation waveform synoptic diagram thereof for the 8th embodiment of memory construction of the present invention, the memory construction of present embodiment and first embodiment are roughly the same, but its main difference is first switch member 21 of this full bridge circuit and second switch spare 22 and is the transmission lock, and the 3rd switch member 23 is the N channel field effect transistors, 24 of the 4th switch member are the P channel field effect transistors, by the different qualities of above-mentioned different channel field effect transistors, positive pulse and negative pulse that its generation is varied in size.
Shown in Figure 12 A to 12B, structure and simulation waveform synoptic diagram thereof for the 9th embodiment of memory construction of the present invention, the memory construction of present embodiment and first embodiment are roughly the same, but its main difference is the 3rd switch member 23 of this full bridge circuit and the 4th switch member 24 and is the transmission lock, this first switch member 21 and this second switch spare 22 then are the P channel field effect transistors, by the different qualities of above-mentioned different channel field effect transistors, and can produce symmetrical positive pulse and negative pulse.
Shown in Figure 13 A to 13B, structure and simulation waveform synoptic diagram thereof for the tenth embodiment of memory construction of the present invention, the memory construction of present embodiment and first embodiment are roughly the same, but its main difference is first switch member 21 of this full bridge circuit and second switch spare 22 and is the transmission lock, the 3rd switch member 23 and the 4th switch member 24 then are the N channel field effect transistors, by the different qualities of above-mentioned different channel field effect transistors, and can produce symmetrical positive pulse and negative pulse.
In sum, memory construction of the present invention is to comprise a power circuit and a bridge circuit, drive this bridge circuit by this power circuit and do positive negative sense switching, thereby produce positive pulse, negative pulse and share pulse, this memory construction simple in structure only need be used one group of power circuit, and not need to know in advance the resistance of its bit line, can utilize power circuit to produce required current value, make its easy and other peripherals collocation application.
In addition, memory construction of the present invention can be selected in response to actual demand to change, can distinguish external or shared different control signal, or the different qualities by P channel field effect transistors and N channel field effect transistors, make this memory construction when positive negative sense switches, be difficult for to produce signal error, and can adjust positive and negatively, also can change the positive negative sense magnitude of current to switch.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those of ordinary skill in the art all can be under spirit of the present invention and scope, and the foregoing description is modified and changed.Therefore, the scope of the present invention, claim is listed as described later.
Claims (13)
1, a kind of memory construction, this memory construction comprises:
One power circuit, it comprises input end and output terminal; And
One bridge circuit, it has one first switch member, a second switch spare, one the 3rd switch member and one the 4th switch member, thereby formation quarter-phase circuit, the two-phase docking point of this bridge circuit is connected with this input end and this output terminal, the two-phase docking point in addition of this bridge circuit is the current lead-through path, by the driving of this power circuit, in order to produce a plurality of conduction modes.
2, memory construction according to claim 1, wherein, these a plurality of conduction modes comprise:
When this first switch member and the 3rd switch member conducting, when this second switch spare and the 4th switch member are disconnection, the input end of this power circuit is exported an electric current, and flow to the resistor assembly of this bridge circuit via this first switch member, to produce one first pulse, flow to the output terminal of this power circuit again via the 3rd switch member;
When this second switch spare and the 4th switch member are conducting, when this first switch member and the 3rd switch member are disconnection, the input end of this power circuit is exported an electric current, and flow to this resistor assembly via this second switch spare, to produce one second pulse, this electric current flow to the output terminal of this power circuit again via the 4th switch member; And
When this first switch member, this second switch spare, the 3rd switch member and the 4th switch member are all disconnection, produce one the 3rd pulse.
3, memory construction according to claim 1, wherein, this full bridge circuit is made up of two P channel field effect transistors and two N channel field effect transistors.
4, memory construction according to claim 1, wherein, this full bridge circuit is made up of with the various permutation and combination of transmission lock P channel field effect transistors, N channel field effect transistors.
5, memory construction according to claim 3, wherein, this P channel field effect transistors and this N channel field effect transistors are formed a positive half cycle driving and a negative half period drives.
6, memory construction according to claim 1, wherein, this bridge circuit comprises a resistor assembly.
7, memory construction according to claim 6, wherein, this resistor assembly comprises the resistance of bit line.
8, a kind of wiring method of memory construction, it produces an electric current by a power circuit, in order to driving a bridge circuit, thereby produces a plurality of conduction modes, and these a plurality of conduction modes comprise:
When first switch member and the 3rd switch member of this bridge circuit is conducting, when the second switch spare of this bridge circuit and the 4th switch member are disconnection, the input end output current of this power circuit, and flow to the resistor assembly of this bridge circuit via this first switch member, to produce one first pulse, flow to the output terminal of this power circuit again via the 3rd switch member;
When this second switch spare and the 4th switch member are conducting, when this first switch member and the 3rd switch member are disconnection, the input end output current of this power circuit, and flow to this resistor assembly via this second switch spare, to produce one second pulse, this electric current flow to the output terminal of this power circuit again via the 4th switch member; And
When this first switch member, this second switch spare, the 3rd switch member and the 4th switch member are all disconnection, produce one the 3rd pulse.
9, the wiring method of memory construction according to claim 8, wherein, this full bridge circuit is made up of two P channel field effect transistors and two N channel field effect transistors.
10, the wiring method of memory construction as claimed in claim 8, wherein, this full bridge circuit is made up of with the various permutation and combination of transmission lock P channel field effect transistors and N channel field effect transistors.
11, the wiring method of memory construction according to claim 9, wherein, this P channel field effect transistors and this N channel field effect transistors are formed a positive half cycle driving and a negative half period drives.
12, memory construction according to claim 8, wherein, this bridge circuit includes a resistor assembly.
13, memory construction according to claim 12, wherein, this resistor assembly comprises the resistance of bit line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510137653 CN1996488A (en) | 2005-12-31 | 2005-12-31 | Memory structure and its writing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510137653 CN1996488A (en) | 2005-12-31 | 2005-12-31 | Memory structure and its writing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1996488A true CN1996488A (en) | 2007-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510137653 Pending CN1996488A (en) | 2005-12-31 | 2005-12-31 | Memory structure and its writing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1996488A (en) |
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2005
- 2005-12-31 CN CN 200510137653 patent/CN1996488A/en active Pending
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Open date: 20070711 |