CN1988116A - Method of manufacturing a field effect transistor and transistor structure manufactured thereby - Google Patents
Method of manufacturing a field effect transistor and transistor structure manufactured thereby Download PDFInfo
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- CN1988116A CN1988116A CN 200510132690 CN200510132690A CN1988116A CN 1988116 A CN1988116 A CN 1988116A CN 200510132690 CN200510132690 CN 200510132690 CN 200510132690 A CN200510132690 A CN 200510132690A CN 1988116 A CN1988116 A CN 1988116A
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- 230000005669 field effect Effects 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 370
- 239000010703 silicon Substances 0.000 claims abstract description 370
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 369
- 239000010409 thin film Substances 0.000 claims abstract description 84
- 239000010408 film Substances 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 76
- 238000005530 etching Methods 0.000 claims abstract description 50
- 239000000463 material Substances 0.000 claims abstract description 39
- 230000003647 oxidation Effects 0.000 claims description 31
- 238000007254 oxidation reaction Methods 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 230000000694 effects Effects 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 21
- 239000004065 semiconductor Substances 0.000 description 8
- 150000003376 silicon Chemical class 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229940090044 injection Drugs 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of fabricating a field effect transistor comprising a channel comprised of a silicon fin and a silicon body, wherein the silicon fin is oriented differently than the silicon body, and a field effect transistor fabricated by the method are disclosed. The method comprises the following steps: forming a hard mask pattern on a substrate including a silicon thin film; (b) anisotropically etching the silicon thin film to a predetermined thickness using the mask pattern as a mask, thereby forming not only silicon fins in which channels are to be formed and silicon patterns in which source/drain regions are to be formed, but also silicon bodies connecting the silicon fins to each other to form channels; (c) partially etching the silicon thin film using an active mask to isolate the source/drain regions and the device from each other; and (d) growing a gate dielectric film around the silicon channel and sequentially depositing a gate material and a gate mask on the resulting structure, and then forming a gate region.
Description
Technical field
The present invention relates to a kind of method of field-effect transistor and transistor arrangement of making by this method made.More specifically, the present invention relates to a kind of manufacturing comprises by the method for the field-effect transistor of silicon fin and the raceway groove that constitutes of the orientation silicon main body different with this silicon fin and the field-effect transistor by this method manufacturing.
Background technology
At present, in the trial of price that reduces semiconductor device and raising device performance, size of semiconductor device constantly reduces according to Moore's Law, makes it possible to thus realize that the height of semiconducter IC chip is integrated.
Yet, because the channel length of semiconductor device is decreased to below the 100nm, so not only will but also will control the current potential of the raceway groove in the field-effect transistor of prior art by the grid region by the drain region, even thereby when device is in cut-off state, also can appear at the phenomenon that flows through very big leakage current between source region and the drain region.
In order to suppress this short-channel effect, proposed to use main body that the thin silicon thin film by SOI (silicon-on-insulator) wafer constitutes as ultra-thin body (UTB) transistor arrangement of raceway groove and the transistor arrangement that uses two or more grids.Under the situation of using the film raceway groove, the influence that exhausts (depletion) electric charge and electric capacity reduces, and makes to suppress short-channel effect effectively, and need not extra channel doping.This can alleviate the problem of the mobility decline that causes owing to the impurity dispersion.
Double-grid structure is the silicon thin film field-effect transistor that SOI (silicon-on-insulator) complementary metal oxide semiconductors (CMOS) (CMOS) technology by prior art is made.In this structure, form raceway groove by the both sides that grid are arranged on the silicon raceway groove that forms perpendicular to substrate, thereby strengthen the control ability of gate voltage, to reduce leakage current to channel potential.
After this, developed: have the deviation that reduces aspect the effective insulation between device property between the wafer and device of fin formula field effect transistor structure and manufacture method thereof, this structure; And body contact omega FinFET structure and manufacture method thereof, this structure is used block substrate (bulksubstrate) rather than SOI substrate, to solve the heat conduction problem of fin formula field effect transistor.
Control the substituting of two-dimensional structure of the current potential of this raceway groove as a grid that is used to use silicon raceway groove top, three-dimensional bigrid or multiple-gate transistors tubular construction have been proposed, wherein a plurality of grids are arranged on the above and below or the both sides of raceway groove, so that control the ability maximum of channel potential, and used thin silicon fin by gate voltage.
Yet under the situation of this three-dimensional perpendicular grid that uses fin-shaped channel, to be formed on crystal orientation different for the situation of the horizontal transistor in the silicon main body of (100) with raceway groove wherein, and raceway groove is formed on crystal orientation in the sidewall of (110).The mobility of electronics shows peak on (100) plane, and descends in order on (111) and (110) plane, and the mobility in hole shows peak on (110) plane, and descends in order on (111) and (100) plane.
As a result, situation about being formed on raceway groove in (100) plane is compared, and the N type fin formula field effect transistor that raceway groove is formed in (110) plane has lower mobility and current value.In addition, there is following problem in this fin formula field effect transistor, in designs channel width is proofreaied and correct more complicated.
In the trial that addresses this problem, a kind of field-effect transistor with silicon fin and silicon main body has been proposed, this field-effect transistor is in simple mode, by making with the similar technology of the transistorized manufacturing process of prior art SOI.
Illustrate according to the method that is used to form the silicon thin film field-effect transistor of prior art and the problem in this method hereinafter with reference to accompanying drawing.
Fig. 1 represents that successively both sides that are used to make fin according to prior art all are formed with the technology stereogram of method of the fin formula field effect transistor of grid.
As shown in Figure 1, comprising on the SOI substrate 101 of silicon substrate, forming flush type oxidation film 102 and silicon thin film 103a, hard mask 104a (100A).
Then, use lithography to form silicon channel pattern (100B).
Then, carry out oxidation and etching, with the width (100C) of the fin that reduces above formation.
Growth or deposit be used for the material of the dielectric film of grid 107 and grid 107 after, composition is carried out in the zone of grid, and injects ion to form source/drain extension territory (100D).
After the both sides of grid 107 form interval body 108, inject formation source/drain region (100E) by ion.
Use self-aligned silicide technology to form electrode 109, make fin formula field effect transistor (100F) thus.
There is following shortcoming in device by this method manufacturing: because must increase the current value of the channel width of device with the increase device, so it needs very big area.Another problem is in designs the device channel width to be proofreaied and correct more complicated.
Fig. 2 is the technology cutaway view of the method for the expression prior art that is used to make fin formula field effect transistor, and the device property that wherein uses the block substrate to reduce between the wafer changes, and realizes the insulation between the device effectively.
As shown in Figure 2, the hard mask barrier layer of deposit 202a and mask capping layer 201a (200A) successively firmly on block wafer 203a.
After this deposit, use photoetching technique that hard mask barrier layer 202a and hard mask capping layer 201a are carried out composition, to form the fin pattern (200B) that constitutes by hard mask barrier layer 202b and hard mask capping layer 201b.
Use the hard mask capping layer 201b and the high key-course of fin of institute's composition, 203c anisotropically is etched to desired depth with this block substrate, with the height (200C) of control fin.
In order between the heat of oxidation speed of growth of the substrate between silicon raceway groove and the fin to be controlled, to use hard mask barrier layer covering silicon raceway groove and inject ion, between fin, to form damaged layer 204 (200D).
Growth or deposit gate dielectric film and grid material are made fin formula field effect transistor (200F) thus on the block substrate.
There is following problem in this structure: because use the height key-course damaged owing to inject heavy ion to control the height of fin, so compare with the situation of using the SOI substrate, be difficult to control the precise height of silicon raceway groove.In addition, also there is a problem, because must increase the current value of the channel width of device, so it needs very big area with the increase device.The another one problem is in designs channel width to be proofreaied and correct more complicated.
Fig. 3 is the technology cutaway view of the method for the expression prior art that is used to make the omega fin formula field effect transistor, wherein uses the block substrate to solve the heat conduction problem of fin formula field effect transistor.
As shown in Figure 3, use grooving processes in silicon substrate, to form the silicon raceway groove, and utilize oxidation and etching that the width of the fin that will form raceway groove and source/drain region is controlled (300A).
Grow oxide film and deposition of nitride film (300B).
Use chemical vapor deposition to come deposition oxide film (300C).
Use nitride film to carry out chemico-mechanical polishing (CMP) (300D) as etching stopping layer.
Nitride film is carried out wet etching, and inject ion subsequently, so that can control (300E) critical voltage.
Growth or deposit gate dielectric film and grid material are made omega fin formula field effect transistor (300F) thus on this block substrate.
There is following problem in this structure, owing to use grooving processes to control the height of fin, so compare with the situation of using the SOI substrate, is difficult to control the precise height of silicon raceway groove.
In addition, also there is following problem: because must increase the current value of the channel width of device, so it needs very big area with the increase device.The another one problem is in designs channel width to be proofreaied and correct more complicated.
Summary of the invention
Therefore, the present invention is proposed to solve the above problem that occurs in the prior art, and an object of the present invention is to provide a kind of method of making field-effect transistor, this field-effect transistor comprises the raceway groove that is made of silicon fin and the orientation silicon main body different with this silicon fin, wherein by silicon being etched into given thickness, perhaps, form silicon fin and silicon main body by the selective epitaxial growth of silicon.
Another object of the present invention provides a kind of field-effect transistor of making by described manufacture method, and it has the current value of increase and can proofread and correct channel width simply in designs.
In order to realize above purpose, according to first embodiment, the invention provides a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps: (a) form hard mask pattern comprising on the substrate of silicon thin film; (b) use this mask pattern silicon thin film anisotropically to be etched into predetermined thickness as mask, thereby not only form the silicon pattern that wherein will form the silicon fin of raceway groove and wherein will form source/drain region, and formation is connected to each other silicon fin to form the silicon main body of raceway groove; (c) it is partially-etched to use active mask that silicon thin film is carried out, so that source/drain region and this device are isolated from each other; And (d) gate dielectric film of growing around the silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
According to second embodiment, the invention provides a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps: (a) form hard mask pattern comprising on the substrate of silicon thin film; (b) it is partially-etched to use active mask that silicon thin film is carried out, so that source/drain region and this device are isolated from each other; (c) use this mask pattern silicon thin film anisotropically to be etched into predetermined thickness as mask, thereby not only form the silicon pattern that wherein will form the silicon fin of raceway groove and wherein will form source/drain region, and formation is connected to each other silicon fin to form the silicon main body of raceway groove; (d) gate dielectric film of growing around the silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
According to the 3rd embodiment, the invention provides a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps: (a) form the substrate that comprises silicon thin film; (b) on silicon thin film, form the film of making by material, and use mask that this high etch-selectivity film is carried out etching, to form the part that wherein will form silicon fin with high etch-selectivity; (c) selective epitaxial growth by silicon forms silicon fin on the part of described formation; (d) it is partially-etched to use active mask that silicon thin film is carried out, so that source/drain region and this device are isolated from each other; And (e) gate dielectric film of growing around the silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
According to the 4th embodiment, the invention provides a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps: (a) form the substrate that comprises silicon thin film; (b) it is partially-etched to use active mask that silicon thin film is carried out, so that source/drain region and this device are isolated from each other; (c) on silicon thin film, form the film of making by material, and this high etch-selectivity film is carried out etching and composition, to form the part that wherein will form silicon fin with high etch-selectivity; (d) selective epitaxial growth by silicon forms silicon fin on the part of described formation; And (e) gate dielectric film of growing around the silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
According to the 5th embodiment, the invention provides a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps: (a) form the substrate that comprises silicon thin film; (b) on silicon thin film, form hard mask, on this hard mask, form poly-silicon pattern, the film that deposit is made by the material with high etch-selectivity on resulting structure carries out etching to this high etch-selectivity film subsequently, to form sidewall on the both sides of poly-silicon pattern; (c) hard mask, polysilicon and silicon thin film are carried out etching,, be isolated from each other thereby make as these sidewalls and this device that are used to form the mask of silicon fin to expose the flush type oxidation film; (d) use these sidewalls and hard mask anisotropically silicon thin film to be carried out etching,, simultaneously the etched thickness of silicon thin film is controlled, between silicon fin, to stay thin silicon main body to form the silicon fin that wherein will form raceway groove; And (e) gate dielectric film of growing around the silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
According to the 6th embodiment, the invention provides a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps: (a) form the substrate that comprises silicon thin film; (b) on silicon thin film, form hard mask, on this hard mask, form poly-silicon pattern, the film that deposit is made by the material with high etch-selectivity on resulting structure carries out etching to this high etch-selectivity film subsequently, to form sidewall on the both sides of poly-silicon pattern; (c) hard mask, polysilicon and silicon thin film are carried out etching,, be isolated from each other thereby make as these sidewalls and this device that are used to form the mask of silicon fin to expose the flush type oxidation film; (d) use these sidewalls and hard mask anisotropically silicon thin film to be carried out etching, to form the silicon fin that wherein will form raceway groove, simultaneously the etched thickness of silicon thin film is controlled, between silicon fin, staying thin silicon main body, and silicon fin and silicon main body are isolated from each other; And (e) gate dielectric film of growing around the silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
On the other hand, the invention provides a kind of by field-effect transistor according to any one manufacturing of the method for first to the 6th embodiment, wherein with silicon fin and silicon main body as raceway groove.
Description of drawings
By detailed description below in conjunction with accompanying drawing, can more be expressly understood above and other purpose of the present invention, feature and advantage, in the accompanying drawing:
Fig. 1 represents that successively both sides that are used to make fin according to prior art all are formed with the technology stereogram of method of the fin formula field effect transistor of grid;
Fig. 2 is the method for fin formula field effect transistor is made in expression according to the use block substrate of prior art a technology cutaway view;
Fig. 3 is the prior art of omega fin formula field effect transistor is made in expression according to the use block substrate of prior art the technology cutaway view of method;
Fig. 4 a represents that successively manufacturing according to the embodiment of the invention 1 has the technology stereogram of method of the field-effect transistor of the raceway groove that is made of silicon fin and silicon main body;
Fig. 4 b is the a-a ' cutaway view by the device of the manufacturing of method shown in Fig. 4 a;
Fig. 5 represents that successively manufacturing according to the embodiment of the invention 3 has the technology cutaway view of method of the field-effect transistor of the raceway groove that is made of silicon fin and silicon main body;
Fig. 6 represents that successively manufacturing according to the embodiment of the invention 5 has the technology cutaway view of method of the field-effect transistor of the raceway groove that is made of silicon fin and silicon main body;
Fig. 7 represents that successively manufacturing according to the embodiment of the invention 6 has the technology cutaway view of method of the field-effect transistor of the raceway groove that is made of silicon fin and silicon main body;
Fig. 8 is a curve chart of representing the comparison of the I-E characteristic between the field-effect transistor of field-effect transistor and prior art according to an embodiment of the invention; And
Fig. 9 is a cutaway view of representing the comparison of the channel width between the field-effect transistor of field-effect transistor and prior art according to an embodiment of the invention.
Embodiment
Describe a plurality of preferred embodiments of the method be used to make field-effect transistor below with reference to accompanying drawings in detail, this field-effect transistor comprises by silicon fin and is orientated the raceway groove that the silicon main body different with this silicon fin constitutes.Although will these embodiment be described at the SOI substrate, they also can use the substrate that comprises silicon, for example silicon bulk substrate, tensile silicon substrate or SiGe substrate according to the technology identical with the SOI substrate.
Embodiment 1
Fig. 4 a is a technology stereogram of representing to be used to make the method for the field-effect transistor that comprises the raceway groove that is made of silicon fin and silicon main body successively.
At first, provide SOI substrate, it comprises silicon substrate 401, flush type oxidation film 402, and is formed on the silicon thin film 403 on the flush type dielectric film 402.Form hard mask 404 (400A) on silicon thin film 403, this hard mask 404 is by can not making by etched material in to the follow-up anisotropy of silicon thin film or isotropic etching.
In this step, also hard mask 404 can be formed on the silicon bulk substrate, rather than be formed on the SOI substrate that comprises silicon substrate 401, flush type oxidation film 402 and silicon thin film 403.
Then, use mask pattern 404 silicon thin film 403 to be carried out anisotropic etching, wherein will form the silicon fin 403 of raceway groove to form as mask, and the silicon pattern 403a that wherein will form source/drain region.In addition, silicon thin film is etched into predetermined thickness, to form the silicon main body that wherein will form raceway groove.That is, to the thickness of etched silicon thin film control, make the thin silicon main body 403c of residue between the silicon fin.
Silicon thin film 403 is anisotropically being etched into predetermined thickness with after forming the silicon main body, can also carry out following steps: making through etched silicon face evenly, perhaps carry out hydrogen annealing, to suppress corner effect.
As mentioned above, by between silicon fin, staying the silicon main body of given thickness, make silicon fin have different crystal orientations with the silicon main body.Therefore, use these planes to make and electric current can be maximized as raceway groove.
In addition,, increased the channel width of resulting device, perhaps guaranteed the convenience that the device channel width is proofreaied and correct by between silicon fin, staying the silicon main body of given thickness.
In addition,, increased the channel width of device, increased the electric current that flows through by the raceway groove that forms of the orientation silicon main body different, and guaranteed convenience that the device channel width is proofreaied and correct with silicon fin by between silicon fin, staying the silicon main body of given thickness.
After this, it is partially-etched to use 405 pairs of silicon thin films of active mask to carry out, so that source/drain region and this device are isolated from each other (400C).
Then, remove mask pattern, on flush type oxidation film 402, to stay thin silicon thin film 403.
By using this active mask to carry out anisotropy or isotropic etching, carry out partially-etched to the silicon thin film on the flush type oxidation film 402 403.
Next, the gate dielectric film 406 of around the raceway groove of silicon thin film 403, growing, and on resulting structure deposit grid material 407 and grid mask 408 successively, form the grid region then.
In this step, a plurality of grids of the both sides at least that cover each silicon fin have been formed.
In this way, field-effect transistor of the present invention be can make, silicon fin and silicon main body wherein formed to be used as raceway groove.
Embodiment 2
Except following aspect, embodiments of the invention 2 are identical with embodiment 1: use 405 pairs of silicon main bodys of active mask to carry out etching having carried out, so that the step (400C) that source/drain region and this device are isolated from each other afterwards, carry out the step (400B) of using hard mask 400 to form silicon fin.Therefore, omitted the accompanying drawing of representing second embodiment herein.
Fig. 4 b is the a-a ' cutaway view by the device of the manufacturing of the method shown in Fig. 4 a.
From Fig. 4 b as can be seen, silicon fin and silicon main body be as raceway groove, being oriented to of silicon fin (110), and being oriented to of silicon main body (100).
Under the situation of NMOS according to an embodiment of the invention, not only pass through the effect of the increase of the device channel width in the silicon main body, and the increase of the mobility that causes by the orientation by the silicon main body, the electric current that electron mobility caused in the silicon fin that is oriented to (110) is reduced to compensate.
In addition, under the situation of PMOS, although since on mobility ratio (100) orientation in hole on (110) orientation of silicon main body greatly, and the advantage forfeiture that causes the current value that brought by the orientation of silicon main body to increase, but the effect of increase that will be by the device channel width comes electric current is compensated.
Fig. 5 represents that successively manufacturing according to the embodiment of the invention 3 has the technology cutaway view of method of the field-effect transistor of the raceway groove that is made of silicon fin and silicon main body.
At first, provide SOI substrate (500A), it comprises silicon substrate 501, flush type oxidation film 502, and is positioned at the silicon thin film 503 on the flush type oxidation film 502.
In this step, also can use the silicon bulk substrate, rather than comprise the SOI substrate of silicon substrate 501, flush type oxidation film 502 and silicon thin film 503.
Then, on silicon thin film 503, form oxidation film 504, and use mask to carry out etching and composition, to form the part (500B) that wherein will form silicon fin.
In this step, also can be on silicon thin film 503 deposit or the other materials of growth except that oxidation film, use mask to carry out etching then.
Next, utilize the selective epitaxial growth of silicon to form silicon fin 503a (500C).
In this step, on silicon main body 503b, form silicon fin 503a, make silicon fin 503a have different orientations with silicon main body 503b.Therefore, use these planes to make and to make the electric current maximization as raceway groove.
In addition,, increased the channel width of device, perhaps guaranteed the convenience of when designs, device channel being proofreaied and correct by on the silicon main body, forming silicon fin.
After this, remove oxidation film 504, and it is partially-etched to use 505 pairs of silicon thin films of active mask to carry out, so that source/drain region and this device are isolated from each other (500D).
In this, after removing oxidation film 504, can also comprise making institute's exposed silicon surface evenly or carry out hydrogen annealing to suppress the step of corner effect.
By using active mask to carry out anisotropy or isotropic etching, carry out partially-etched to the silicon thin film on the flush type oxidation film 503.
Next, the gate dielectric film 506 of growing around the silicon raceway groove, and on resulting structure deposit grid material 507 and grid mask 508 successively, form the grid region then.
In this step, a plurality of grids of the both sides at least that cover each silicon fin have been formed.
In this way, field-effect transistor be can make, silicon fin and silicon main body wherein formed to be used as raceway groove according to the embodiment of the invention 3.
Embodiment 4
Except following aspect, embodiments of the invention 4 are identical with embodiment 3: use 505 pairs of silicon main bodys of active mask to carry out etching having carried out, so that the step (500D) that source/drain region and this device are isolated from each other afterwards, execution forms oxidation film 504 on silicon thin film 503, and use mask that oxidation film 504 is etched to the part that wherein will form silicon fin, form the step (500C) of silicon fin then by the selective epitaxial growth of silicon.Therefore, omitted the accompanying drawing of representing the 4th embodiment herein.
Embodiment 5
Fig. 6 represents that successively manufacturing according to the embodiment of the invention 5 has the technology stereogram of method of the field-effect transistor of the raceway groove that is made of silicon fin and the orientation silicon main body different with this silicon fin.In this embodiment, use interval body to form silicon fin.
At first, provide SOI substrate, it comprises silicon substrate 601, flush type oxidation film 602, and is positioned at the silicon thin film 603 on the flush type oxidation film 602.Then, on this substrate, form hard mask 604 (600A).This hard mask 604 is preferably by can not making by etched material in the anisotropic silicon etching.
On hard mask, form poly-silicon pattern 605, thereby can use the interval body lithography to form silicon fin (600B) after a while.
Deposition oxide film 606 on the both sides of poly-silicon pattern 605, and are etched with formation sidewall (600C).
Then hard mask 604 is carried out etching, to expose silicon thin film 603.
Hard mask 604 is carried out partially-etched, to form silicon fin (600F).
In order to form silicon fin, use oxide side walls 606 and hard mask 604 silicon thin film 603 to be carried out anisotropic etching, to form the silicon fin (600G) that wherein will form raceway groove after a while as mask.In this step, to the thickness of etched silicon thin film control, make between silicon fin 603b, to stay thin silicon main body 603a.
After removing oxide side walls 606 and hard mask 605, on silicon fin and silicon main body, form gate dielectric film 607 (600H).
After growth gate dielectric film 607, deposit grid material 608 and grid mask 609 successively on resulting structure form grid region (600I) subsequently.
In this step, mask 609 is preferably by can not making by etched material when grid material is carried out anisotropic etching.
Embodiment 6
Fig. 7 represents that successively manufacturing according to the embodiment of the invention 6 comprises the technology stereogram of method of the field-effect transistor of the raceway groove that is made of silicon fin and the orientation silicon main body different with this silicon fin.In this embodiment, silicon fin and silicon main body are isolated from each other.
At first, some steps of method shown in the execution graph 4a and 6.That is, step 400A among the execution graph 4a and the step 600A to 600G (700A) among 400B and Fig. 6.
In the step that forms silicon fin 703b and silicon main body 703a, etching condition is controlled, make silicon fin 703b and silicon main body 703a be isolated from each other.Then, growth gate dielectric film 707 (700B) on silicon fin and silicon main body.
After growth gate dielectric film 707, deposit grid material 708 and grid mask 709 successively on resulting structure form the grid region subsequently, make field-effect transistor thus.In this step, mask 709 is preferably by can not making by etched material when subsequently grid material being carried out anisotropic etching.
Fig. 8 is a curve chart of representing the comparison of the I-E characteristic between the field-effect transistor of field-effect transistor and prior art according to an embodiment of the invention.
Particularly, Fig. 8 a is expression to the field-effect transistor of prior art (using silicon fin as raceway groove) and the curve chart of the analog result of the comparison of the leakage current-gate voltage between the field-effect transistor (use silicon fin and silicon main body are as raceway groove) according to an embodiment of the invention.
Fig. 8 b is expression to the field-effect transistor of prior art (using silicon fin as raceway groove) and the curve chart of the analog result of the comparison of the leakage current-gate voltage between the field-effect transistor (use silicon fin and silicon main body are as raceway groove) according to another embodiment of the present invention.
As can be seen, the current value ratio that comprises the field-effect transistor of the present invention of the raceway groove that is made of silicon fin and silicon main body comprises that the current value of field-effect transistor of the prior art of the raceway groove that is made of silicon fin wants high from Fig. 8 a and 8b.
In addition, consider the effect that is caused by the orientation of silicon main body, the field-effect transistor structure of the present invention with the raceway groove that is made of silicon fin and silicon main body also can further strengthen.
Fig. 9 is the cutaway view of the comparison of the channel width between the field-effect transistor of expression field-effect transistor of the present invention and prior art.
Particularly, Fig. 9 a is the cutaway view of grid of the field-effect transistor of the prior art of expression with the raceway groove that is made of silicon fin, and the cutaway view of the grid of Fig. 9 b field-effect transistor of the present invention that to be expression have the raceway groove that is made of silicon fin and silicon main body.
In Fig. 9 a and 9b, W
FinThe width of representing each silicon fin, h
FinThe height of representing each silicon fin, W
UtbThe width of expression silicon main body, h
UtbThe height of expression silicon main body, and W
tThe width of expression silicon Subject Extension.
The channel width of field-effect transistor with prior art of the raceway groove that is made of silicon fin is expressed as 2W
Fin+ 4h
Fin, and the channel width with field-effect transistor of the present invention of the raceway groove that is made of silicon fin and silicon main body is expressed as 2W
Fin+ 4h
Fin-2h
Utb+ W
Utb+ 2W
t
Because parameter W
Fin, 2h
Utb, h
FinAnd W
tBe determined value, so under the situation of the prior art constructions with the raceway groove that is made of silicon fin, the correction of when designs the device channel width being carried out need be carried out complicated trimming process by a plurality of silicon fins.On the other hand, under the situation of structure of the present invention with the raceway groove that constitutes by silicon fin and silicon main body, can be to the correction of device channel width by change W
UtbRealize simply.
As mentioned above, the method for the present invention that is used to make the field-effect transistor that comprises the raceway groove that is made of silicon fin with different orientation and silicon main body makes it possible to make the device that characteristic is improved in simple and reproducible mode.Therefore, method of the present invention to size of semiconductor device constantly reduce have very great help.
In addition, method of the present invention is to utilize the very practical technology of current semiconductor technology, and can solve low current value and when designs to the problem of the correction difficulty of device channel width, these problems are considered to the problem in the fin formula field effect transistor of prior art.
In addition, because making, method of the present invention can constantly reduce size of semiconductor device, so helpful to the future development of semi-conductor industry.
Although preferred embodiments of the present invention have been disclosed for illustrative for illustrative purposes, but it should be appreciated by those skilled in the art, under situation about not breaking away from, can carry out multiple modification, interpolation and replacement as the disclosed the scope and spirit of the present invention of claims.
Claims (35)
1, a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps:
(a) form hard mask pattern comprising on the substrate of silicon thin film;
(b) use described hard mask pattern described silicon thin film anisotropically to be etched into predetermined thickness as mask, to form the silicon fin that wherein will form raceway groove, form the silicon pattern that wherein will form source/drain region, and formation is connected to each other described silicon fin to form the silicon main body of described raceway groove;
(c) it is partially-etched to use active mask that described silicon thin film is carried out, so that described source/drain region and described device are isolated from each other; And
(d) gate dielectric film of growing around the described silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
2, the described substrate that comprises described silicon thin film that uses in the method according to claim 1, wherein said step (a) is to select from the group that is made of silicon-on-insulator substrate, silicon bulk substrate, tensile silicon substrate and SiGe substrate.
3, method according to claim 1, wherein in the step (b) that forms described silicon main body by etching afterwards, further comprising the steps of: as to utilize surface that hydrogen annealing makes the silicon thin film after the etching evenly, to suppress corner effect.
4, method according to claim 1 is wherein carried out etching in the described step (c) by anisotropy or isotropic etching.
5, method according to claim 1, the grid in the wherein said step (d) are a plurality of grids that cover the both sides at least of each silicon fin.
6, a kind of field-effect transistor by any manufacturing in the claim 1 to 5, it comprises the raceway groove that is made of silicon fin and silicon main body, wherein said silicon fin has and the different orientation of described silicon main body.
7, a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps:
(a) form hard mask pattern comprising on the substrate of silicon thin film;
(b) it is partially-etched to use active mask that described silicon thin film is carried out, so that source/drain region and described device are isolated from each other;
(c) use described mask pattern described silicon thin film anisotropically to be etched into predetermined thickness as mask, to form the silicon fin that wherein will form raceway groove, form the silicon pattern that wherein will form source/drain region, and formation is connected to each other described silicon fin to form the silicon main body of described raceway groove;
(d) gate dielectric film of growing around the described silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
8, the described substrate that comprises described silicon thin film that uses in the method according to claim 7, wherein said step (a) is to select from the group that is made of silicon-on-insulator substrate, silicon bulk substrate, tensile silicon substrate and SiGe substrate.
9, method according to claim 7, wherein in the step (c) that forms described silicon main body by etching afterwards, further comprising the steps of: as to utilize surface that hydrogen annealing makes the silicon thin film after the etching evenly, to suppress corner effect.
10, method according to claim 7 is wherein carried out etching in the described step (b) by anisotropy or isotropic etching.
11, method according to claim 7, the grid in the wherein said step (d) are a plurality of grids that cover the both sides at least of each silicon fin.
12, a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps:
(a) form the substrate that comprises silicon thin film;
(b) on described silicon thin film, form the film of making by material, and use mask that this high etch-selectivity film is carried out etching, to form the part that wherein will form silicon fin with high etch-selectivity;
(c) selective epitaxial growth by silicon forms silicon fin on the part of described formation;
(d) it is partially-etched to use active mask that described silicon thin film is carried out, so that source/drain region and described device are isolated from each other; And
(e) gate dielectric film of growing around the described silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
13, the described substrate that comprises described silicon thin film that uses in the method according to claim 12, wherein said step (a) is to select from the group that is made of silicon-on-insulator substrate, silicon bulk substrate, tensile silicon substrate and SiGe substrate.
14, the described film that the material by having high etch-selectivity that uses in the method according to claim 12, wherein said step (b) is made is oxidation film or nitride film.
15, method according to claim 12, wherein in the step (c) that forms described silicon main body by etching afterwards, further comprising the steps of: as to remove described high etch-selectivity film, make described silicon thin film even then, perhaps carry out hydrogen annealing, to suppress corner effect.
16, method according to claim 12 is wherein carried out etching in the described step (b) by anisotropy or isotropic etching.
17, method according to claim 12, the grid in the wherein said step (e) are a plurality of grids that cover the both sides at least of each silicon fin.
18, a kind of field-effect transistor by any manufacturing in the claim 12 to 17, it comprises the raceway groove that is made of silicon fin and silicon main body, wherein said silicon fin has and the different orientation of described silicon main body.
19, a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps:
(a) form the substrate that comprises silicon thin film;
(b) it is partially-etched to use active mask that described silicon thin film is carried out, so that source/drain region and described device are isolated from each other;
(c) on described silicon thin film, form the film of making by material, and this high etch-selectivity film is carried out etching and composition, to form the part that wherein will form silicon fin with high etch-selectivity;
(d) selective epitaxial growth by silicon forms silicon fin on the part of described formation; And
(e) gate dielectric film of growing around the described silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
20, the described substrate that comprises described silicon thin film that uses in the method according to claim 19, wherein said step (a) is to select from the group that is made of silicon-on-insulator substrate, silicon bulk substrate, tensile silicon substrate and SiGe substrate.
21, the described film that the material by having high etch-selectivity that uses in the method according to claim 19, wherein said step (c) is made is oxidation film or nitride film.
22, method according to claim 19, wherein in the described step (c) that forms described silicon main body by etching afterwards, further comprising the steps of: as to remove described high etch-selectivity film, make described silicon thin film even then, perhaps carry out hydrogen annealing, to suppress corner effect.
23, method according to claim 19 is wherein carried out etching in the described step (b) by anisotropy or isotropic etching.
24, method according to claim 19, the grid in the wherein said step (e) are a plurality of grids that cover the both sides at least of each silicon fin.
25, a kind of field-effect transistor by any manufacturing in the claim 19 to 24, it comprises the raceway groove that is made of silicon fin and silicon main body, wherein said silicon fin has and the different orientation of described silicon main body.
26, a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps:
(a) form the substrate that comprises silicon thin film;
(b) on described silicon thin film, form hard mask, on this hard mask, form poly-silicon pattern, the film that deposit is made by the material with high etch-selectivity on resulting structure carries out etching to this high etch-selectivity film subsequently, to form sidewall on the both sides of described poly-silicon pattern;
(c) described hard mask, described polysilicon and described silicon thin film are carried out etching,, be isolated from each other thereby make as the described sidewall and the described device that are used to form the mask of described silicon fin to expose the flush type oxidation film;
(d) use described sidewall and described hard mask that described silicon thin film is carried out anisotropic etching,, simultaneously the etched thickness of described silicon thin film is controlled, between described silicon fin, to stay thin silicon main body to form the silicon fin that wherein will form raceway groove; And
(e) gate dielectric film of growing around the described silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
27, the described substrate that comprises described silicon thin film that uses in the method according to claim 26, wherein said step (a) is to select from the group that is made of silicon-on-insulator substrate, silicon bulk substrate, tensile silicon substrate and SiGe substrate.
28, the film that the material by having high etch-selectivity that uses in the method according to claim 26, wherein said step (b) is made is oxidation film or nitride film.
29, method according to claim 26, the grid in the wherein said step (e) are a plurality of grids that cover the both sides at least of each silicon fin.
30, a kind of field-effect transistor by any manufacturing in the claim 26 to 29, it comprises the raceway groove that is made of silicon fin and silicon main body, wherein said silicon fin has and the different orientation of described silicon main body.
31, a kind of method of making field-effect transistor, this field-effect transistor has the raceway groove that is made of silicon fin and silicon main body, and this method may further comprise the steps:
(a) form the substrate that comprises silicon thin film;
(b) on described silicon thin film, form hard mask, on this hard mask, form poly-silicon pattern, the film that deposit is made by the material with high etch-selectivity on resulting structure carries out etching to this high etch-selectivity film subsequently, to form sidewall on described poly-silicon pattern;
(c) described hard mask, described polysilicon and described silicon thin film are carried out etching,, be isolated from each other thereby make as the described sidewall and the described device that are used to form the mask of silicon fin to expose the flush type oxidation film;
(d) use described sidewall and described hard mask that described silicon thin film is carried out anisotropic etching, to form the silicon fin that wherein will form raceway groove, simultaneously the etched thickness of described silicon thin film is controlled, between described silicon fin, staying thin silicon main body, and described silicon fin and described silicon main body are isolated from each other; And
(e) gate dielectric film of growing around the described silicon raceway groove, and on resulting structure deposit grid material and grid mask successively, form the grid region then.
32, the described substrate that comprises described silicon thin film that uses in the method according to claim 31, wherein said step (a) is to select from the group that is made of silicon-on-insulator substrate, silicon bulk substrate, tensile silicon substrate and SiGe substrate.
33, the film that the material by having high etch-selectivity that uses in the method according to claim 31, wherein said step (b) is made is oxidation film or nitride film.
34, method according to claim 31, the grid in the wherein said step (e) are a plurality of grids that cover the both sides at least of each silicon fin.
35, a kind of field-effect transistor by any manufacturing in the claim 31 to 34, it comprises the raceway groove that is made of silicon fin and silicon main body, wherein said silicon fin has and the different orientation of described silicon main body.
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| CN100536092C (en) * | 2007-09-21 | 2009-09-02 | 北京大学 | Method for manufacturing fin-shaped field effect transistor by epitaxial process |
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| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
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| CN104425601A (en) * | 2013-08-30 | 2015-03-18 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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