CN1983441A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device Download PDFInfo
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- CN1983441A CN1983441A CN 200610148592 CN200610148592A CN1983441A CN 1983441 A CN1983441 A CN 1983441A CN 200610148592 CN200610148592 CN 200610148592 CN 200610148592 A CN200610148592 A CN 200610148592A CN 1983441 A CN1983441 A CN 1983441A
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Abstract
A semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.
Description
Technical field
The present invention relates to semiconductor integrated circuit apparatus, be specifically related to a kind of semiconductor integrated circuit apparatus that reduces leakage current, this equipment comes the control gate pole tension by the temperature profile of considering leakage current mobile when the field effect transistor inertia, thereby has reduced leakage current.
Background technology
In nearest semiconductor integrated circuit apparatus, along with the appearance of less geometry semiconductor processes technology, power consumption reduces along with the reduction of supply voltage, and increases simultaneously along with the increase of integrated level and access speed.In addition, in nearest semiconductor integrated circuit apparatus, not only power consumption in the active state but also the power consumption in the holding state have all caused problem.The increase of power consumption is caused by less geometry semiconductor processes technology and low supply voltage during the holding state, particularly in MISFET (metal insulatioin semiconductor field effect transistor).If the supply voltage step-down, therefore the starting voltage of field effect transistor should reduce.Low starting voltage has caused the increase of sub-threshold current leakage.In addition, less geometry semiconductor processes technology has caused gate insulator to become thinner, and this has caused the increase of leakage current.
Leakage current comprises: the junction leakage (drain diffusion layer junction leakage) among the subthreshold current (sub-threshold current leakage) that causes owing to the drift or the diffusion of electric charge, the MISFET between drain region and the substrate regions, because the tunnel leakage current between drain region that the gate-to-drain electric field causes and the band-band between the substrate regions (band to band) tunnel leakage current (GIDL:Gate Induced DrainLeakage, gate induced drain leakage flows) and grid and drain electrode, source electrode and the substrate regions.Among these leakage currents, sub-threshold current leakage and drain diffusion layer junction leakage show the high temperature dependency characteristic.On the other hand, the tunnel leakage current between GIDL and grid and drain electrode, source electrode and the substrate regions shows the low temperature dependence.About these leakage currents, " " 16.7-fA/Cell Tunnel-Leakage-Suppressed 16-Mb SRAM forHandling Cosmic-Ray-Induced Multierrors "; Kenichi Osada et al.; IEEE journal of solid-state circuits; Vol.38; No.11; pp1952-1957, in November, 2003 " by being example, provide description about the relation between leakage current component and leakage current and the temperature with the leakage current of SRAM (static RAM) unit in holding state.In addition, " " Impact of Gate-Induced DrainLeakage on Retention Time Distribution of 256 Mbit DRAM WithNegative Wordline Bias "; Michen Chang et al.; IEEETransactions On Electron Devices; Vol.50; No.4; pp1036-1041, in April, 2003 ", in its Fig. 3, provide to rely on relevant about the description of the relation between the fail bit among the DRAM (dynamic RAM) and the word electromotive force and the grid voltage of GIDL.
The leakage current that flows through MISFET is described below with reference to Figure 19.Figure 19 shows the relation between the drain current and grid voltage among the MISFET.In the chart of Figure 19, Z-axis is represented the drain current under the logarithmic coordinate, and transverse axis is represented the grid voltage under the linear coordinate.As shown in figure 19, when grid voltage Vg surpasses threshold value, flow through the quantitative really drain current of MISFET because of becoming in the magnitude of voltage of grid voltage Vg.
When grid voltage Vg was lower than threshold value, the electric current that flows through was called as leakage current.As grid voltage Vg during near threshold value, the leakage current that is caused by the drift of charge carrier in the highest flight.Along with the reduction of grid voltage Vg, the leakage current that is caused by the skew of charge carrier reduces, and the leakage current that is caused by the diffusion of charge carrier in the highest flight.The grid voltage at the minimum place of drain current is Vg (Id_min＜environment temperature 〉).Locate at grid voltage Vg (Id_min＜environment temperature 〉), the drain diffusion layer junction leakage flows.In the time of under grid voltage drops to Vg (Id_min＜environment temperature 〉), GIDL increases.
Hereinafter GIDL is described in more detail.Because the electric field between drain region and the gate electrode, the electric field in the depletion layer of the near surface between drain region and the substrate regions becomes stronger, thereby has dwindled the depletion layer of setting up between drain region and substrate regions.This has caused tunnel current, and promptly GIDL flows to substrate regions from the drain region.Therefore, when the difference between drain voltage and the grid voltage became big, it is big that GIDL becomes.
Solid line among Figure 19 has been represented the drain current among the MISFET and the relation between the grid current under the environment temperature, and dotted line has been represented the relation under high temperature (for example 100 ℃).Particularly, along with uprising of substrate temperature, sub-threshold current leakage and drain diffusion layer junction leakage increase, thereby the minimum value of leakage current increases.The voltage Vg at the minimum place of leakage current (Id_min＜high temperature 〉) is lower than voltage Vg under the environment temperature (Id_min＜environment temperature 〉).
Some shortcomings have been drawn in the increase of leakage current, and for example power consumption increases and uses the data hold period of the memory cell (for example DRAM unit) of MISFET to reduce during the semiconductor integrated circuit apparatus standby.
A kind of method that reduces the sub-threshold current leakage in the above-mentioned leakage current is to use for example MTCMOS (Multi Threshold complementary Metal Oxide Semiconductor, multi-threshold cmos) or the element of VTCMOS (Variable ThresholdComplementary Metal Oxide Semiconductor, variable thresholding complementary metal oxide semiconductor (CMOS)).
In addition, the technology that a kind of source voltage by the NMOSFET in the control sram cell reduces the power consumption of all SRAM is disclosed in " " A 300MHz 25 μ A/Mb Leakage On-Chip SRAM ModuleFeaturing Process-Variation Immunity and Low-Leakage-ActiveMode for Mobile-Phone Application Processor "; Masanao Yamaokaet al.; IEEE International Solid-State Circuits Conference; pp494-495; 452,2004 years ".Japanese unexamined patent announces that disclosing a kind of grid voltage by the NMISFET in the storage unit among the No.2000-11651 is set to the technology that negative voltage reduces the standby current among the DRAM.In addition, Japanese unexamined patent is announced to disclose among the No.2003-173675 and a kind ofly is set to be higher than slightly the technology that ground voltage reduces GIDL by the voltage that is applied to word line during the standby of DRAM.
Though above-mentioned technology provides the control of grid voltage or source voltage so that reduce leakage current, does not control yet they provide with temperature correlation.The grid voltage Vg (Id_min) at the minimum place of leakage current depends on temperature.Therefore, though above-mentioned technology can reduce leakage current when semiconductor integrated circuit apparatus is in environment temperature, yet when temperature uprised, leakage current increased, and this is a unwanted results.
In addition, announce disclosed technology (grid voltage is set to negative voltage) among the No.2000-11651 according to Japanese unexamined patent, it is non-minimum value that negative voltage can make drain current increase.In addition, if the absolute value of the negative voltage of grid voltage is very big, need more time and energy so so that grid voltage is increased to supply voltage.This has hindered the high speed access to storage unit.
Summary of the invention
According to an aspect of the present invention, a kind of semiconductor integrated circuit apparatus is provided, comprise field effect transistor and voltage control circuit, this voltage control circuit produces the gate terminal that will offer in the field effect transistor, the control voltage that is used for the deactivation field effect transistor.Voltage control circuit is controlled voltage according to device temperature, so that minimize be in the non-leakage current that flows through when movable at field effect transistor substantially.
In this semiconductor integrated circuit apparatus, according to device temperature control voltage, thereby the leakage current that flows through when field effect transistor is in non-activity is substantially very little.This makes it possible to not consider that device temperature ground minimizes leakage current substantially.As a result, can not consider temperature in the semiconductor integrated circuit apparatus and the power consumption during the minimize standby substantially.
Description of drawings
According to description taken together with the accompanying drawings hereinafter, above and other objects of the present invention, advantage and characteristics will become obviously, wherein:
Fig. 1 is the circuit diagram according to the DRAM of first embodiment of the invention;
Fig. 2 shows the chart according to the relation of first embodiment between leakage current minimum place grid voltage and device temperature;
Fig. 3 shows the block diagram according to the voltage control circuit of first embodiment;
Fig. 4 shows the circuit diagram according to the example of the datum generator of first embodiment;
Fig. 5 shows the circuit diagram according to the level detector of first embodiment;
Fig. 6 shows according to the control voltage VNN of first embodiment and the chart of the relation between the device temperature;
Fig. 7 shows the circuit diagram according to the unit leakage meter of first embodiment;
Fig. 8 shows the chart according to the relation between the leakage current IA of first embodiment and the control voltage VNN;
Fig. 9 shows the chart of the relation between voltage VA and the control voltage VNN that detects according to the leakage current of first embodiment;
Figure 10 shows the block diagram according to the voltage control circuit of second embodiment of the invention;
Figure 11 shows each voltage that produces in the voltage control circuit according to second embodiment and the chart of the relation between the control voltage VNN;
Figure 12 shows the circuit diagram according to the level detector of third embodiment of the invention;
Figure 13 shows the circuit diagram according to the level detector of fourth embodiment of the invention;
Figure 14 shows the chart of the relation between the substrate voltage Vsub and drain current in the transfering transistor;
Figure 15 shows according to fifth embodiment of the invention at the substrate voltage Vsub at the minimum place of leakage current and the chart of the relation between the device temperature;
Figure 16 shows the block diagram according to the voltage control circuit of the 5th embodiment;
Figure 17 shows each voltage that produces according to the 5th embodiment and the chart of the relation between the substrate voltage Vsub in voltage control circuit;
Figure 18 is the sequential chart that is used to make the control signal that voltage control circuit operates according to the 5th embodiment; And
Figure 19 shows the grid voltage among the MISFET and the chart of the relation between the drain current.
Embodiment
Here will present invention is described with reference to illustrative embodiment.Those skilled in the art will appreciate that and use content of the present invention can realize a plurality of alternative embodiment, and the embodiment that the invention is not restricted to illustrate for the purpose of explaining.
First embodiment
The hereinafter with reference accompanying drawing is described exemplary embodiments of the present invention.Semiconductor integrated circuit apparatus among the present invention comes the control gate pole tension according to temperature, so that substantially the leakage current that is formed in the field effect transistor (for example MISFET) on the semiconductor substrate (hereinafter being called substrate simply) is minimized.Hereinafter in the exemplary embodiments of Miao Shuing, DRAM is as the example of semiconductor integrated circuit apparatus, describes control to the grid voltage of the transfering transistor among the DRAM in detail by example.Leakage current in hereinafter describing is meant the leakage current that preamble is described.
Fig. 1 shows the DRAM 1 according to first embodiment of the invention.As shown in Figure 1, DRAM1 comprises a plurality of storage unit 2; Bit line in the memory cell array and sub-word line; And sub-word line voltage is selected circuit 3 and as the voltage control circuit 4 of peripheral circuit.DRAM 1 among first embodiment selects circuit 3 that the first control voltage (for example controlling voltage VNN) that is produced by single voltage control circuit 4 is provided to a plurality of sub-word line voltages.Sub-word line voltage selects circuit 3 to link to each other with corresponding sub-word line respectively, thereby sub-word voltage is offered a plurality of storage unit 2 that link to each other with each sub-word line.
A plurality of storage unit 2 are arranged with grid pattern.The storage unit 2 that is arranged in same row is connected to a bit line, and the storage unit 2 that is arranged in delegation is connected to a word line (for example sub-word line).The column decoder (not shown) activates one of a plurality of bit lines, thereby specifies delegation to carry out read/write.Sub-word line is controlled by the major word signal of exporting from the row decoder (not shown), thereby specifies row to carry out read/write.
Sub-word line voltage selects circuit 3 to comprise that PMISFET P1 (will note, in the following description, if MISFET represent by specific reference symbol, so for clear understand for the purpose of, FET is expressed as " transistor ", i.e. " PMIS transistor P1 ") and nmis transistor N1 and N2.PMIS transistor P1 and nmis transistor N1 are phase inverters, and their drain electrode is connected with each other, and select signal for grid provides major word.For the source electrode of PMIS transistor P1 provides sub-word select to select signal A, and the source electrode of nmis transistor N1 links to each other with control voltage VNN.Particularly, select signal by major word, sub-word line voltage select the voltage of the sub-word line of circuit 3 controls be have with sub-word select select the identical level of signal A voltage or for and the identical voltage of control voltage VNN.Voltage control circuit 4 produces control voltage VNN with the transfering transistor Tr in the deactivation storage voltage 2.Hereinafter will describe control voltage VNN and voltage control circuit 4 in detail.Signal A is selected in sub-word select provides the guiding voltage that is higher than supply voltage to activate the transfering transistor Tr in the storage unit 2.
Selecting the grid of the nmis transistor N2 in the circuit 3 for sub-word line voltage provides sub-word select to select signal B, and the source electrode of transistor N2 links to each other with control voltage VNN, and drain electrode links to each other with sub-word line.Particularly, nmis transistor N2 controls sub-word select and selects signal B selecting the identical logical operation of signal with major word, thereby the voltage of sub-word line is set for controlling voltage VNN when above-mentioned phase inverter output control voltage VNN.
Voltage control circuit 4 produces the control voltage VNN that is used for deactivation MISFET and the control voltage that will produce offers a plurality of sub-word line voltages selection circuit 3.Voltage control circuit 4 comprises voltage generator (for example VNN voltage generator) 10 and unit leakage meter 20.VNN voltage generator 10 comprises datum generator 11, level detector 12 and output voltage generator 13.Datum generator 11 produces the datum voltage of control voltage VNN, and the voltage level of this datum voltage is controlled by level detector 12 and output voltage generator 13.Level detector 12 output control signals when this control signal reaches minimum value at the leakage current of MISFET substantially about device temperature, are controlled the magnitude of voltage of voltage VNN according to the change of grid voltage.Output voltage generator 13 produces control voltage according to control signal.20 pairs of unit leakage meters are formed on the leakage current that produces in the storage unit 2 in the memory cell array and regenerate.Then, unit leakage meter 20 comes output leakage current to detect voltage VA according to the current value of the leakage current of regeneration.Hereinafter describe voltage control circuit 4 in detail.
Storage unit 2 comprises transfering transistor Tr and capacitor C.Transfering transistor Tr has the grid that is connected to sub-word line, be connected to the first terminal of bit line and be connected to second terminal of the end of capacitor C.The other end of capacitor C is connected to the bias voltage with assigned voltage.
The feature of transfering transistor Tr is hereinafter described.For example transfering transistor Tr can be MISFET, and has the grid voltage shown in Figure 19-drain current feature.Particularly, at ambient temperature, the minimum value of leakage current is positioned at the Vg=0V place.At high temperature, can be that negative voltage minimizes leakage current by grid voltage Vg is set.According to the voltage on the sub-word line, transfering transistor Tr is in activity or inactive state.When having applied sub-word select and select signal A, activate transfering transistor Tr; When having applied control voltage VNN, deactivation transfering transistor Tr.In order to prolong the charge retention time of the capacitor C among the DRAM 1, need when transfering transistor Tr inertia, reduce leakage current.Leakage current comprises the above-described sub-threshold current leakage that flows, flows to drain diffusion layer junction leakage and band-band (band to band) tunnel leakage current of substrate regions from the drain region between source region and drain region.The feature that the combination of these leakage currents has is: leakage current is located minimum at the grid voltage Vg (Id_min) of regulation.Grid voltage Vg (Id_min) changes along with the variation of device temperature.Fig. 2 shows the relation between grid voltage Vg (Id_min) and the device temperature.
Grid voltage Vg (Id_min) shown in Fig. 2 is that experimental result by the inventor obtains about the variation characteristic of device temperature.The inventor finds, when the temperature T of semiconductor integrated circuit apparatus was in 0 ℃ to 100 ℃ scope, grid voltage Vg (Id_min) changed linearly about device temperature.Following expression 1 can be similar to and obtain grid voltage Vg (Id_min):
Vg(Id_min)<T>∝-α*T
Vg (Id_min)＜T wherein〉Vg (Id_min) under the indication equipment temperature T (Celsius thermometric scale or Kelvin scale), and α be by process or device structure determine greater than 0 constant (V/ ℃ or V/K).In the NMISFET that the experiment by the inventor produces, the value of α is approximately 0.01 (unit of T be ℃).
Following expression 2 can be similar to and obtain feature shown in Figure 2:
Vg(Id_min)<T>＝-α*T+β
Wherein β is constant (unit is V), under this β value during as T=TO, and Vg (Id_min)=0.T0 can not be an environment temperature.
Particularly, be set to identical with grid voltage Vg (Id_min) substantially by controlling voltage VNN, or, can not consider that device temperature minimizes leakage current by variation among the control voltage VNN and the variation among the grid voltage Vg (Id_min) are carried out real balance respectively about device temperature.In this embodiment, control voltage VNN is produced by voltage control circuit 4, so voltage control circuit 4 can change control voltage VNN.Hereinafter describe voltage control circuit 4 in detail.
Fig. 3 is the block diagram of voltage control circuit 4.Voltage control circuit 4 comprises datum generator 11, level detector 12 and output voltage generator 13.Datum generator 11 is provided with the voltage level of datum voltage VNNref.Datum voltage VNNref is input to level detector 12 and compares with control voltage VNN.Datum voltage VNNref does not rely on temperature.Level detector 12 detects the level of control voltage VNN based on the difference of the control voltage VNN of datum voltage VNNref and voltage control circuit 4 generations.Based on testing result, level detector output control signal.Output voltage generator 13 comprises ring oscillator 14 and charge pump circuit 15.Ring oscillator 14 produces the clock signal with assigned frequency consistent with the output control signal of level detector 12.Charge pump circuit 15 is according to the voltage level of the frequency control voltage VNN of the clock signal of ring oscillator 14 generations.
Each parts in the voltage control circuit 4 are hereinafter described in further detail.Fig. 4 shows the block diagram of an example of datum generator 11.As shown in Figure 4, datum generator 11 comprises that a plurality of resistors (for example resistor R 111, R112, R1111, R1112, R1121, R1122), a plurality of line as the level setting element change element (for example fuse F1111, F1112, F1121, F1122) and impact damper 111.
A plurality of resistors are connected between supply voltage VDD and the ground voltage VSS in the mode of series connection.In this embodiment, resistor is connected to ground voltage VSS according to the order of R1111, R1112, R111, R112, R1121 and R1122 from supply voltage VDD.Fuse F1111 is in parallel with resistor R 1111, and fuse F1112 is in parallel with resistor R 1112, and fuse F1121 is in parallel with resistor R 1121, and fuse F1122 is in parallel with resistor R 1122.Impact damper 111 is amplifiers, and wherein output terminal and inverting input are connected with each other.The non-oppisite phase end of amplifier links to each other with node between resistor R 111 and the R112.The voltage that buffer circuits 111 is provided with by a plurality of resistors by its output terminal output is as reference level voltage VNNref.
When connecting fuse, fuse is as lead.When disconnecting fuse, the two ends of fuse are electrically isolated from one another.Can for example using after making semiconductor equipment, the instrument of laser cutting machine disconnects fuse.If fuse is disconnected, become effectively with this fuse parallel resistor device.Though this embodiment uses fuse as example, also can use after manufacturing, to change other element that connects, for example short circuit fuse (for example Zener zinc anode plate, zener zap) and on-off element.
As another example of reference level generator 11, can use the storer of ROM (ROM (read-only memory)) for example to keep the setting of reference voltage.In this case, need determine to use which setting among the ROM by external control signal.As long as can change the reference voltage to produce after making semiconductor equipment, datum generator 11 is not limited to that shown in Fig. 4.
Hereinafter describe level detector 12 in detail.Fig. 5 shows the circuit diagram of level detector 12.Level detector 12 comprises reference voltage generator 121, comparison voltage generator 122 and comparer 124.Reference voltage generator 121 comprises constant current source I1 and first resistor (for example resistor R 121).Constant current source I1 and resistor 121 are connected between supply voltage VDD and the ground voltage GND in the mode of series connection, and reference voltage Vref N exports from the node between constant current source I1 and the resistor R 121.For example, the current value I 1 of constant current source I1 does not change with temperature.For example, resistor R 121 can be formed and had the negative temperature feature by polysilicon, and promptly resistance value reduces with a certain speed when device temperature rises.Therefore, reference voltage generator 121 produces voltage: I1*R1=VrefN.Reference voltage Vref N has the temperature profile corresponding to the temperature profile of resistor R 121.
In comparison voltage generator 122, voltage division element 123 is connected and is used to import the terminal of datum voltage VNNref and be used between the terminal of input control voltage VNN.For example in voltage division element 123, resistor R 122 and resistor R 123 are connected, and comparative voltage Vcomp exports from the node between resistor R 122 and the resistor R 123.Resistor R 122 and R123 can be formed and had the negative temperature feature by polysilicon, and promptly resistance value reduces with a certain speed when device temperature rises.Therefore, comparison voltage generator 122 produces voltage: VNN+ (R123/ (R122+R123)) * (VNNref-VNN)=Vcomp.Because resistor R 122 and R123 do not change with device temperature with a certain rate variation comparative voltage Vcomp about device temperature.Comparative voltage Vcomp divides comparison datum voltage VNNref by the resistor R 122 and the impedance of resistor R 123 to divide the value that obtains with control voltage VNN.
Like this, voltage control circuit 4 produces control voltage VNN, and VNN depends on the temperature profile of the datum voltage VNNref in the level detector 12 and changes.Control voltage VNN has the value that is provided with by datum voltage VNNref and resistor R 121 to R123.Fig. 6 shows the example that control voltage VNN changes about device temperature.In this embodiment, as shown in Figure 6, control voltage VNN is set to identical actually about the variation of device temperature with grid voltage Vg (Id_min) about the variation of device temperature.
If DRAM comprises a plurality of memory cell arrays, can arrange voltage control circuit 4 for each memory cell array.Selectively, can arrange voltage control circuit 4 for each word line that links to each other with each storage unit.
Hereinafter describe unit leakage meter 20 in detail.Fig. 7 shows the block diagram of unit leakage meter 20.As shown in Figure 7, unit leakage meter 20 comprises imaginary unit 21, PMIS transistor P21 to P23 and nmis transistor N21 and N22.For example, imaginary unit 21 can have the leakage current checkout area effect transistor (for example empty transistor) with transfering transistor Tr similar number, and wherein this transfering transistor Tr links to each other with a sub-word line in the memory cell array.Empty transistorized source electrode is connected respectively to bias voltage (for example half of supply voltage VDD), and drain electrode links together.Empty transistorized grid links to each other with dummy wordlines, dummy.Dummy wordlines, dummy has the control voltage VNN that the VNN voltage generator produces.Preferably, unit leakage meter 20 be placed near the memory cell array or memory cell array in.Preferably, shape and the size of the transfering transistor Tr in each empty transistorized shape and size and the storage unit 2 are practically identical.This allows the leakage current that the storage unit in the memory cell array 2 produces is carried out accurate reproduction.
The source terminal of PMIS transistor P21 and P22 links to each other with supply voltage VDD.The gate terminal of PMIS transistor P21 and P22 is connected with each other.Gate terminal and the drain terminal of PMIS transistor P21 are connected with each other.The drain terminal of PMIS transistor P21 is connected to the common node that the empty transistor drain terminal in the imaginary unit 21 links to each other jointly.The drain terminal of PMIS transistor P22 is connected to and is used for the terminal that output leakage current detects voltage VA.
The source terminal of PMIS transistor P23 links to each other with supply voltage VDD.The gate terminal of PMIS transistor P23 has voltage Vconst, and the electric current of exporting from the drain terminal of PMIS transistor P23 on voltage Vconst is actually the not constant of temperature influence.The drain terminal of PMIS transistor P23 links to each other with the drain terminal of nmis transistor N22.The source terminal of nmis transistor N21 and N22 links to each other with ground voltage VSS.The gate terminal of nmis transistor N21 and N22 is connected with each other.Gate terminal and the drain terminal of nmis transistor N22 are connected with each other.The drain terminal of nmis transistor N21 links to each other with the terminal that is used for output leakage current detection voltage VA.
Voltage leakage meter 20 is according to the voltage level of the control voltage VNN leakage current (this leakage current is to be produced by the storage unit 2 that forms on the memory cell array) of regenerating, and according to the current value output voltage (for example leakage current detects voltage VA) of leakage current.Particularly, the control module VNN that unit leakage meter 20 will offer unselected storage unit 2 offers the empty transistorized grid in the imaginary unit 21, thus the leakage current that uses imaginary unit 21 to regenerate and produce in the storage unit 2.Current mirror by PMIS transistor P21 and P22 exports the electric current of regeneration as leakage current IA.In addition, the temperature independent constant current Iconst of PMIS transistor P23 output.Current mirror by nmis transistor N21 and N22 comes output current Iconst.Therefore, unit leakage meter 20 detects voltage VA by its output terminal output voltage as leakage current, and wherein VA is based on the ratio of leakage current IA and electric current I const.
Fig. 8 shows the relation between control voltage VNN and the leakage current IA.As shown in Figure 8, leakage current IA reduces along with the increase of control voltage VNN and reaches minimum value when voltage VNN is in specified level when controlling.Then, when control voltage VNN surpassed specified level (leakage current IA minimum herein), leakage current IA increased thereupon.
Fig. 9 shows the relation between control voltage VNN and the leakage current detection voltage VA.As shown in Figure 9, leakage current detection voltage VA reduces along with the increase of control voltage VNN and reaches minimum value when voltage VNN is in specified level when controlling.Then, when control voltage VNN surpassed specified level (leakage current detects voltage VA minimum) herein, leakage current detects voltage VA to be increased thereupon.
In this embodiment, unit leakage meter 20 detects leakage currents control voltage VNN hour, and VNN voltage generator 10 produces leakage currents control voltage VNN in fact hour.If the value of control voltage VNN is that leakage current is the magnitude of voltage of minimum value under this voltage, VNN voltage generator 10 can change the value of control voltage VNN according to temperature so.The method of the initial value that control voltage VNN is set is hereinafter described.
For the initial value of control voltage VNN is set, when VNN voltage generator 10 stops, applying the voltage of regulation at watch-dog contact 1 place that links to each other with VNN voltage generator 10.Then, use the watch-dog contact 2 that links to each other with the output terminal of unit leakage meter 20 to monitor leakage current and detect voltage VA, detect the value that in fact voltage VA is in the control voltage VNN at minimum value place thereby detect at leakage current.In addition, suitably change the setting of fuse in the datum generator 11 or ROM so that datum voltage VNNref is adjusted into detected magnitude of voltage.Thereby the initial value of controlling voltage VNN is set to leakage current in the storage unit 2 is actually minimum value at this initial value place value.
As mentioned above, among the DRAM 1 in first embodiment, Control of Voltage electric current 4 produces control voltage VNN, and when the MISFET inertia, VNN will be applied to grid.Control voltage VNN is set to the practically identical value of grid voltage Vg (Id_min) with the minimum place of leakage current.In addition, control voltage VNN is set to identical actually about the variation of device temperature with grid voltage Vg (Id_min) about the variation of device temperature.Therefore, even device temperature changes, the DRAM 1 among first embodiment also can keep minimum leakage current under each device temperature.Therefore, the DRAM 1 among first embodiment can be in the holding state under the arbitrary temp minimizing power dissipation.
Owing to the value of α and β along with process or device structure change, the LSI deviser can obtain these values by measuring in advance.If changed substrate voltage, voltage Vg (Id_min) changes so.Like this, the temperature by measuring voltage Vg (Id_min) in advance relies on, and the LSI deviser can allow to control voltage VNN and have feature corresponding to the voltage Vg (Id_min) of relevant device.Yet the change of substrate voltage has influenced the drain diffusion layer junction leakage component in the subdomain value electric current to a great extent.Therefore, the grid voltage of describing among first embodiment can not be applied to substrate voltage simply about the change of temperature.In the substrate voltage/grid voltage of the substrate voltage/grid voltage of Kong Zhi substrate voltage/grid voltage, control at high temperature and control at low temperatures each all has optimum combination at ambient temperature.In addition, for example by implementing control to substrate voltage with the circuit of voltage control circuit 4 same way as operations.Hereinafter describe control in detail to substrate voltage.
Among the DRAM 1 in first embodiment, control voltage VNN can be a negative voltage.Even control voltage VNN is a negative voltage, the voltage of sub-word line is switched to sub-word select from control voltage VNN select the time of signal A and also can not prolong, unless the grid voltage of MISFET is provided with lowly excessively.Therefore, this embodiment can reduce leakage current and not sacrifice the access speed of storage unit 2.
Preferably, the scope that is provided with of control voltage VNN withstand voltage less than gate insulator.For example, if the grid voltage of control voltage VNN and NMISFET has surpassed the withstand voltage of gate insulator, this will destroy element.In addition, if the voltage difference between the drain electrode of MISFET and the source electrode greater than rated voltage, element loss in time becomes serious.Trouble-proof cycle is called as TDDB (relying on the dielectric breakdown of time, the TimeDependent Dielectric Breakdown) life-span in the little and element of loss influence in time.Preferably, control voltage VNN is set to can not shorten in the scope in TDDB life-span.
This embodiment detects the variation of leakage current about device temperature, and controls voltage VNN and be set to identical actually about the variation of device temperature with leakage current about the variation of device temperature.Selectively, can on semiconductor substrate, form, and the value of control voltage VNN is set and control the variation of voltage VNN about device temperature according to the feature of reference MISFET with reference to MISFET.
Second embodiment
Measure the value of leakage currents control voltage VNN hour according to the voltage control circuit 4 of first embodiment by unit leakage meter 20, and the initial value of control voltage VNN is set based on measurement result.On the other hand, measure the DRAM leakage current of operating period, and measurement result is reflected to the value of control voltage VNN according to the voltage control circuit 4a of second embodiment of the invention.Like this, the voltage control circuit 4a among second embodiment has realized the automatic control to the value of control voltage VNN.
Hereinafter will describe voltage control circuit 4a in detail.Figure 10 shows the block diagram of voltage control circuit 4a.As shown in figure 10, except according to the element in the voltage control circuit 4 of first embodiment, voltage control circuit 4a also comprises the second unit leakage meter (for example unit leakage meter 20b), level shifter 30 and comparer 40.First module leakage meter (for example unit leakage meter 20a) is corresponding to the unit leakage meter 20 among first embodiment, but it is represented so that it is distinguished mutually with unit leakage meter 20b by different reference symbols.Unit leakage meter 20a and 20b be with first embodiment in the substantially identical circuit of unit leakage meter 20.
Among the voltage control circuit 4a in a second embodiment, VNN voltage generator 10 is operated based on the difference that leakage current detects between voltage VA and the leakage current detection voltage VB, wherein export VA, come output voltage V B according to the voltage VNN2 that obtains from control voltage VNN displacement according to control voltage VNN.This operation is hereinafter described.
Figure 11 shows the relation of the voltage that produces among the voltage control circuit 4a.The chart on Figure 11 top shows the relation between control voltage VNN and leakage current detection voltage VA and the VB.In this chart, the curve that leakage current detects voltage VB is the displacement form that leakage current detects the curve of voltage VA.Therefore, to detect the minimum value of voltage VB be to detect the value that the minimum value displacement of voltage VA obtains from leakage current to leakage current.Leakage current detects the curve of voltage VA and the curve of leakage current detection voltage VB has intersection point.Corresponding to the control voltage VNN (being the voltage Vg_set1 among Figure 11) of the intersection point output change point of device 40 as a comparison.Preferably, this intersection point approaches the value that leakage current detects voltage VA control voltage VNN in fact hour.
Chart in the middle of Figure 11 shows the relation between the output voltage V C that controls voltage VNN and comparer 40.When control voltage VNN was higher than voltage Vg_set1, output voltage V C was a high level; When control voltage VNN was lower than voltage Vg_set1, output voltage V C was a low level.
The chart of Figure 11 bottom shows the relation between the datum voltage VNNref that controls in voltage VNN and the datum generator 11.Datum voltage VNNref is the reversing form of output voltage V C.When datum voltage VNNref was high level, 10 work of VNN voltage generator were to increase control voltage VNN.On the other hand, when datum voltage VNNref was low level, the work of VNN voltage generator was to reduce to control voltage VNN.
Therefore, the voltage control circuit 4a among second embodiment automatically changes control voltage VNN, thus the approximate voltage Vg_set1 that obtained.Voltage Vg_set1 is set to leakage current and detects the scope that voltage VA is actually hour.Therefore, the voltage control circuit 4a among second embodiment can be under situation about needn't carry out as the initial setting up among first embodiment, and the leakage current that keeps producing in the storage unit 2 is actual minimum value.
The 3rd embodiment
Figure 12 is the circuit diagram according to the level detector 12a of the 3rd embodiment.As shown in figure 12, among the level detector 12a in the 3rd embodiment, voltage division element 123a is connected and is used to import the terminal of datum voltage VNNref and be used between the terminal of input control voltage VNN.In voltage division element 123a, resistor R 122, R1221, R1222, R123, R1231 and R1232 series connection, comparative voltage Vcomp exports from the node between resistor R 122 and the resistor R 123.In addition, fuse F1221, F1222, F1231 and F1232 are in parallel with resistor R 1221, R1222, R1231 and R1232 respectively.
In this configuration, comparison voltage generator 122a among the 3rd embodiment can measure control voltage VNN (for example transporting in the checking process) after making semiconductor integrated circuit apparatus, and if the value that measures can adjust this value when being different from expectation value.If the control voltage VNN that measures is lower than expectation value, this adjustment can disconnect any fuse that connects on this side of datum voltage VNNref so.
Hereinafter describe and disconnect fuse F1221 to adjust the situation of control voltage VNN by example.Suppose that control voltage VNN is lower than datum voltage VNNref.Disconnect fuse F1221 comparative voltage Vcomp before and be expressed as VNN+ (R123/ (R122+R123)) * (VNNref-VNN).On the other hand, disconnect fuse F1221 comparative voltage Vcomp afterwards and be expressed as VNN+ (R123/ (R122+R1221+R123)) * (VNNref-VNN).Therefore, when disconnecting fuse, comparative voltage Vcomp becomes less value.Thereby 4 work of the voltage control circuit among the 3rd embodiment are to increase control voltage VNN.
Not only the tripper by for example fuse changes resistance value, can also be set to the effective or invalid resistance value that changes by the excitation resistor by the exciting bank of for example Zener zinc anode plate.
As mentioned above, the DRAM 1 among the 3rd embodiment can more accurately produce control voltage VNN than the DRAM among first embodiment 1.In addition, accurately produce control voltage VNN and can further reduce leakage current than first embodiment.
The 4th embodiment
In the level detector 12 in first embodiment, reference voltage Vref N is produced by resistor R 121 and constant current source I1.But among the level detector 12b in the fourth embodiment of the present invention, reference voltage Vref N is produced by the field effect transistor (for example MISFET) and the constant current source I1 of regulation shape.For example, the MISFET of regulation shape has and the practically identical shape of field effect transistor that forms storage unit.Therefore, the level detector 12b among the 4th embodiment obtains the resistor R 121 among alternative first embodiment of the MISFET of regulation shape.Figure 13 shows the circuit diagram according to the level detector 12b of the 4th embodiment.Element among the element except level detector 12b and first embodiment is practically identical, does not do specific descriptions here.
As shown in figure 13, the level detector 12b among the 4th embodiment comprises reference voltage generator 121b.Reference voltage generator 121b comprises constant current source I1 and a plurality of empty transistor.Constant current source I1 is in fact identical with constant current source I1 among first embodiment.Among a plurality of MISFET each has gate terminal, the first terminal (for example drain terminal) that links to each other with constant current source I1 and second terminal that links to each other with the bias voltage with assigned voltage (for example source terminal) that links to each other with ground voltage GND.Each empty transistor all is a field effect transistor, have with storage unit 2 in the practically identical shape of transfering transistor Tr used.
The empty transistor right and wrong activity of Lian Jieing by this way, and have leakage current to flow through therein.By leakage current is converted to impedance, can regard empty transistor as resistor element equivalently.Therefore, empty transistor can be regarded as equivalent resistor among the transfering transistor Tr that is in inactive state.Equivalent resistor in the empty transistor that the is connected to constant current source I1 combined impedance when in parallel is regarded in the impedance that a plurality of empty transistors can be connected to constant current source I1 place as.
In addition, if it is identical with the number of the storage unit that is connected to a sub-word line to be connected to the empty transistorized number of constant current source I1, can regard the storage unit that is connected to a sub-word line as practically identical equivalent resistor with the empty transistor that is connected to constant current source I1 so.In this case, if it is identical actually with empty transistorized layout to be connected to the layout of the transfering transistor Tr in the storage unit 2 of a sub-word line, so preferably, the relative accuracy that is used for further balanced equiva lent impedance increases.
By reference voltage Vref N and comparative voltage Vcomp are compared, level detector 12b is to ring oscillator 14 output control signals, wherein reference voltage Vref N is produced by empty transistor and constant current source I1, and comparative voltage Vcomp is produced by impedance division and the datum voltage VNNref of control voltage VNN.If device temperature uprises, the sub-word voltage in the storage unit (leakage current is in fact minimum herein) becomes bigger than negative voltage one side.In this embodiment, produce reference voltage Vref N based on the empty transistorized equiva lent impedance in the inactive state, wherein empty transistor have with storage unit 2 in the practically identical shape of transfering transistor Tr.Therefore, if the equiva lent impedance of inactive transfering transistor Tr reduces owing to the rising of device temperature, the transistorized equiva lent impedance of so inactive void reduces thereupon, and the voltage VrefN that has produced also reduces thereupon.As a result, the control voltage VNN that is produced by voltage control circuit 4 diminishes.
As mentioned above, by the transistorized equiva lent impedance of inactive void, level detector 12b among the 4th embodiment has realized selecting with sub-word line voltage the equiva lent impedance of the non-active storage unit 2 that circuit 3 links to each other, and uses inactive empty transistor to produce reference voltage Vref N.Based on reference voltage Vref N, level detector 12b output is used to the control signal of the value of control voltage VNN, this has enabled the control of the control voltage VNN that voltage control circuit 4 is produced, so that to selecting the leakage current in the storage unit 2 that circuit 3 links to each other to minimize actually with sub-word line voltage.
Though the empty transistor among the 4th embodiment has substituted the resistor R 121 in the level detector 12 among first embodiment, can substitute resistor R 122 or R123 in the level detector 12 among first embodiment with imaginary unit.
The 5th embodiment
DRAM according to fifth embodiment of the invention controls the voltage (for example controlling voltage VNN) except controlling first, also the second control voltage (for example substrate voltage Vsub) of the transfering transistor Tr in the control store unit 2.Substrate voltage Vsub offers transistorized back gate terminal.Figure 14 shows substrate voltage Vsub among the transfering transistor Tr and the relation between the drain current.As shown in figure 14, when substrate voltage Vsub became negative value, the grid voltage Vg (Id_min) at the minimum place of drain current was greater than its value when the substrate voltage Vsub=0.Figure 15 shows the substrate voltage Vsub (Id_min) at the minimum place of leakage current and the relation between the temperature variation.As shown in figure 15, substrate voltage Vsub (Id_min) reduces along with the rising of temperature.
Therefore, in order to minimize leakage current, be that constant makes substrate voltage Vsub reduce according to temperature by the grid voltage that is provided with among the transfering transistor Tr.In the above-described embodiments, control voltage VNN reduces according to temperature.Yet, the high level voltage that the reducing of control voltage VNN enlarged sub-word line with control poor between the voltage VNN, this has hindered high speed operation.Present embodiment is controlled substrate voltage Vsub and control voltage VNN simultaneously, thereby has realized high speed operation and reduced leakage current simultaneously.
Figure 16 is the block diagram according to the voltage control circuit 4b of the 5th embodiment.As shown in figure 16, voltage control circuit 4b comprises first voltage generator (for example VNN voltage generator) 10a, second voltage generator (for example Vsub voltage generator) 10b, the first and second unit leakage meters (for example unit leakage meter 20c and 20d), level shifter 30a and 30b, comparer 40 and switch SW 1 and SW2.VNN voltage generator 10a, Vsub voltage generator 10b and unit leakage meter 20c and 20d in fact respectively with first embodiment in VNN voltage generator 10 and unit leakage meter 20 are identical circuit.Level shifter 30a, 30b and comparer 40 in fact respectively with second embodiment in level shifter 30 and comparer 40 are identical circuit.For convenience of description, the reference symbol of these parts is different.
The substrate voltage Vsub of the Vsub voltage generator 10b output from present embodiment offers memory cell array, as the substrate voltage of the transfering transistor in the memory cell array.Substrate voltage Vsub also offers imaginary unit 21, as the empty transistorized substrate voltage Vsub among unit leakage meter 20c and the 20d.Unit leakage meter 20c receives the substrate voltage Vsub that is produced by Vsub voltage generator 10b.On the other hand, unit leakage meter 20d receives substrate voltage Vsub2, and the substrate voltage Vsub that Vsub2 produces Vsub voltage generator 10b is shifted and obtains.
Relation between substrate voltage Vsub and each voltage is hereinafter described.Control voltage VNN and leakage current detect identical described in the relation between voltage VA and the VB and second embodiment, no longer description here.Figure 17 shows each voltage that produces among the voltage control circuit 4b and the relation between the substrate voltage Vsub.The chart on Figure 17 top shows the relation between substrate voltage Vsub and leakage current detection voltage VA and the VB.In this chart, the curve that leakage current detects voltage VB is the displacement form that leakage current detects the curve of voltage VA.Therefore, to detect the minimum value of voltage VB be that the minimum value that leakage current detects voltage VA is carried out translation and the value that obtains to leakage current.Leakage current detects the curve of voltage VA and the curve of leakage current detection voltage VB has intersection point.Corresponding to the substrate voltage Vsub (being the voltage Vg_set2 among Figure 17) of this intersection point as a comparison the output of device 40 change point.Preferably, this intersection point approaches leakage current and detects voltage VA substrate voltage Vsub in fact hour.
Figure 17 middle part shows the relation between the output voltage V C of substrate voltage Vsub and comparer 40.When substrate voltage Vsub was higher than voltage Vg_set2, output voltage V C was a high level; When substrate voltage Vsub was lower than voltage Vg_set2, output voltage V C was a low level.
Figure 17 bottom shows the relation between the datum voltage Vsubref among substrate voltage Vsub and the datum generator 11b.Datum voltage Vsubref is the anti-phase form of output voltage V C.When datum voltage Vsubref was high level, VNN voltage generator 10b work was to increase substrate voltage Vsub.On the other hand, when datum voltage Vsubref was low level, VNN voltage generator 10b worked to reduce substrate voltage Vsub.
Therefore, the voltage control circuit 4b among the 5th embodiment automatically changes substrate voltage Vsub, thus the approximate voltage Vg_set2 that obtains.Voltage Vg_set2 is set to leakage current and detects in the voltage VA scope in fact hour.Therefore, the voltage control circuit 4b among the 5th embodiment need not carry out leakage current that initial setting up among first embodiment also can keep producing in the storage unit 2 actually for minimum.
In addition, voltage control circuit 4b goes back control basal plate voltage Vsub except control control voltage VNN, thereby has suppressed the variation of control voltage VNN.Vsub is set to negative value by substrate voltage, and the grid voltage Vg (Id_min) at the minimum place of leakage current has moved on to higher level.So, the grid voltage Vg (Id_min) by after controlling voltage VNN and being set to be shifted can suppress to control the variation among the voltage VNN.This has reduced poor between high level voltage in the sub-word line and the control voltage VNN, thereby has enabled the high speed operation among the DRAM.
In the 5th embodiment, when device temperature in set point of temperature (for example environment temperature) following time, control voltage VNN and substrate voltage Vsub remain the constant of regulation.When device temperature surpasses set point of temperature, control voltage VNN and substrate voltage Vsub are controlled.Though this is that the quantity of leakage current does not cause the prominent question under the low device temperature because the significant increase of leakage current has caused the problem under the high device temperature.Do not carry out control when device temperature is low, this can reduce the current drain in the circuit.
In addition, when having carried out the refresh operation of stipulated number, the voltage control circuit 4b among the 5th embodiment just adjusts the voltage that will produce.Figure 18 shows the sequential chart of this operation.As shown in figure 18, in voltage control circuit 4b, when having carried out the refresh operation of stipulated number (for example N time among Figure 18), the alternately pulse of input control signal VNN_cont and the pulse (pulse of a refresh signal is corresponding to a refresh operation) of control signal Vsub_cont.The pulse of switch SW 1 responsive control signal VNN_cont and closure, the pulse of switch SW 2 responsive control signal Vsub_cont and closure.Therefore, when having carried out the refresh operation of stipulated number, voltage control circuit 4b progressively increases or reduces voltage.Thereby alternately carry out to the adjustment of control voltage VNN with to the adjustment of substrate voltage Vsub.
This has eliminated the demand that voltage control circuit is often operated, thereby has reduced power consumption.The embodiment of the voltage adjustment that replaces in addition, has been realized the effective coordinated manipulation of control voltage VNN and substrate voltage Vsub.
Preferably the substrate voltage Vsub forward voltage that is set to the parasitic diode among the MISFET is not in relation to substrate voltage or well voltage and mobile scope.For example, if substrate voltage is a ground voltage, controls voltage VNN so and be preferably-0.7V or higher.
The invention is not restricted to the foregoing description also can change in many ways.In the above-described embodiments, though the grid voltage of field effect transistor can change continuously according to temperature, can preset grid voltage with the value of being maintained fixed, for example be X[V at ambient temperature], be (X-A) [V] down at high temperature (for example 50 ℃ or higher), be (X+A) [V] down at low temperature (for example 0 ℃ or lower).Like this, if having with the circuit of voltage control circuit 4 identical functions uses finishing fuse to wait the X[V under the environment temperature according to creating conditions of equipment] change into (X-α) [V] or (X+ β) [V] and further change voltage under the environment temperature with respect to temperature, can obtain the optimal current feature of the equipment consistent so with temperature conditions.In addition, the invention is not restricted to the storer of DRAM for example or SRAM, can be applied to use for example any other circuit of the field effect transistor of logical circuit.
Though the foregoing description has been described the situation that transfering transistor Tr is formed by nmis transistor, transfering transistor Tr can be formed by the PMIS transistor.In this case, control voltage VNN and substrate voltage Vsub progressively increase in mode in contrast with the previous embodiment or reduce.Particularly, the present invention controls control voltage VNN and substrate voltage Vsub, so that based on reducing leakage current when controlling voltage VNN and the substrate voltage Vsub voltage when uncontrolled.This control has enlarged the absolute value of the difference of reference voltage.Preferably, can control control voltage VNN and substrate voltage Vsub independently of one another.
Be apparent that, the invention is not restricted to the foregoing description, and under the prerequisite that does not deviate from scope and spirit of the present invention, can make amendment and change embodiment.
Claims (20)
1. semiconductor integrated circuit apparatus comprises:
Field effect transistor; And
Voltage control circuit, its generation will offer gate terminal in the field effect transistor, be used for the control voltage of deactivation field effect transistor, voltage control circuit is controlled voltage according to device temperature, thereby minimizes be in the non-leakage current that flows through when movable at field effect transistor substantially.
2. semiconductor integrated circuit apparatus according to claim 1, thus wherein voltage control circuit control voltage will be minimized by subdomain value leakage current, drain diffusion layer junction leakage and the band-determined drain current of band tunnel leakage current in the field effect transistor under the temperature of regulation substantially.
3. semiconductor integrated circuit apparatus according to claim 1, wherein voltage control circuit control voltage makes it change linearly according to device temperature.
4. semiconductor integrated circuit apparatus according to claim 1, wherein voltage control circuit is controlled voltage based on following relation:
Vg(T)∝-α*T
Wherein Vg (T) is that T is a device temperature at the control voltage of the device temperature of regulation, and α is the constant of being determined by process or device structure.
5. semiconductor integrated circuit apparatus according to claim 1, wherein at least one is used as controlling voltage in the voltage control circuit generation first control voltage and the second control voltage, wherein the first control voltage is provided for the gate terminal of field effect transistor, and the second control voltage is provided for the back gate terminal of field effect transistor.
6. semiconductor integrated circuit apparatus according to claim 1, wherein voltage control circuit comprises:
The unit leakage meter, it is regenerated based on control voltage and is in the leakage current that produces in the field effect transistor of inactive state, and produces detection voltage according to the current value of leakage current; And
Voltage generator, it is provided with the magnitude of voltage of controlling voltage based on detecting voltage, and changes the magnitude of voltage of control voltage according to device temperature.
7. semiconductor integrated circuit apparatus according to claim 6, wherein the unit leakage meter comprises shape or the practically identical leakage current checkout area effect transistor of electric characteristic that has with field effect transistor, and produces detection voltage according to the current value of the leakage current that produces in the leakage current checkout area effect transistor.
8. semiconductor integrated circuit apparatus according to claim 7, wherein leakage current checkout area effect transistor is operated based on the control voltage of voltage generator output.
9. semiconductor integrated circuit apparatus according to claim 6, wherein voltage generator comprises the datum generator, be used to be provided with the datum of the voltage that will produce, described datum generator uses the level setting element of selecting from disconnect fuse, short circuit fuse, on-off element and logical storage circuit to store setting, and produces datum voltage according to the state of level setting element.
10. semiconductor integrated circuit apparatus according to claim 9, wherein, the state of level setting element is provided with according to detecting voltage.
11. semiconductor integrated circuit apparatus according to claim 6, wherein voltage control circuit comprises the first module leakage meter, is used for exporting first based on the control voltage of voltage generator output and detects voltage; And the second unit leakage meter, be used for exporting second and detect voltage based on the voltage that obtains according to the control voltage shift.
12. semiconductor integrated circuit apparatus according to claim 11, the control voltage phase difference tens that wherein is input to the output of the control voltage of the second unit leakage meter and voltage generator is to the hundreds of millivolt.
13. semiconductor integrated circuit apparatus according to claim 11, wherein voltage generator increases or reduces to control voltage based on first difference that detects between the voltage and the second detection voltage.
14. semiconductor integrated circuit apparatus according to claim 11 wherein whenever carries out the refresh operation of stipulated number, voltage control circuit just increases or reduces the control voltage of voltage generator output.
15. semiconductor integrated circuit apparatus according to claim 1, the field effect transistor that wherein has been applied in control voltage is the transfering transistor of storage unit.
16. semiconductor integrated circuit apparatus according to claim 15, wherein when control voltage was applied to gate terminal, transfering transistor became non-activity.
17. semiconductor integrated circuit apparatus according to claim 1, wherein the grid voltage of field effect transistor is the word voltage in the storage unit.
18. semiconductor integrated circuit apparatus according to claim 1 wherein is that each in a plurality of memory cell array blocks or each word line that links to each other with each storage unit have all been arranged voltage control circuit.
19. a semiconductor integrated circuit apparatus comprises:
Voltage control circuit is used to produce the control voltage of the gate electrode that will offer field effect transistor, and described voltage control circuit comprises:
Reference voltage generator, comprise the constant current source that output has the rated current value, with first resistor with the resistance value that changes with schedule speed at device temperature, described reference voltage generator produces at the reference voltage of device temperature with the schedule speed variation based on the electric current output of constant current source and the resistance value of first resistor;
Comparison voltage generator, the datum voltage that is used to receive control voltage and has the magnitude of voltage of regulation, described comparison voltage generator comprises the voltage division element with a plurality of resistors of connecting between the voltage in datum voltage and control, and by the impedance division ratio that utilizes the voltage division element difference between datum voltage and the control voltage is divided and to produce comparative voltage; And
Comparer, it exports the adjustment signal based on the difference between reference voltage and the comparative voltage,
Wherein, adjust the magnitude of voltage of control voltage based on adjusting signal.
20. a semiconductor integrated circuit apparatus comprises:
Voltage control circuit, its generation are used for the control voltage of deactivation field effect transistor, and described voltage control circuit comprises:
Level detector, its output is used for according to the next control signal that the magnitude of voltage of control voltage is controlled of the variation of grid voltage, under described grid voltage, when field effect transistor was in non-activity, the leakage current that flows through was essentially minimum value with respect to device temperature; And
Voltage generator, it produces control voltage according to control signal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP2005329692 | 2005-11-15 | ||
| JP2005329692 | 2005-11-15 | ||
| JP2006260834 | 2006-09-26 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106664091A (en) * | 2014-08-12 | 2017-05-10 | 赛灵思公司 | Interconnect circuits having low threshold voltage p-channel transistors for a programmable integrated circuit |
| CN111766913A (en) * | 2020-05-27 | 2020-10-13 | 北京新忆科技有限公司 | Control system of integrated circuit and integrated circuit |
| CN112053968A (en) * | 2020-08-27 | 2020-12-08 | 中国科学院微电子研究所 | Method and device for reducing high-temperature off-state leakage of semiconductor device |
-
2006
- 2006-11-15 CN CN 200610148592 patent/CN1983441A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106664091A (en) * | 2014-08-12 | 2017-05-10 | 赛灵思公司 | Interconnect circuits having low threshold voltage p-channel transistors for a programmable integrated circuit |
| CN111766913A (en) * | 2020-05-27 | 2020-10-13 | 北京新忆科技有限公司 | Control system of integrated circuit and integrated circuit |
| CN111766913B (en) * | 2020-05-27 | 2023-12-22 | 北京新忆科技有限公司 | Control system of integrated circuit and integrated circuit |
| CN112053968A (en) * | 2020-08-27 | 2020-12-08 | 中国科学院微电子研究所 | Method and device for reducing high-temperature off-state leakage of semiconductor device |
| CN112053968B (en) * | 2020-08-27 | 2022-07-08 | 中国科学院微电子研究所 | Method and device for reducing high-temperature off-state leakage of semiconductor device |
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