CN1982997A - Thin-film transistor base plate and its production - Google Patents
Thin-film transistor base plate and its production Download PDFInfo
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- CN1982997A CN1982997A CN 200510120679 CN200510120679A CN1982997A CN 1982997 A CN1982997 A CN 1982997A CN 200510120679 CN200510120679 CN 200510120679 CN 200510120679 A CN200510120679 A CN 200510120679A CN 1982997 A CN1982997 A CN 1982997A
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- film transistor
- base plate
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- metal
- transistor base
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Abstract
A base plate of film transistor consists of an insulation substrate, a grid line, a storage capacity-electrode line, insulation layer and pixel electrode. It is featured as forming a storage capacity by storage capacity-electrode line and pixel electrode, forming grid line by the first metal layer and the second metal layer set on the first one, applying metal with high reflectivity as material of the first metal layer and said storage capacity-electrode line.
Description
[technical field]
The present invention relates to a kind of thin film transistor base plate, also relate to a kind of thin film transistor base plate manufacture method.
[prior art]
At present, LCD replaces conventional cathode ray tube (the Cathode Ray Tube that is used for counter gradually, CRT) display, and owing to characteristics such as the liquid crystal display utensil are light, thin, little, make its be fit to very much be applied to desktop PC, personal digital assistant (Personal Digital Assistant, PDA), in TV and multiple office automation and the audio-visual equipment.Liquid crystal panel is its primary clustering, its generally comprise a thin film transistor base plate, a colored filter substrate and be sandwiched in this thin film transistor base plate and this colored filter substrate between liquid crystal layer.
Seeing also Fig. 1, is the floor map of the thin film transistor base plate 100 of a prior art.This thin film transistor base plate 100 comprises many gate lines 110, many data lines 120 and many storage capacitor electrode lines 150.120 insulation of many data lines of these many gate lines 110 and this are intersected, and define a plurality of pixel cells (not indicating).Each pixel cell correspondence is provided with a pixel electrode 140 and a thin film transistor (TFT) 130.This thin film transistor (TFT) 130 is arranged on this gate line 110 and these data line 120 intersections, and it comprises a grid 131, one source pole 132 and a drain electrode 133.This grid 131 is to link to each other with these gate line 110 one, and this source electrode 132 is electrically connected with this data line 120, and this drain electrode 133 is electrically connected with this pixel electrode 140.This storage capacitor electrode line 150 is parallel with this gate line 110, and it passes this pixel cell.
Seeing also Fig. 2, is the diagrammatic cross-section along line II-II shown in Figure 1.This thin film transistor base plate 100 also comprises a dielectric base 101, a gate insulator 102, semiconductor layer 103 and a passivation layer 104 corresponding with each thin film transistor (TFT) 130.This grid 131, gate line 110 and this storage capacitor electrode line 150 are arranged on this dielectric base 101; This gate insulator 102 is arranged on this grid 131, gate line 110, this storage capacitor electrode line 150 and this dielectric base 101; 103 pairs of this semiconductor layers should be arranged on this gate insulator 102 by grid 131; This source electrode 132 and this drain electrode 133 are arranged on this semiconductor layer 103, and this source electrode 132 and this drain electrode 133 are separately positioned on the both sides of this semiconductor layer 103; This passivation layer 104 is arranged on this source electrode 132, this drain electrode 133, this semiconductor layer 103 and this gate insulator 102, this pixel electrode 140 is arranged on this passivation layer 104, it is electrically connected with this drain electrode 133 by a connecting hole 105 that penetrates this passivation layer 104, and itself and this storage capacitor electrode line 150 couplings form a memory capacitance.
The material that this pixel electrode 140 adopts is that (Indium Tin Oxide, ITO), this gate line 110 will be that the connecting line (figure does not show) of ITO is electrically connected with external drive circuit by material to indium tin oxide.This gate line 110 and this storage capacitor electrode line 150 are positioned at same level, in processing procedure, form simultaneously, and adopt identical materials molybdenum (Mo), and electrochemical reaction can not take place with ITO in molybdenum, so can avoid this gate line 110 and this connecting line generation electrochemical reaction.
Yet this storage capacitor electrode line 150 is arranged on the zone of pixel cell, and molybdenum is light tight material, and reflectivity is lower, makes that this pixel cell brightness reduces when showing.
[summary of the invention]
Problem for the pixel cell brightness that solves above-mentioned thin film transistor base plate reduces is necessary to provide a kind of thin film transistor base plate that improves pixel cell brightness.
Also be necessary to provide a kind of employing above-mentioned manufacturing method of film transistor base plate.
A kind of thin film transistor base plate, it comprises a dielectric base, be arranged on a gate line on this dielectric base and a storage capacitor electrode line, is arranged on insulation course and on this gate line, this storage capacitor electrode line and this dielectric base and is arranged on pixel electrode on this insulation course, this storage capacitor electrode line and this pixel electrode form a memory capacitance, this gate line comprises a first metal layer and is positioned at second metal level on this first metal layer that the material of this first metal layer and this storage capacitor electrode line all is a high-reflectivity metal.
A kind of thin film transistor base plate manufacture method, its step comprises: a dielectric base is provided; Deposit a first metal layer, one second metal level and a photoresist layer successively on this first dielectric base, the material that this first metal layer adopts is the metal material of high reflectance; This photoresist layer is exposed and develops, form the different photoresist layer pattern of thickness; The unlapped the first metal layer of this photoresist layer and second metal level are etched away; This photoresist layer is carried out etching, etched away fully until this thin photoresistance, and this thicker photoresistance also has residue; Etch away unlapped second metal level of this photoresistance; Remove the residue photoresistance, to form gate line that constitutes by the first metal layer and second metal level and the storage capacitor electrode line that constitutes by this first metal layer.
Compared to prior art, this storage capacitor electrode line adopts the material of high reflectance, and it can reflect surround lighting, thereby can increase the brightness of this pixel cell when showing.This method forms this first metal layer and this second metal level in one light shield processing procedure, can not increase processing procedure.
[description of drawings]
Fig. 1 is the floor map of thin film transistor base plate one pixel cell of prior art.
Fig. 2 is the diagrammatic cross-section along line II-II shown in Figure 1.
The floor map of Fig. 3 thin film transistor base plate one pixel cell of the present invention.
Fig. 4 is the section enlarged diagram along line IV-IV shown in Figure 1.
Fig. 5 is the process flow diagram of thin film transistor base plate manufacture method of the present invention.
Fig. 6 is the synoptic diagram that the present invention forms the first metal layer and second metal level.
Fig. 7 is the synoptic diagram of the present invention's one light shield.
Fig. 8 is the synoptic diagram that the present invention forms the different photoresistance of thickness.
Fig. 9 carries out synoptic diagram after the etching to substrate shown in Figure 8.
Figure 10 carries out synoptic diagram after the etching to photoresistance shown in Figure 9.
Figure 11 is the synoptic diagram that the present invention forms a grid and storage capacitor electrode line.
Figure 12 is the synoptic diagram that the present invention forms gate insulator, amorphous silicon and doped amorphous silicon layer.
Figure 13 is the synoptic diagram that the present invention forms semiconductor layer pattern.
Figure 14 is the synoptic diagram that the present invention forms source/drain metal layer.
Figure 15 is the synoptic diagram that the present invention forms source/drain pattern.
Figure 16 is the synoptic diagram that the present invention forms passivation layer.
Figure 17 is the synoptic diagram that the present invention forms passivation layer pattern.
Figure 18 is the synoptic diagram that the present invention forms the transparent conductive metal layer.
Figure 19 is the synoptic diagram that the present invention forms pixel electrode.
[embodiment]
Seeing also Fig. 3, is the floor map of thin film transistor base plate 200 1 pixel cells of the present invention.This thin film transistor base plate 200 comprises many gate lines 210, many data lines 220 and many storage capacitor electrode lines 250.220 insulation of many data lines of these many gate lines 210 and this are intersected, and define a plurality of pixel cells (not indicating).Each pixel cell correspondence is provided with a pixel electrode 240 and a thin film transistor (TFT) 230.This thin film transistor (TFT) 230 is arranged on this gate line 210 and these data line 220 intersections, and it comprises a grid 231, one source pole 232 and a drain electrode 233.This grid 231 links to each other with these gate line 210 one, and this source electrode 232 is electrically connected with this data line 220, and this drain electrode 233 is electrically connected with this pixel electrode 240.
Seeing also Fig. 4, is the section enlarged diagram along line IV-IV shown in Figure 3.This thin film transistor base plate 200 also comprises a dielectric base 201, a gate insulator 202, semiconductor layer 203 and a passivation layer 204 corresponding with each thin film transistor (TFT) 230.This grid 231, gate line 210 and this storage capacitor electrode line 250 are arranged on this dielectric base 201; This gate insulator 202 is arranged on this grid 231, gate line 210, this storage capacitor electrode line 250 and this dielectric base 201; This semiconductor layer 203 should be arranged on this gate insulator 202 by grid 231 mutually; This source electrode 232 and this drain electrode 233 are arranged on this semiconductor layer 203, and this source electrode 232 and this drain electrode 233 are separately positioned on this semiconductor layer 203 both sides; This passivation layer 204 is arranged on this source electrode 232, this drain electrode 233, this semiconductor layer 203 and this gate insulator 202, this pixel electrode 240 is arranged on this passivation layer 204, it is electrically connected with this drain electrode 233 by a connecting hole 205 that penetrates this passivation layer 204, and itself and this storage capacitor electrode line 250 couplings form a memory capacitance.
The material that this pixel electrode 240 adopts be ITO or indium-zinc oxide (IndiumZinc Oxide, IZO).This gate line 210 and this grid 231 are the pair of lamina metal construction, second metal level 212 that it comprises the first metal layer 211 that equates with these storage capacitor electrode line 250 thickness and is positioned at these the first metal layer 211 tops.This gate line 210 will be that the connecting line (figure do not show) of ITO or IZO is electrically connected with external drive circuit by material.This first metal layer 211 is the metal material of high reflectance with the material that this storage capacitor electrode line 250 adopts, as silver (Ag), aluminium or aluminium neodymium alloy.This second metal level 212 can adopt material molybdenum, chromium (Cr) or titanium (Ti), and those materials can electrochemical reaction not take place with ITO or IZO at normal temperatures and pressures, so this second metal level 212 can prevent this gate line 210 and this connecting line generation electrochemical reaction.
Compared to prior art, this storage capacitor electrode line 250 adopts the material of high reflectance, and it can reflect surround lighting, thereby can increase the brightness of this pixel cell when showing; And this gate line 210 adopts double-decker, and this gate line 210 forms in the light shield processing procedure with this storage capacitor electrode line 250, and this second metal level 212 can prevent this gate line 210 and this connecting line generation electrochemical reaction.
Seeing also Fig. 5, is the process flow diagram of thin film transistor base plate manufacture method of the present invention.This manufacturing method of film transistor base plate comprises five road light shield processing procedures, and its concrete steps are as follows:
One, the first road light shield
(1) forms a first metal layer and second metal level (step S10);
See also Fig. 6, a dielectric base 301 is provided, this dielectric base 301 can be insulation materials such as glass, quartz or pottery; Deposition the first metal layer 311 on this dielectric base 301, this first metal layer 311 adopts the metal material of high reflectance, as silver, aluminium or aluminium neodymium alloy; Deposition one second metal level 312 on this first metal layer 311, but its material molybdenum, chromium or titanium; Deposition one first photoresist layer 341 on this second metal level 312.
(2) form gate pattern and storage capacitor electrode line pattern (step S11);
See also Fig. 7, aim at these first photoresist layer, 341 tops with the light shield 320 of the first road light shield processing procedure, with this first photoresist layer 341 of ultraviolet light parallel radiation.This light shield 320 is the slit light shield, and it comprises a plurality of slit reticle field 322 and a plurality of shading region 321.This photoresist layer 341 is developed again, thereby can form as shown in Figure 8 predetermined pattern on this first photoresist layer 341, promptly the part photoresistance 361 corresponding to this shading region 321 is thin corresponding to the part photoresistance 351 of this slit reticle field 322.
See also Fig. 9, this first metal layer 311 and this second metal level 312 are carried out etching, can remove the first metal layer 311 and second metal level 312 of remaining photoresistance 351 and 361 unmasked portions.
See also Figure 10, again this residue photoresist layer is carried out etching, the control etching period, so that etched away fully than thin part photoresistance 351 when this, and this thicker part photoresistance 361 also has residue.
See also Figure 11, etch away unlapped this second metal level 312 of photoresistance, remain this first metal layer 311, remove remaining photoresistance 361 again, promptly form the pattern of predetermined grid 331 and gate line 310 and storage capacitor electrode line 350.Clean back oven dry substrate 301.
Two, the second road light shield
(3) form gate insulator, amorphous silicon and doped amorphous silicon layer (step S12) in regular turn;
See also Figure 12, (Chemical VaporDeposition, CVD) method are utilized reactant gas silane (SiH4) and ammonia (NH3), form the gate insulator 302 that silicon nitride (SiNx) constitutes with chemical vapor deposition; On this gate insulator 302, form an amorphous silicon layer with chemical gaseous phase depositing process again; Carry out one doping process again, mix, form one deck doped amorphous silicon, thereby form amorphous silicon and doped amorphous silicon layer 313 on this amorphous silicon layer surface.
On this amorphous silicon and doped amorphous silicon layer 313, form one second photoresist layer 342.
(4) form semiconductor layer pattern (step S13);
See also Figure 13, aim at this second photoresist layer, 342 tops with the pattern of the second road light shield processing procedure, with this second photoresist layer 342 of ultraviolet light parallel radiation, thereby can on this second photoresist layer 342, form a predetermined pattern, this amorphous silicon and doped amorphous silicon layer 313 are carried out dry ecthing, to remove portion of amorphous silicon and doped amorphous silicon, formation one has the semiconductor layer 303 of predetermined pattern, removes remaining second photoresist layer 342.
Three, the 3rd road light shield
(5) formation source/drain metal layer (step S14);
See also Figure 14, deposit one source/drain metal layer 314 and one the 3rd photoresist layer 343 successively on this gate insulator 302 and this semiconductor layer 303, this source/drain metal layer 314 adopts molybdenum or molybdenum alloy to make.
(6) formation source/drain metal layer pattern (step S15);
See also Figure 15, aim at the 3rd photoresist layer 343 tops,, thereby can on the 3rd photoresist layer 343, form a predetermined pattern with ultraviolet light parallel radiation the 3rd photoresist layer 343 with the pattern of the 3rd road light shield processing procedure; This source/drain metal layer 314 is etched with the source electrode 332 that forms predetermined pattern and drains 333, and remove remaining the 3rd photoresist layer 343.
Four, the 4th road light shield
(7) form passivation layer (step S16);
See also Figure 16, deposition one deck passivation layer 304 on this source electrode 332, drain electrode 333 and this gate insulator 302, deposition one deck the 4th photoresist layer 344 on this passivation layer 304 again.
(8) form passivation layer pattern (step S17);
See also Figure 17, aim at the 4th photoresist layer 344 tops,, thereby can on the 4th photoresist layer 344, form a predetermined pattern with ultraviolet light parallel radiation the 4th photoresist layer 344 with the pattern of the 4th road light shield processing procedure; This passivation layer 304 is carried out etching, and formation has the passivation layer pattern of connecting hole 305.
Five, the 5th road light shield
(9) form transparent conductive metal layer (step S18);
See also Figure 18, deposition layer of transparent conductive metal layer 306 on this passivation layer pattern, the material that this transparent metal adopts can be ITO.This transparent metal conductive layer 306 is electrically connected with this drain electrode 333 by this connecting hole 305.On this transparent conductive metal layer 306, form one the 5th photoresist layer 345 again.
(10) form pixel electrode pattern (step S19);
See also Figure 19, to the 5th photoresist layer 345 tops,, thereby can on the 5th photoresist layer 345, form a predetermined pattern with ultraviolet light parallel radiation the 5th photoresist layer 345 with the pattern of the 5th road light shield processing procedure; This transparent metal conductive layer 306 is carried out etching, form the pixel electrode 340 of predetermined pattern.
Through above-mentioned steps, promptly form thin film transistor base plate.
Claims (10)
1. thin film transistor base plate, it comprises a dielectric base, be arranged on a gate line on this dielectric base and storage capacitor electrode line, is arranged on insulation course and on this gate line, this storage capacitor electrode line and this dielectric base and is arranged on pixel electrode on this insulation course, this storage capacitor electrode line and this pixel electrode form a memory capacitance, it is characterized in that: this gate line comprises a first metal layer and is positioned at second metal level on this first metal layer that the material of this first metal layer and this storage capacitor electrode line all is a high-reflectivity metal.
2. thin film transistor base plate as claimed in claim 1 is characterized in that: the material that this second metal level adopts be under the normal temperature and pressure not with the material of indium tin oxide or indium-zinc oxide generation electrochemical reaction.
3. thin film transistor base plate as claimed in claim 2 is characterized in that: the material that this second metal level adopts is a kind of of following material: molybdenum, chromium and titanium.
4. thin film transistor base plate as claimed in claim 1 is characterized in that: the material that this pixel electrode adopts is indium tin oxide or indium-zinc oxide.
5. thin film transistor base plate as claimed in claim 1 is characterized in that: the material of this storage capacitor electrode is a kind of of following material: silver, aluminium and aluminium neodymium alloy.
6. thin film transistor base plate as claimed in claim 1, wherein, this storage capacitor electrode line and this first metal layer adopt same material.
7. manufacturing method of film transistor base plate, it comprises:
One dielectric base is provided;
Deposit a first metal layer, one second metal level and a photoresist layer successively on this dielectric base, the material that this first metal layer adopts is the metal material of high reflectance;
This photoresist layer is exposed and develops, form the different photoresist layer pattern of thickness;
The unlapped the first metal layer of this photoresist layer and second metal level are etched away;
This photoresist layer is carried out etching, etched away fully until this thin photoresistance, and this thicker photoresistance also has residue;
Etch away unlapped second metal level of this photoresist layer;
Remove the residue photoresistance, to form gate line that constitutes by the first metal layer and second metal level and the storage capacitor electrode line that constitutes by this first metal layer.
8. thin film transistor base plate manufacture method as claimed in claim 7 is characterized in that: the material of this first metal layer is a kind of of following material: silver, aluminium and aluminium neodymium alloy.
9. thin film transistor base plate manufacture method as claimed in claim 8 is characterized in that: this second metal level be under the normal temperature and pressure not with the material of indium tin oxide or indium-zinc oxide generation electrochemical reaction.
10. thin film transistor base plate manufacture method as claimed in claim 9 is characterized in that: the material of this second metal level is a kind of of following material: molybdenum, chromium and titanium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510120679 CN1982997A (en) | 2005-12-16 | 2005-12-16 | Thin-film transistor base plate and its production |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510120679 CN1982997A (en) | 2005-12-16 | 2005-12-16 | Thin-film transistor base plate and its production |
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| CN1982997A true CN1982997A (en) | 2007-06-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420183A (en) * | 2011-12-07 | 2012-04-18 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT (Thin Film Transistor) array substrate and TFT array substrate |
-
2005
- 2005-12-16 CN CN 200510120679 patent/CN1982997A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420183A (en) * | 2011-12-07 | 2012-04-18 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT (Thin Film Transistor) array substrate and TFT array substrate |
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