CN1980103B - Detecting device and system for index of transmitting receiving teleseme - Google Patents
Detecting device and system for index of transmitting receiving teleseme Download PDFInfo
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- CN1980103B CN1980103B CN2005101300837A CN200510130083A CN1980103B CN 1980103 B CN1980103 B CN 1980103B CN 2005101300837 A CN2005101300837 A CN 2005101300837A CN 200510130083 A CN200510130083 A CN 200510130083A CN 1980103 B CN1980103 B CN 1980103B
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Abstract
The testing device is composed of transmitting test circuit, receiving test circuit, and clock generation circuit. The clock generation circuit provides working clock for each built up circuit, receiver and transmitter to be tested. The disclosed scheme can carry out test for receiving and transmitting indexes of receiver and transmitter expediently. Moreover, when problem is discovered, the scheme can distinguish whether problem occurs at receiving side or at transmitting side. In test for sensitivity of receiver, using method of testing EMV value, instead of test of bit error rate, the invention increases test speed and simplifies instruments needed.
Description
Technical field
The present invention relates to test the measuring technology of transceiver index, especially the testing apparatus of a kind of receipts/sender in the radio system and system.
Background technology
In radio system, the various technical indicators of transceiver all are the critical index of system usually.Leak (ACPR), PCDE (PCDE) like the Error Vector Magnitude (EVM) of transmitting end in the WCDMA system, adjacent-channel power, the receiving sensitivity of the end of collecting mail, face selectivity, veneer and block index etc. and all the performance of system is had bigger influence.
Error Vector Magnitude (EVM) is commonly used to describe the modulation quality of transmitter, and the range value of EVM representative vector error is not a statistic.As shown in Figure 1, error vector is the phasor difference between desirable vector signal of fixed time and the actual vector signal.Error Vector Magnitude (EVM) is the root-mean-square value of the error vector within a period of time.
Sensitivity is to satisfy under the situation of specifying BER (bit error rate) amplitude of the minimum signal that receiver can receive.Usually use the amplitude of signal voltage to describe sensitivity.Under a kind of specific modulation system, the signal to noise ratio snr of BER and signal is a kind of specific relation.For example WCDMA system requirements BER＜0.001 is equivalent to SNR＞7dB, and signal to noise ratio and EVM have
The transformational relation of (when SNR＞0).Promptly EVM less than 44.7% situation under, be equivalent to error rate BER＜0.001 of system.If test through the error rate, because the error rate itself is a statistical value, reach certain measuring accuracy must add up for a long time, the correct and wrong bit of transmission in the code stream is counted respectively, so test speed is slow.
These parameters measurement to transceiver before equipment uses is very important, because the deterioration of These parameters is to the communication quality of whole wireless system, power system capacity all has bigger influence.Normally used mode is at the initial stage of equipment development the various indexs of transceiver to be carried out detailed measurement identification, and in the production phase, only the sample of a spot of transceiver is measured.A problem of testing like this is to be difficult to guarantee the index of all transceiver products that dispatch from the factory.
Using more a kind of method of testing at present is in system, the whole system that comprises baseband portion to be tested.But the time of this method of testing cost is longer, therefore is merely able to the part sample is tested, and another problem of this method is, when test can not through the time to be difficult to distinguish be that transceiver is out of joint or other parts of system have problem.
A kind of test mode such as the Chinese patent CN98813155 that also have at present are said; Adopt transceiver to measure from the mode of ring; The advantage of this test mode is need not add testing apparatus; But the shortcoming of this method of testing is can not measure accurately to transmit and receive index, and when pinpointing the problems, can not distinguish emission or the problem that receives.
Summary of the invention
The technical problem that the present invention will solve provides a kind of testing apparatus and test macro of transceiver index; Realization can be tested the transmitting-receiving index of transceiver easily, and when pinpointing the problems, can distinguish emission or the goal of the invention of the problem that receives.
The present invention adopts the method for test EVM value to replace the test of bit error rate in the test of carrying out receiver sensitivity in addition, has improved test speed, has simplified the instrument that test needs.
In order to solve above technical problem, the present invention proposes following technical scheme:
A kind of testing apparatus of receiver index is connected in receiver and receives between the index test instrument, the clock generating circuit that comprises the acceptance test circuit and clock pulse is provided for the acceptance test circuit;
Described acceptance test circuit constitutes by receiving data converting circuit and D/A converting circuit; Described reception data converting circuit receives the data that receiver transmits; Send described D/A converting circuit to after converting the needed data format of D/A converting circuit to, described D/A converting circuit converts thereof into analog signal and exports reception index test instrument to.
The reception data converting circuit of the testing apparatus of described receiver index is control logic able to programme or digital signal processing circuit, and described D/A converting circuit is for adopting and receiving the speed that data converting circuit adapts and the digital to analog converter of figure place.
The testing apparatus of described receiver index also comprises the transmission test circuit; Said clock generating circuit is connected with this transmission test circuit; For this transmission test circuit provides clock signal; This transmission test circuit is connected between host computer and the sender; This transmission test circuit comprises and sends data storage and data sending controling circuit, and said transmission data storage is used to store the data of testing usefulness, is sent to sender after the said test data that said data sending controling circuit is read storage is changed.
The transmission test circuit of the testing apparatus of described receiver index also comprises the Data Update control circuit; Be used under the Data Update state, downloading test data and being saved in said transmission data storage from host computer, said data sending controling circuit is read test data from said transmission data storage again under the data transmit status.
The Data Update control circuit of the testing apparatus of described receiver index is CPU or PLD; Described transmission data storage is internal memory or flash memory; Described data sending controling circuit is FPGA or digital signal processing circuit.
The clock generating circuit of the testing apparatus of described receiver index comprises phase-locked loop circuit, crystal oscillating circuit, clock timing sequence generating circuit; Described phase-locked loop circuit is used to receive the reference clock by receiving the input of index test instrument, and phase-locked loop circuit sends this clock signal to said crystal oscillating circuit, makes the crystal oscillating circuit synchronous with the clock reference signal of outside input; Described crystal oscillating circuit is sent to described clock timing sequence generating circuit with clock signal, and said clock timing sequence generating circuit produces the work clock of receiver and acceptance test circuit according to the clock signal that receives.
Described phase-locked loop circuit is that phase-locked loop chip constitutes; Described crystal oscillating circuit is constant temperature or VCXO; Said clock timing sequence generating circuit is a programmable logic chip.
The present invention also points out a kind of testing apparatus of sender index, is connected between host computer and the sender, comprises sending test circuit and for sending test circuit the clock generating circuit of clock pulse being provided; This transmission test circuit comprises and sends data storage and data sending controling circuit, and said transmission data storage is used to store the data of testing usefulness, is sent to sender after the said test data that said data sending controling circuit is read storage is changed.
The transmission test circuit of the testing apparatus of described sender index also comprises the Data Update control circuit; Be used under the Data Update state, downloading test data and being saved in said transmission data storage from host computer, said data sending controling circuit is read test data from said transmission data storage again under the data transmit status.
The described Data Update control circuit of the testing apparatus of described sender index is CPU or PLD; Described transmission data storage is internal memory or flash memory; Described data sending controling circuit is FPGA or digital signal processing circuit.
The clock generating circuit of the testing apparatus of described sender index comprises phase-locked loop circuit, crystal oscillating circuit, clock timing sequence generating circuit; Described phase-locked loop circuit receives reference input clock signal, and phase-locked loop circuit sends this clock signal to said crystal oscillating circuit, makes the crystal oscillating circuit synchronous with the clock reference signal of outside input; Described crystal oscillating circuit is sent to described clock timing sequence generating circuit with clock signal, the work clock that said clock timing sequence generating circuit produces sender and sends test circuit according to the clock signal that receives.Described phase-locked loop circuit is that phase-locked loop chip constitutes; Described crystal oscillating circuit is constant temperature or VCXO; Said clock timing sequence generating circuit is a programmable logic chip.
The present invention also points out a kind of test macro of transceiver index; Comprise transceiver tester device, transceiver to be tested, host computer, emission index test instrument and receive the index test instrument; This transceiver tester device is formed by sending test circuit and acceptance test circuit and clock generating circuit, and described clock generating circuit provides the work clock pulse for sending test circuit and acceptance test circuit and transceiver to be tested;
Described reception index test instrument is that clock generating circuit provides pulse reference clock;
Wherein host computer is connected with the transmission test circuit, and the transmission test circuit will be tested number and send transceiver to be tested to, and the transmit port by transceiver to be tested sends emission index test instrument to again;
Transceiver to be tested sends the acceptance test circuit to through its receiving port acceptance test signal, and the acceptance test circuit is exported to after to conversion of signals and received the index test instrument.
The reception index test instrument of described transceiver index testing system is the instrument of test error amplitude of the vector.
The acceptance test circuit of described transceiver index testing system constitutes by receiving data converting circuit and D/A converting circuit; Described reception data converting circuit receives the data that receiver transmits; Send described D/A converting circuit to after converting the needed data format of D/A converting circuit to, described D/A converting circuit converts thereof into analog signal and exports reception index test instrument to.Described reception data converting circuit is control logic able to programme or digital signal processing circuit, and described D/A converting circuit is for adopting and receiving the speed that data converting circuit adapts and the digital to analog converter of figure place.
The transmission test circuit of described transceiver index testing system comprises transmission data storage and data sending controling circuit; Said transmission data storage is used to store the data of test usefulness, is sent to sender after the said test data that said data sending controling circuit is read storage is changed.
Said transmission test circuit also comprises the Data Update control circuit; Be used under the Data Update state, downloading test data and being saved in said transmission data storage from host computer, said data sending controling circuit is read test data from said transmission data storage again under the data transmit status.
Described Data Update control circuit is CPU or PLD; Described transmission data storage is internal memory or flash memory; Described data sending controling circuit is FPGA or digital signal processing circuit.
The clock generating circuit of described transceiver index testing system comprises phase-locked loop circuit, crystal oscillating circuit, clock timing sequence generating circuit; Described phase-locked loop circuit receives by the reference clock that receives the input of index test instrument, sends this clock signal to said crystal oscillating circuit, makes the crystal oscillating circuit synchronous with the clock reference signal of outside input; Described crystal oscillating circuit is sent to described clock timing sequence generating circuit with clock signal, the work clock that said clock timing sequence generating circuit produces transceiver, acceptance test circuit and sends test circuit according to the clock signal that receives.
Described phase-locked loop circuit is that phase-locked loop chip constitutes; Described crystal oscillating circuit is constant temperature or VCXO; Said clock timing sequence generating circuit is a programmable logic chip.
Technique effect of the present invention is significant; Transceiver tester device of the present invention has the storage of transmission, clock generation, acknowledge(ment) signal translation circuit; Use this device the time can select to use different data sources to send sending test, when acceptance test, under instrument auxiliary, can test the reception index faster; The present invention adopts the method for test EVM value to replace the test of bit error rate in the test of carrying out receiver sensitivity, and this method has improved the speed of test significantly, has simplified the instrument and equipment that test needs; The present invention compared with prior art adopts the mode of testing receiver and sender separately, can the Fault Isolation of other parts in the wireless system be gone out, and can clearly judge it is the problem of receiver or sender.
Description of drawings
Fig. 1 is the presentation graphs of Error Vector Magnitude.
Fig. 2 is the structured flowchart of embodiments of the invention one.
Fig. 3 is the structured flowchart of embodiments of the invention two.
Fig. 4 is the structured flowchart of embodiments of the invention three.
Fig. 5 is the structured flowchart of the test macro of embodiments of the invention three compositions.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further detailed description.
Embodiment one
The testing apparatus of receiver index as shown in Figure 2, this device are connected in receiver and receive between the index test instrument, the clock generating circuit 3 that comprises acceptance test circuit 2 and clock pulse is provided for the acceptance test circuit; Described acceptance test circuit 2 constitutes by receiving data converting circuit 22 and D/A converting circuit 21; Described reception data converting circuit 22 receives the data that receiver transmits; Convert the needed data format of D/A converting circuit to and send described D/A converting circuit to, described D/A converting circuit 21 converts this digital signal to analog signal and exports reception index test instrument to.
In the present embodiment, described reception data converting circuit is control logic able to programme or Digital Signal Processing (DSP) circuit, and described D/A converting circuit is for adopting and the DA transducer that receives corresponding speed of data converting circuit and figure place.
Described clock generating circuit 3 comprises phase-locked loop circuit 31, crystal oscillating circuit 32 and clock timing sequence generating circuit 33; By receiving index test instrument input reference clock to described phase-locked loop circuit, phase-locked loop circuit sends this clock signal to the crystal oscillating circuit, makes the crystal oscillating circuit synchronous with the clock reference signal of outside input; Described crystal oscillating circuit is sent to described clock timing sequence generating circuit with clock signal, and the clock timing sequence generating circuit produces the work clock of receiver and acceptance test circuit according to the clock signal that receives.This crystal oscillating circuit provides clock reference for all circuit in this device, and its precision should satisfy circuit and receiver to be tested in this device to the requirement of clock accuracy
Described phase-locked loop circuit is that phase-locked loop chip constitutes; Described crystal oscillating circuit is constant temperature or VCXO; Said clock timing sequence generating circuit is a programmable logic chip.
When the test that receives index, signal source received the receiving port of receiver to be tested, the test signal of signalization source output certain format.The acceptance test circuit is sent in the D/A converting circuit after receiving the format conversion of digital signal through the reception data converting circuit from receiver.D/A converting circuit converts digital signal into analog signal output, supplies the acceptance test instrument to receive index test.
Carry out in the measurement of sensitivity of receiver, adopt the mode of the equivalent bit error rate of EVM value to measure, can know under a kind of specific modulation system by prior art; Relation is one to one arranged between these two kinds of desired values; Can convert through the method for numerical computations, the therefore value that obtains of the two kinds of index tests quality of end of can actual response collecting mail is so shortened Measuring Time greatly; Simplify the required instrument of test, improved testing efficiency.
Embodiment two
Shown in Figure 3 is a kind of testing apparatus of sender index, and this device is connected between host computer and the sender, comprises sending test circuit 1 and for sending test circuit 1 clock generating circuit 3 of clock pulse being provided; This transmission test circuit 1 comprises Data Update control circuit 11, sends data storage 12 and data sending controling circuit 13.
Data Update control circuit 11 is used under the Data Update state, and control is downloaded test data from host computer, and with storage in sending data storage 12.Data sending controling circuit 13 is used under the data transmit status, reads the data of sending storage in the data storage 12, is sent to sender after changing.
Described in the present embodiment Data Update control circuit is CPU or PLD; Described transmission data storage is internal memory or flash memory; Described data sending controling circuit is FPGA or digital signal processing circuit.
The structure of the clock generator circuit that adopts in the present embodiment and principle can be consistent with embodiment 1 described content, do not giving unnecessary details at this.
In the present embodiment, said Data Update control circuit can adopt network interface, serial ports or other interfaces to receive from host computer and send data, and said Data Update control circuit provides corresponding data, address, control interface to link to each other with the transmission data storage; Said Data Update control circuit adopts above-mentioned interface to upgrade the content of sending in the data storage.Said data sending controling circuit links to each other with the data, address, the control interface that send data storage, and provides the corresponding interface to link to each other with the sender of transceiver to be tested.The data, address, the control interface that are said transmission data storage link to each other with the data sending controling circuit with the Data Update control circuit simultaneously.Said transmission data storage can be that power down is prone to lose or non-power-failure is prone to lose.The capacity of said transmission data storage confirms according to the data volume of testing requirement, can select to store one group or organize test data more.
When the test of sending index, content measurement is as required downloaded corresponding test data to sending data storage 12 from host computer, and process of downloading is by 11 controls of Data Update control circuit.Select for use nonvolatile memory can one group that use always or several groups of test datas be stored in to send in the data storage 12 if send data storage 12, like this data download again all when not needing at every turn to test.Data download to be accomplished back data sending controling circuit 13 and are obtained the control of sending data storage 12, and sense data converts the transmitter unit of delivering to transceiver to be tested behind the form of appointment into from transmission data storage 12.The transmitter unit of transceiver to be tested converts this digital signal into radiofrequency signal output, emission index test instrument is received the transmit port of transceiver and just can be tested various transmission indexs easily.
Embodiment three
As shown in Figure 4; Structure for embodiments of the invention three; In the present embodiment, device of the present invention can be tested receiving and send index, and is visible by diagram; The transmission test circuit 1 and the acceptance test circuit 2 of this device are two relatively independent parts; Be respectively applied for the emission path of transceiver is tested with the reception path, and clock generating circuit 3 is used for producing transmission test circuit 1, acceptance test circuit 2 and the needed clock of transceiver to be tested, realizes carrying out simultaneously the transmission index test of transceiver and receives index test.
Certainly the described device of present embodiment also can be realized the function of embodiments of the invention one and embodiment two, promptly can send index test separately or receive index test.
In the present embodiment; Clock generating circuit 3 is automatic phase-locked loop circuitry 31 when powering on; Make crystal oscillating circuit 32 lock onto outside input reference clock under the situation of outside input reference clock having, do not having to make crystal oscillating circuit 32 be operated in frequency preset output under the situation of outside input reference clock.The work clock that clock timing sequence generating circuit 33 is required with sending test circuit 1, acceptance test circuit 2 according to the required various clocks of the clock generating of crystal oscillating circuit 32 output transceiver to be tested.
The test process of the reception of present embodiment and transmission index is consistent with embodiment two with embodiment one, so repeat no more at this.
In sum; The transceiver tester device that the present invention proposes, owing to adopt the method for testing receiver and sender separately, so compare than prior art; The Fault Isolation of other part in the wireless system is gone out, can clearly judge receiver or sender goes wrong.The sender test circuit partly adopts renewable data storage, and the test data that can load any needs is tested.The acceptance test circuit converts the reception signal of receiver into analog signal output again, and the various instruments of convenient use are measured.In the measurement of receiver sensitivity, adopt the mode of the equivalent bit error rate of EVM value to measure, shortened Measuring Time greatly, simplified and tested required instrument, improved the efficient of test.
Below system that the present invention is proposed describe:
The present invention is on the basis of above-mentioned testing apparatus; A kind of test macro of transceiver index has been proposed; As shown in Figure 5; This system comprises transceiver tester device, transceiver to be tested, host computer, emission index test instrument and receives the index test instrument; This transceiver tester device is formed by sending test circuit and acceptance test circuit and clock generating circuit, and described clock generating circuit provides the work clock pulse for sending test circuit and acceptance test circuit and transceiver to be tested; Described reception index test instrument is that clock generating circuit provides pulse reference clock; Wherein host computer is connected with the transmission test circuit, and the transmission test circuit will be tested number and send transceiver to be tested to, and the transmit port by transceiver to be tested sends emission index test instrument to again; Transceiver to be tested sends the acceptance test circuit to through its receiving port acceptance test signal, and the acceptance test circuit is exported to after to conversion of signals and received the index test instrument.
The formation of the transmission test circuit that comprises in the transceiver tester device in the native system, acceptance test circuit and clock generating circuit is identical with the structure and the operation principle of the foregoing description, repeats no more at this.
The system of indication of the present invention has adopted band to send the transceiver tester device of storage, clock generation, acknowledge(ment) signal conversion; Used the system of this device to test the transmitting-receiving index of transceiver easily; When sending test; Can select to use different data sources to send, when acceptance test, can test the reception index faster down, especially in the test of carrying out receiver sensitivity, adopt the method for testing the EVM value to replace the test of bit error rate the auxiliary of instrument; Can know under specific modulation system according to the content of prior art; Relation is arranged between these two kinds of desired values one to one, is to convert through the method for numerical computations, therefore the value that obtains of the two kinds of index tests quality of end of can actual response collecting mail.This test has significantly improved the speed of test, has simplified the instrument and equipment that test needs.
In the transmission test circuit of native system data storage is set in addition, like this when not needing each test all again machine carry out data and download, also improved testing efficiency.
In sum; System of the present invention can solve the technical problem that exists in the prior art; And realization the object of the invention, can test the transmitting-receiving index of transceiver easily, and when pinpointing the problems, can distinguish emission or the problem that receives.
Claims (20)
1. the testing apparatus of a receiver index is connected in receiver and receives between the index test instrument, it is characterized in that, the clock generating circuit that comprises the acceptance test circuit and clock pulse is provided for the acceptance test circuit;
Described acceptance test circuit constitutes by receiving data converting circuit and D/A converting circuit; Described reception data converting circuit receives the data that receiver transmits; Send described D/A converting circuit to after converting the needed data format of D/A converting circuit to, described D/A converting circuit converts thereof into analog signal and exports reception index test instrument to;
This testing apparatus also comprises the transmission test circuit; Said clock generating circuit is connected with this transmission test circuit; For this transmission test circuit provides clock signal, this transmission test circuit is connected between host computer and the sender, and this transmission test circuit comprises transmission data storage and data sending controling circuit; Said transmission data storage is used for store test data, is sent to sender after the said test data that said data sending controling circuit is read storage is changed.
2. the testing apparatus of receiver index as claimed in claim 1; It is characterized in that; Described reception data converting circuit is control logic able to programme or digital signal processing circuit, and described D/A converting circuit is for adopting and receiving the speed that data converting circuit adapts and the digital to analog converter of figure place.
3. the testing apparatus of receiver index as claimed in claim 1; It is characterized in that; Said transmission test circuit also comprises the Data Update control circuit; Be used under the Data Update state, downloading test data and being saved in said transmission data storage from host computer, said data sending controling circuit is read test data from said transmission data storage again under the data transmit status.
4. the testing apparatus of receiver index as claimed in claim 3 is characterized in that, described Data Update control circuit is CPU or PLD; Described transmission data storage is internal memory or flash memory; Described data sending controling circuit is FPGA or digital signal processing circuit.
5. the testing apparatus of receiver index as claimed in claim 1 is characterized in that, described clock generating circuit comprises phase-locked loop circuit, crystal oscillating circuit, clock timing sequence generating circuit; Described phase-locked loop circuit is used to receive the reference clock by receiving the input of index test instrument, and phase-locked loop circuit sends this clock signal to said crystal oscillating circuit, makes the crystal oscillating circuit synchronous with the clock reference signal of outside input; Described crystal oscillating circuit is sent to described clock timing sequence generating circuit with clock signal, and said clock timing sequence generating circuit produces the work clock of receiver and acceptance test circuit according to the clock signal that receives.
6. the testing apparatus of receiver index as claimed in claim 5 is characterized in that, described phase-locked loop circuit is that phase-locked loop chip constitutes; Described crystal oscillating circuit is constant temperature or VCXO; Said clock timing sequence generating circuit is a programmable logic chip.
7. the testing apparatus of a sender index is connected between host computer and the sender, it is characterized in that, comprises sending test circuit and for sending test circuit the clock generating circuit of clock pulse being provided; This transmission test circuit comprises and sends data storage and data sending controling circuit, and said transmission data storage is used for store test data, is sent to sender after the said test data that said data sending controling circuit is read storage is changed;
Said testing apparatus also comprises the acceptance test circuit, and clock generating circuit provides clock pulse for this acceptance test circuit;
Described acceptance test circuit constitutes by receiving data converting circuit and D/A converting circuit; Described reception data converting circuit receives the data that receiver transmits; Send described D/A converting circuit to after converting the needed data format of D/A converting circuit to, described D/A converting circuit converts thereof into analog signal and exports reception index test instrument to.
8. the testing apparatus of sender index as claimed in claim 7; It is characterized in that; Said transmission test circuit also comprises the Data Update control circuit; Be used under the Data Update state, downloading test data and being saved in said transmission data storage from host computer, said data sending controling circuit is read test data from said transmission data storage again under the data transmit status.
9. the testing apparatus of sender index as claimed in claim 8 is characterized in that, described Data Update control circuit is CPU or PLD; Described transmission data storage is internal memory or flash memory; Described data sending controling circuit is FPGA or digital signal processing circuit.
10. the testing apparatus of sender index as claimed in claim 7 is characterized in that, described clock generating circuit comprises phase-locked loop circuit, crystal oscillating circuit, clock timing sequence generating circuit; Described phase-locked loop circuit receives reference input clock signal, and phase-locked loop circuit sends this clock signal to said crystal oscillating circuit, makes the crystal oscillating circuit synchronous with the clock reference signal of outside input; Described crystal oscillating circuit is sent to described clock timing sequence generating circuit with clock signal, the work clock that said clock timing sequence generating circuit produces sender and sends test circuit according to the clock signal that receives.
11. the testing apparatus of sender index as claimed in claim 10 is characterized in that, described phase-locked loop circuit is that phase-locked loop chip constitutes; Described crystal oscillating circuit is constant temperature or VCXO; Said clock timing sequence generating circuit is a programmable logic chip.
12. the test macro of a transceiver index; It is characterized in that; Comprise transceiver tester device, transceiver to be tested, host computer, emission index test instrument and receive the index test instrument; This transceiver tester device is formed by sending test circuit and acceptance test circuit and clock generating circuit, and described clock generating circuit provides the work clock pulse for sending test circuit and acceptance test circuit and transceiver to be tested;
Described reception index test instrument is that clock generating circuit provides pulse reference clock;
Wherein host computer is connected with the transmission test circuit, and the transmission test circuit will be tested number and send transceiver to be tested to, and the transmit port by transceiver to be tested sends emission index test instrument to again;
Transceiver to be tested sends the acceptance test circuit to through its receiving port acceptance test signal, and the acceptance test circuit is exported to after to conversion of signals and received the index test instrument.
13. transceiver index testing system as claimed in claim 12 is characterized in that, described reception index test instrument is the instrument of test error amplitude of the vector.
14. transceiver index testing system as claimed in claim 12; It is characterized in that; Described acceptance test circuit constitutes by receiving data converting circuit and D/A converting circuit; Described reception data converting circuit receives the data that receiver transmits, and sends described D/A converting circuit to after converting the needed data format of D/A converting circuit to, and described D/A converting circuit converts thereof into analog signal and exports to and receive the index test instrument.
15. transceiver index testing system as claimed in claim 14; It is characterized in that; Described reception data converting circuit is control logic able to programme or digital signal processing circuit, and described D/A converting circuit is for adopting and receiving the speed that data converting circuit adapts and the digital to analog converter of figure place.
16. transceiver index testing system as claimed in claim 12; It is characterized in that; Described transmission test circuit comprises transmission data storage and data sending controling circuit; Said transmission data storage is used for store test data, is sent to sender after the said test data that said data sending controling circuit is read storage is changed.
17. transceiver index testing system as claimed in claim 16; It is characterized in that; Said transmission test circuit also comprises the Data Update control circuit; Be used under the Data Update state, downloading test data and being saved in said transmission data storage from host computer, said data sending controling circuit is read test data from said transmission data storage again under the data transmit status.
18. transceiver index testing system as claimed in claim 17 is characterized in that, described Data Update control circuit is CPU or PLD; Described transmission data storage is internal memory or flash memory; Described data sending controling circuit is FPGA or digital signal processing circuit.
19. transceiver index testing system as claimed in claim 12 is characterized in that, described clock generating circuit comprises phase-locked loop circuit, crystal oscillating circuit, clock timing sequence generating circuit; Described phase-locked loop circuit receives by the reference clock that receives the input of index test instrument, sends this clock signal to said crystal oscillating circuit, makes the crystal oscillating circuit synchronous with the clock reference signal of outside input; Described crystal oscillating circuit is sent to described clock timing sequence generating circuit with clock signal, the work clock that said clock timing sequence generating circuit produces transceiver, acceptance test circuit and sends test circuit according to the clock signal that receives.
20. transceiver index testing system as claimed in claim 19 is characterized in that, described phase-locked loop circuit is that phase-locked loop chip constitutes; Described crystal oscillating circuit is constant temperature or VCXO; Said clock timing sequence generating circuit is a programmable logic chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101300837A CN1980103B (en) | 2005-12-08 | 2005-12-08 | Detecting device and system for index of transmitting receiving teleseme |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101300837A CN1980103B (en) | 2005-12-08 | 2005-12-08 | Detecting device and system for index of transmitting receiving teleseme |
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| CN1980103A CN1980103A (en) | 2007-06-13 |
| CN1980103B true CN1980103B (en) | 2012-02-29 |
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| CN111209718B (en) * | 2018-11-05 | 2023-06-02 | 珠海格力电器股份有限公司 | Verification environment platform, verification method, computer device and readable storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0847153A2 (en) * | 1996-12-09 | 1998-06-10 | Advantest Corporation | Method and apparatus for measuring waveform quality of CDMA signal |
| CN1278376A (en) * | 1997-10-27 | 2000-12-27 | 西门子公司 | Estimation of transmission channels in communication sysetms for wireless telecommunication |
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2005
- 2005-12-08 CN CN2005101300837A patent/CN1980103B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0847153A2 (en) * | 1996-12-09 | 1998-06-10 | Advantest Corporation | Method and apparatus for measuring waveform quality of CDMA signal |
| CN1278376A (en) * | 1997-10-27 | 2000-12-27 | 西门子公司 | Estimation of transmission channels in communication sysetms for wireless telecommunication |
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