CN1979423A - Multi-processor load distribution-regulation method - Google Patents
Multi-processor load distribution-regulation method Download PDFInfo
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- CN1979423A CN1979423A CN 200510022179 CN200510022179A CN1979423A CN 1979423 A CN1979423 A CN 1979423A CN 200510022179 CN200510022179 CN 200510022179 CN 200510022179 A CN200510022179 A CN 200510022179A CN 1979423 A CN1979423 A CN 1979423A
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Abstract
The invention is a multiprocessor load allocation regulating method, relating to the data communication field, especially relating to a technique for regulating load allocation of each processor in multiprocessor network equipment. And it comprises the steps of: a. CPU obtains bandwidth condition of system interface socket; b. according to processing ability of each processor, CPU allocates interface to each processor in proportion. And it makes the data flow processed by each processor in operation basically equivalent, relatively uniformly and appropriately allocating processor resources and avoiding load allocation ununiformity in a multiprocessor system.
Description
Technical field
The present invention relates to data communication field, relate in particular to the adjustment technology that each processor load distributes in the multiprocessor network equipment.
Background technology
In existing data communication system, the apparatus for network node that performance and complexity are had relatively high expectations adopts the distributed systems framework usually, with the data forwarding task of the various distinct interface of high speed processing.The main task of this network equipment is exactly to transmit packet with high speed, so a plurality of processor major parts of this network equipment all are the processing forward tasks.
Present multiprocessor network equipment, the load of its processing forward task handling device distribute normally static, and is promptly just fixing when designing, and that is to say the fixing data of handling some or a plurality of interfaces receptions and sending of some processors.Whether handle the data of slot 1,2 such as, processor 1, processor 2 is handled the data of slots 3,4, and no matter insert in the slot 1,2,3,4, perhaps inserts which kind of interface card.This processing mode has a very serious weak point to be, the load of its processor can't dynamically be adjusted in actual environment, some processors may be occurred and a plurality of high-speed interfaces must be handled, and another processor is only handled the situation of a low-speed interface, cause processor load seriously inhomogeneous, make actual service efficiency low, the processor performance waste is serious.
Also have some multiprocessor network equipment, adopted task dynamic assignment mode based on the existing load of processor.This dynamic assignment mode is normally followed the tracks of the running load of current processor, more newly-increased task is added on the lighter processor of load.The problem that this mode is brought mainly is, because same interface may be handled by a plurality of processors, so must introduce the mechanism of mutual exclusion, has influence on the concurrency of multiprocessor, thereby reduces the forwarding performance of interface.Also have and a kind of each processor is designed into structure on each ply-yarn drill, each interface card all has the processor of oneself, though this design has got around the problem that the multiprocessor load distributes, the thing followed is the sharp increase of processor number, causes cost to rise; Because each processor not on same printed circuit board, also causes being difficult between the processor connecting at a high speed, or the cost that connects at a high speed also sharply rises; The design difficulty of simultaneity factor software also sharply increases.
Summary of the invention
Technical matters to be solved by this invention is, a kind of method of each processor tasks of high-performance multiprocessor network devices allocation is provided, make the reception of each interface send task under the situation that does not influence transmitting-receiving performance own, being assigned to each as far as possible uniformly handles, make each processor load basis equalization, improve the utilization factor of processor.
The technical scheme that the present invention solve the technical problem employing is that multi-processor load distribution-regulation method is characterized in that, may further comprise the steps: a, CPU (central processing unit) obtain system interface slot bandwidth conditions; B, according to the processing power of each processor, CPU (central processing unit) is each processor distribution interface in proportion.
Further, a0 in steps also before the described step a: when trigger event takes place when, the notice CPU (central processing unit).
Further, manage throughout under the suitable situation of the arithmetic capability of device, described step b comprises: b1, when available processor number is N, interface is divided into the N group, and make the bandwidth summation of every group interface suitable; B2, upgrade the handled interface table of each processor, redistribute the transmitting-receiving task of each processor processing, the transmitting-receiving task of the group interface in each processor processing N group interface.
Described trigger event is that system configuration changes, and specifically, revises incidents such as configuration, hot-swappable or initialization.
Among the described step b, CPU (central processing unit) is according to the proportional distribution interface of the frequency of operation of each processor.
The invention has the beneficial effects as follows, adopt the designed distribution method of the present invention, can when system configuration changes, operation calculate, and in system stable operation, can not take processor resource.And owing to the network equipment that is in than core position, general flow is all bigger, its interface data flow is basic suitable with its bandwidth, also have only in this case, just can high requirements be proposed, so method of the present invention makes each processor handled data traffic when operation also suitable substantially to processor resource, relatively evenly suitable distribution processor resource has been avoided the busy not busy uneven of multicomputer system.Secondly, by top scheme also as can be seen, method of the present invention is after each system triggers moves to the distribution end, do not need to preserve any state and statistics, system triggers this flow process all from stationary state at every turn, the difficulty of system handles such as system reliability and master control borad hot-swap has improved so that software processes in institute.Moreover this programme physical slot with system when allocating task is a least unit, has avoided different processor to handle the possibility of same interface, has also just avoided the mutually exclusive operation between the different processor, has improved the concurrency of multiprocessing.At last, because the physical slot number of system is limited, controlled, common several to dozens of the order of magnitude just, so it is the calculating of collection bandwidth and grouping is all very simple efficient, minimum to systematic influence.
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is a method flow diagram of the present invention.
Fig. 2 is the synoptic diagram of embodiment 1.
Embodiment
Referring to Fig. 1.The trigger event that present embodiment is set is for revising configuration, hot-swappable or initialization.After trigger event took place, the CPU (central processing unit) of system was obtained the bandwidth information of each interface, distributed corresponding interface according to the arithmetic capability of each processor then, made the load of each processor and arithmetic capability suitable.As Fig. 1.
Embodiment 1: referring to Fig. 2.
The bandwidth of the interface 1,2,3,4 of system is respectively 1M, 1M, 2M, 4M;
The frequency of operation of processor A, B, C is respectively aHz, aHz, 2aHz;
When system initialization, trigger allocator of the present invention, promptly to processor A, B, C proportional distribution interface according to 1: 1: 2.
" quite " as herein described should not be construed as strict equating, allows the difference that the present technique field is approved to occur, i.e. " roughly suitable ".For those of ordinary skill, this point is conspicuous.
Embodiment 2:
Present embodiment is the example of managing throughout under the roughly suitable situation of the arithmetic capability of device.
The bandwidth of interface a, the b of system, c, d, e is respectively 1M, 1M, 2M, 2M, 4M;
The arithmetic capability of processor A 1, B1 is suitable;
When hot drawing takes place interface e, trigger allocator of the present invention:
1, Yu Xia interface bandwidth status report system CPU (central processing unit);
2, CPU (central processing unit) computation bandwidth total amount (1M+1M+2M+2M=4M), because processor is 2, distribution interface a, c are to processor A1, interface b, d make the load of processor A 1, B1 roughly suitable to processor B1.
Claims (6)
1, multi-processor load distribution-regulation method is characterized in that, may further comprise the steps:
A, CPU (central processing unit) obtain system interface slot bandwidth conditions;
B, according to the processing power of each processor, CPU (central processing unit) is each processor distribution interface in proportion.
2, multi-processor load distribution-regulation method as claimed in claim 1 is characterized in that, a0 in steps also before the described step a: when trigger event takes place when, and the notice CPU (central processing unit).
3, multi-processor load distribution-regulation method as claimed in claim 1 is characterized in that, manages throughout under the suitable situation of the arithmetic capability of device, and described step b comprises:
B1, when available processor number is N, interface is divided into N group, make the bandwidth summation of every group interface suitable;
B2, upgrade the handled interface table of each processor, redistribute the transmitting-receiving task of each processor processing, the transmitting-receiving task of the group interface in each processor processing N group interface.
4, multi-processor load distribution-regulation method as claimed in claim 2 is characterized in that, described trigger event is that system configuration changes.
5, multi-processor load distribution-regulation method as claimed in claim 2 is characterized in that, described trigger event is for revising configuration, hot-swappable or initialization.
6, multi-processor load distribution-regulation method as claimed in claim 1 is characterized in that, among the described step b, CPU (central processing unit) is according to the proportional distribution interface of the frequency of operation of each processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100221791A CN100562850C (en) | 2005-11-30 | 2005-11-30 | Multi-processor load distribution-regulation method |
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| CNB2005100221791A CN100562850C (en) | 2005-11-30 | 2005-11-30 | Multi-processor load distribution-regulation method |
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| CN1979423A true CN1979423A (en) | 2007-06-13 |
| CN100562850C CN100562850C (en) | 2009-11-25 |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101217450B (en) * | 2008-01-15 | 2011-12-28 | 中兴通讯股份有限公司 | A calling distribution method |
| CN102426544A (en) * | 2011-11-04 | 2012-04-25 | 浪潮(北京)电子信息产业有限公司 | Task allocating method and system |
| CN101256668B (en) * | 2008-03-12 | 2012-09-05 | 中兴通讯股份有限公司 | Method for implementing video filtering to working balanced multiple nucleus |
| CN103024812A (en) * | 2007-12-28 | 2013-04-03 | 中国移动通信集团浙江有限公司 | Multiprocessor system load balanced configuration method |
| CN104598412A (en) * | 2014-10-17 | 2015-05-06 | 新浪网技术(中国)有限公司 | Data transmission method and device |
| CN104731740A (en) * | 2013-12-23 | 2015-06-24 | 联芯科技有限公司 | Hot-swap control method and hot-swap control device for multi-core central processing units in terminals |
| CN104935522A (en) * | 2014-03-19 | 2015-09-23 | 中兴通讯股份有限公司 | Static IPSec virtual interface load balancing method and device and main processor |
| CN105630602A (en) * | 2015-12-18 | 2016-06-01 | 山东海量信息技术研究院 | Method for dynamically adjusting computer system resources |
| CN106385385A (en) * | 2016-09-29 | 2017-02-08 | 东软集团股份有限公司 | Resource allocation method and device |
| CN111247513A (en) * | 2017-04-17 | 2020-06-05 | 迪普西格有限公司 | Placement and scheduling of radio signal processing data stream operations |
| CN111984556A (en) * | 2020-08-17 | 2020-11-24 | 紫光恒越技术有限公司 | Mainboard and mainboard resource sharing method |
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| GB2309558A (en) * | 1996-01-26 | 1997-07-30 | Ibm | Load balancing across the processors of a server computer |
| JPH11261702A (en) * | 1998-03-06 | 1999-09-24 | Fujitsu Ltd | System optimization controlling by predicting load |
| CN100444572C (en) * | 2001-12-01 | 2008-12-17 | 中兴通讯股份有限公司 | Multi-processing unit route system |
| US6687651B2 (en) * | 2002-01-10 | 2004-02-03 | Fujitsu Network Communications, Inc. | Real time estimation of equivalent bandwidth utilization |
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2005
- 2005-11-30 CN CNB2005100221791A patent/CN100562850C/en not_active Expired - Fee Related
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| CN103024812B (en) * | 2007-12-28 | 2015-08-26 | 中国移动通信集团浙江有限公司 | Balanced configuration method of multiprocessor system charge |
| CN103024812A (en) * | 2007-12-28 | 2013-04-03 | 中国移动通信集团浙江有限公司 | Multiprocessor system load balanced configuration method |
| CN101217450B (en) * | 2008-01-15 | 2011-12-28 | 中兴通讯股份有限公司 | A calling distribution method |
| CN101256668B (en) * | 2008-03-12 | 2012-09-05 | 中兴通讯股份有限公司 | Method for implementing video filtering to working balanced multiple nucleus |
| CN102426544A (en) * | 2011-11-04 | 2012-04-25 | 浪潮(北京)电子信息产业有限公司 | Task allocating method and system |
| CN104731740A (en) * | 2013-12-23 | 2015-06-24 | 联芯科技有限公司 | Hot-swap control method and hot-swap control device for multi-core central processing units in terminals |
| CN104731740B (en) * | 2013-12-23 | 2017-11-10 | 联芯科技有限公司 | Polycaryon processor hot plug control method and device in terminal |
| CN104935522B (en) * | 2014-03-19 | 2019-08-27 | 南京中兴新软件有限责任公司 | The method, apparatus and primary processor of static IP Sec virtual interface load balancing |
| CN104935522A (en) * | 2014-03-19 | 2015-09-23 | 中兴通讯股份有限公司 | Static IPSec virtual interface load balancing method and device and main processor |
| WO2015139433A1 (en) * | 2014-03-19 | 2015-09-24 | 中兴通讯股份有限公司 | Load balancing method and device for static ipsec virtual interfaces, and main processor |
| CN104598412A (en) * | 2014-10-17 | 2015-05-06 | 新浪网技术(中国)有限公司 | Data transmission method and device |
| CN105630602A (en) * | 2015-12-18 | 2016-06-01 | 山东海量信息技术研究院 | Method for dynamically adjusting computer system resources |
| CN105630602B (en) * | 2015-12-18 | 2019-01-15 | 山东海量信息技术研究院 | A kind of method of resource for computer system dynamic adjustment |
| CN106385385A (en) * | 2016-09-29 | 2017-02-08 | 东软集团股份有限公司 | Resource allocation method and device |
| CN106385385B (en) * | 2016-09-29 | 2020-02-21 | 东软集团股份有限公司 | Resource allocation method and device |
| CN111247513A (en) * | 2017-04-17 | 2020-06-05 | 迪普西格有限公司 | Placement and scheduling of radio signal processing data stream operations |
| CN111247513B (en) * | 2017-04-17 | 2021-10-08 | 迪普西格有限公司 | Placement and scheduling of radio signal processing data stream operations |
| US11871246B2 (en) | 2017-04-17 | 2024-01-09 | DeepSig Inc. | Placement and scheduling of radio signal processing dataflow operations |
| CN111984556A (en) * | 2020-08-17 | 2020-11-24 | 紫光恒越技术有限公司 | Mainboard and mainboard resource sharing method |
| CN111984556B (en) * | 2020-08-17 | 2022-04-26 | 紫光恒越技术有限公司 | Mainboard and mainboard resource sharing method |
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| CN100562850C (en) | 2009-11-25 |
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Denomination of invention: Multi-processor load distribution-regulation method Effective date of registration: 20121122 Granted publication date: 20091125 Pledgee: Bank of Chengdu science and technology branch of Limited by Share Ltd. Pledgor: MAIPU COMMUNICATION TECHNOLOGY Co.,Ltd. Registration number: 2012990000717 |
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Date of cancellation: 20140514 Granted publication date: 20091125 Pledgee: Bank of Chengdu science and technology branch of Limited by Share Ltd. Pledgor: MAIPU COMMUNICATION TECHNOLOGY Co.,Ltd. Registration number: 2012990000717 |
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Granted publication date: 20091125 |