CN1976260A - Burst mode optical receiver - Google Patents
Burst mode optical receiver Download PDFInfo
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- CN1976260A CN1976260A CNA200610146896XA CN200610146896A CN1976260A CN 1976260 A CN1976260 A CN 1976260A CN A200610146896X A CNA200610146896X A CN A200610146896XA CN 200610146896 A CN200610146896 A CN 200610146896A CN 1976260 A CN1976260 A CN 1976260A
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Abstract
A system, method, and computer readable medium for burst mode optical receiver that enables an optical receiver to receive signals from a plurality of optical network units at different optical power levels comprising, collecting received signal strength indication information from a previous data stream of an optical network unit, and adjusting an optical receiver to optimize reception of subsequent incoming data streams of the optical network unit based upon received signal strength indication information received from the previous data stream.
Description
Cross reference to related application
It is the temporary patent application NO.60/740 of " BURSTMODE OPTICAL RECEIVER " that present patent application relates to and require the exercise question of submitting on November 28th, 2005, and 099 rights and interests are incorporated its full content at this into by reference.The exercise question that present patent application also relates to same date to be submitted to is incorporated its full content at this by reference for the temporary patent application NO.139513 of " ADDITIONAL CIRCUIT TOPOLOGIES FORBURST-MODE RECEIVER ".
Background technology
EPON (PON) comprises the optical line terminal (OLT) that is positioned at central office (CO).Optical line terminal utilizes optical branching device to provide service to a plurality of optical network units (ONU) that connect with star arrangement usually that are positioned at the user dwelling.Upstream data on the EPON from the optical network unit to the optical line terminal is time-multiplexed between a plurality of optical network units.Because each optical network unit can be positioned at the different distance place apart from optical line terminal, so the amplitude of the upward signal of seeing at the optical line terminal place changes between optical network unit.When sending the continuous impulse of the data that are in complete different capacity level, two optical network units will go wrong.
The power stage of the unpredictable data pulse of seeing at the receiver place of optical line terminal on the horizon of current burst mode optical receiver technology.This causes needs long packet preamble (preamble) so that satisfy the optical dynamic range demand of optical line terminal burst mode input signal, as defined in International Telecommunication Union's gigabit passive optical network (GPON) standard (G.984) and ITU broadband passive optical network (BPON) standard (G.983).In fact these long lead codes have wasted the upstream bandwidth of EPON.Do not have method to utilize medium access control (MAC) to come the fill-in light receiver at present or utilize amplifier that the data circuit is carried out direct current (DC) biasing, to obtain solution at the different optical power levels that enters.The MAC householder method is regulated the forward direction of MAC and is searched view (forward looking view), because it has about arranging the next specific knowledge of up arrival of which ONU, and it can utilize this information butt joint receipts machine to carry out preliminary treatment.In theory, such receiver can be worked under the situation that does not at all have lead code.Utilizing the method based on resetting of DC amplifier circuit is reactive approach, and it always needs a certain amount of lead code to train.
Passive optical network media access controller has the anticipatory knowledge that will transmit with uplink frame about which optical network unit.Therefore needed is a kind of circuit, wherein rapid adjustment to various input power levels so that shorten in the task of requirement of the required lead code of training, use EPON (PON) media access controller (MAC) to assist burst mode optical receiver (BMRX).This short lead code causes the upstream bandwidth of the increase on the EPON effectively.The invention provides a kind of system, method and computer-readable medium, it allows the auxiliary burst-mode receiver of passive optical network media access controller to reduce going up required time and up preamble length between row cell, and this has increased the effective bandwidth of EPON.
Summary of the invention
For example the passive optical network of those defineds in ITU GPON standard (G.984) and ITU BPON standard (G.983) needs specific burst mode optical-fiber network receiver, and this receiver has from the ability of a plurality of optical network unit received signals that are in different optical power levels.Verified, the ability that receives the signal that is in different optical power levels is a challenge design objective of field of telecommunications.A plurality of custom silicon integrated circuits fail to provide the solution that meets the demands.Do not have method to utilize media access controller at present or utilize amplifier that the data circuit is carried out the DC biasing solution with the different input optical power levels that obtain burst mode optical receiver.
Optical line terminal utilizes optical branching device to provide service to the optical network unit that connects with star arrangement that is positioned at the user dwelling.Upstream data on the EPON from the optical network unit to the optical line terminal is time-multiplexed between a plurality of optical network units.Because each optical network unit can be positioned at the different physical distances place from optical line terminal, the amplitude of the upward signal of seeing at the optical line terminal place changes to next optical network unit from an optical network unit.When two optical network units transmissions were in the continuous data pulse of complete different capacity level, obtaining free from error Data Receiving was a challenge.
The power stage of the unpredictable data pulse of seeing at the receiver place of optical line terminal on the horizon of current burst mode optical receiver technology.Therefore need the receiver of optical line terminal own so that receive data error freely at each upstream packet training.Receiver training is carried out being called on the dummy data of lead code, and this lead code is the repetitive sequence of 101010 bits normally, and receiver can utilize this sequence to adjust its sampling threshold but do not need must correctly to recover, because it is not real data.Before the real data payload of upstream packet, insert effective upstream bandwidth that lead code has reduced EPON.The required training time is depended on the amplitude difference between the continuous upstream packet to a great extent, and worst condition is that the high-amplitude grouping follows the low amplitude grouping closely, or opposite situation.Current system is designed to be used in sufficiently long fixedly lead code to provide maximum amplitude difference (for example, 15dB).This needs relatively long lead code, and this lead code can consume among the PON with a large amount of ONU the upstream bandwidth up to 20%.This causes the long lead code of needs so that satisfy the required optical dynamic range of optical line terminal burst mode input signal of regulation in the ITU GPON standard (G.984).In fact these long lead codes have wasted the bandwidth on the EPON.The present invention reduces required lead code by AC connection line DC is biased to known level.In an embodiment of the invention, MAC knows the uplink power level of each ONU and can before cell arrives coupling capacitor be pre-charged to correct value.Second method uses circuit to quicken the charging of coupling capacitance after all cells arrive.Can shorten lead code by using the media access controller data that the burst mode input signal of optical line terminal is carried out direct current (DC) biasing.In fact this shorter lead code obtains the upstream bandwidth that increases on the EPON.
The present invention utilizes the last row cell luminous power of front and the passive optical network media access controller information of last row cell luminous power subsequently to determine to be injected into the electric charge of the coupling capacitor between transreactance amplifier (TIA) and the limiting amplifier (LIMA), so that reduce to go up the required recovery time of optics between the row cell.The present invention disobeys pattern/number (A/D) or D/A (D/A) transducer will be sent to optical receiver from the information of media access controller to adjust AC coupling capacitor voltage.Advantage provided by the invention provides that significantly to have reduced burst-mode receiver be the quantity that reaches balanced required lead code.This converts the upstream bandwidth that increases on the EPON to.
In an embodiment of the invention, a kind of method that is used to make optical receiver can receive from the signal of a plurality of optical network units that are in different optical power levels comprises: collect received signal intensity indication (RSSI) information from the data flow of the front of optical network unit, and based on adjust the reception of optical receiver with the data flow that enters subsequently of optimizing this optical network unit from the received signal intensity indication information that data flow received of front.Estimating received signal intensity was indicated after this method also was included in predetermined interval, estimating received signal intensity indication when utilizing the collected received signal intensity in front to indicate to adjust optical receiver, perhaps estimating received signal intensity indication when utilizing the collected received signal intensity in front to indicate to adjust optical receiver.This method can comprise the received signal intensity indication information that storage is collected in addition, the collected received signal intensity indication information of link optical network unit, and the tracing table that generates the collected received signal intensity indication information of optical network unit, wherein collection occurs in the media access controller and wherein adjusts from media access controller and sends.Another embodiment of the invention can have by the RSSI level of system user defined during system start-up rather than by the measured RSSI level of the circuit in the receiver.
In yet another embodiment of the present invention, computer-readable medium comprises instruction, this instruction is used for the data flow estimating received signal intensity indication from the front of optical network unit, the estimated received signal intensity indication of link optical network unit, and based on adjusting the reception of optical-fiber network receiver with the data flow that enters subsequently of optimization optical network unit from the received signal intensity that data flow the received indication of front.Computer-readable medium also can comprise the instruction, the instruction of look-up table that is used to store the instruction of collected received signal intensity indication information and is used to generate the collected received signal intensity indication information of optical network unit of received signal intensity indication of the data flow of the front that is used to collect optical network unit, wherein after predetermined interval, estimate, when adjusting optical receiver, take place to estimate or after adjusting optical receiver, estimate.Another embodiment of the invention can have by the RSSI level of system user defined during system start-up rather than by the measured RSSI level of the circuit in the receiver.
In another execution mode, the system of burst mode optical receiver comprises memory and the media access controller that can be coupled to memory communicatedly, media access controller is suitable for estimating the received signal intensity indication of optical network unit, and adjusts the reception of optical receiver with the data flow that enters of optimization optical network unit based on received signal intensity indication information by applying the first control voltage, the second control voltage and the 3rd control voltage.This system also can comprise: first transreactance amplifier, have anti-phase output, and this first transreactance amplifier has non-return output; First resistor is connected to first transreactance amplifier and oppositely exports; Second resistor is connected to the non-return output of first transreactance amplifier; First capacitor is connected to first transreactance amplifier and oppositely exports, and this first capacitor and first resistor are connected in parallel; Second capacitor is connected to the non-return output of first transreactance amplifier, and this second capacitor and second resistor are connected in parallel; The 3rd capacitor is connected to first resistor, and the 3rd capacitor has the capacitance less than first capacitor; The 4th capacitor is connected to second resistor, and the 4th capacitor has the capacitance less than second capacitor; First limiting amplifier has reverse input that is connected to the 3rd capacitor and the non-return input that is connected to the 4th capacitor; The first transistor has the grid that receives the first control voltage, and this first transistor has the drain electrode that is connected to supply voltage, and this first transistor has the source electrode that is connected to first resistor; Transistor seconds has the grid that receives the second control voltage, and this transistor seconds has the drain electrode that is connected to the first transistor source electrode, and this transistor seconds has the source electrode of ground connection; The 3rd transistor has the grid that receives the first control voltage, and the 3rd transistor has the drain electrode that is connected to supply voltage, and the 3rd transistor has the source electrode that is connected to second resistor; The 4th transistor has the grid that receives the second control voltage, and the 4th transistor has the drain electrode that is connected to described the 3rd transistor source, and the 4th transistor has the source electrode of ground connection; The 5th transistor has the grid that receives the 3rd control voltage, and the 5th transistor has the drain electrode that is connected to supply voltage, and the 5th transistor has the source electrode that is connected to the non-return input of first limiting amplifier; And the 6th transistor, having the grid that receives the 3rd control voltage, the 6th transistor has the drain electrode that is connected to supply voltage, and the 6th transistor has and is connected to the oppositely source electrode of input of first limiting amplifier.
An optional execution mode of the native system among Fig. 4 also can comprise: second transreactance amplifier, have reverse output, and this second transreactance amplifier has non-return output; The 3rd resistor is connected to the non-return output of described second transreactance amplifier; The 5th capacitor is connected to the 3rd resistor; The 4th resistor is connected to second transreactance amplifier and oppositely exports; The 6th capacitor is connected to the 4th resistor; Second limiting amplifier has non-return input that is connected to the 5th capacitor and the reverse input that is connected to the 6th capacitor; The 7th transistor has the drain electrode that is connected to the non-return output of second transreactance amplifier, and the 7th transistor has the grid that is connected to the reset terminal (reset junction) that receives the 3rd control voltage, and the 7th transistor has source electrode; The 8th transistor has the drain electrode that is connected to the reverse output of second transreactance amplifier, and the 8th transistor has the grid that is connected to reset terminal, and the 8th transistor has source electrode; The 5th resistor is connected to the non-return input of second limiting amplifier; The 6th resistor is connected to second limiting amplifier and oppositely imports, and the 6th resistor is connected to the 5th resistor; Buffer amplifier, has the reverse input that is connected to the 7th transistor source, this buffer amplifier oppositely input is connected to the 8th transistor source, this buffer amplifier output is connected to buffer amplifier and oppositely imports, this buffer output is connected to the 5th resistor, this buffer output is connected to the 6th resistor, and this buffer amplifier has non-return input; And, the 7th capacitor, the 7th capacitor grounding, the 7th capacitor are connected to the non-return input of buffer amplifier.
In another execution mode of native system in Fig. 5, can comprise: second transreactance amplifier, have reverse output, this second transreactance amplifier has non-return output; The 3rd resistor is connected to the non-return output of second transreactance amplifier; The 5th capacitor is connected to the 3rd resistor; The 4th resistor is connected to second transreactance amplifier and oppositely exports; The 6th capacitor is connected to the 4th resistor; Second limiting amplifier has reverse input that is connected to the 5th capacitor and the non-return input that is connected to the 6th capacitor; The 7th transistor has the drain electrode that is connected to the non-return output of second transreactance amplifier, and the 7th transistor has the grid that is connected to the knot that resets that receives the 3rd control voltage, and the 7th transistor has source electrode; The 8th transistor has the drain electrode that is connected to the reverse output of second transreactance amplifier, and the 8th transistor has the grid that is connected to reset terminal, and the 8th transistor has source electrode, and the 8th transistor source is connected to the 7th transistor source; The 5th resistor is connected to the non-return input of second limiting amplifier; The 6th resistor is connected to second limiting amplifier and oppositely imports, and the 6th resistor is connected to the 5th resistor, and the 6th resistor is connected to the 8th transistor source with being connected of the 5th resistor; The 7th resistor, be connected to the 5th with being connected of the 6th resistor; Buffer amplifier has reverse input, and this buffer amplifier has the output that is connected to the reverse input of buffer amplifier, and this buffer output is connected to the 7th resistor, and this buffer amplifier has non-return input; The 7th capacitor, the 7th capacitor grounding, the 7th capacitor are connected to the non-return input of buffer amplifier; The 8th capacitor is connected to the 7th transistorized source electrode, the 8th capacitor grounding; And the 9th capacitor, be connected to the 8th transistor source, the 9th capacitor grounding.
Description of drawings
Fig. 1 illustrates first execution mode according to the system of the burst mode optical receiver of preferred implementation of the present invention;
Fig. 2 illustrates the expense agreement of GPON standard G.984 according to ITU;
Fig. 3 illustrates the system of the burst mode optical receiver that has the AC coupling but do not reset;
Fig. 4 illustrates second execution mode according to the system of the burst mode optical receiver of preferred implementation of the present invention;
Fig. 5 illustrates the 3rd execution mode according to the system of the burst mode optical receiver of preferred implementation of the present invention;
Fig. 6 illustrates first method flow diagram according to the burst mode optical receiver of preferred implementation of the present invention;
Fig. 7 illustrates second method flow diagram according to the burst mode optical receiver of preferred implementation of the present invention;
Fig. 8 illustrates the third party's method flow chart according to the burst mode optical receiver of preferred implementation of the present invention;
Fig. 9 illustrates first software flow pattern according to the burst mode optical receiver of preferred implementation of the present invention;
Figure 10 illustrates second software flow pattern according to the burst mode optical receiver of preferred implementation of the present invention; And
Figure 11 illustrates the 4th execution mode according to the system of the burst mode optical receiver of preferred implementation of the present invention.
Embodiment
Referring now to Fig. 1, show first system 10 of burst mode optical receiver.First execution mode of the present invention comprises first transreactance amplifier 12, and this amplifier comprises reverse output 14 and non-return output 16.First resistor 18 is connected to the oppositely output and second resistor 20 is connected to non-return output of first transreactance amplifier.First capacitor 22 is connected to first transreactance amplifier and oppositely exports, and wherein first capacitor is in parallel with first resistor.Second capacitor 24 is connected to the non-return output of first transreactance amplifier, and wherein second capacitor is in parallel with second resistor.The 3rd capacitor 26 is connected to first resistor and has capacitance less than first capacitor.The 4th capacitor 28 is connected to second resistor and has capacitance less than second capacitor.First limiting amplifier 30 has reverse input 32 and is connected to the 3rd capacitor.First limiting amplifier has the non-return input 34 that is connected to the 4th capacitor.The first transistor 36 has the grid 38 that receives the first control voltage, the source electrode 42 that is connected to the drain electrode 40 of supply voltage and is connected to first resistor.Transistor seconds 44 has the source electrode 48 of the grid 46, the drain electrode that is connected to the first transistor source electrode and the ground connection that receive the second control voltage.The 3rd transistor 50 has the grid 52 that receives the first control voltage, the source electrode 56 that is connected to the drain electrode 54 of supply voltage and is connected to second resistor.The 4th transistor 58 has the source electrode 62 of the grid 60, the drain electrode that is connected to the 3rd transistor source and the ground connection that receive the second control voltage.The 5th transistor 64 has the grid 66 that receives the 3rd control voltage, the source electrode 70 that is connected to the drain electrode 68 of supply voltage and is connected to the non-return input of first limiting amplifier.The 6th transistor 72 has the grid 74 that receives the 3rd control voltage, the source electrode 78 that is connected to the drain electrode 76 of supply voltage and is connected to the reverse input of first limiting amplifier.These pieces or module are the combinations of software, hardware, firmware and/or software, hardware and/or firmware.
The present invention utilize passive optical network media access controller knowledge so that to alternating current (AC) thus coupling capacitor adjustment reduces the recovery time between the required last row cell of optics.The present invention does not rely on mould/number (A/D) and D/A (D/A) thereby transducer will be sent into optical receiver from the information of media access controller and adjust AC coupling capacitor voltage.Passive optical network media access controller utilizes the anticipatory knowledge of the last row cell luminous power front and subsequently to determine that how many electric charges will be injected in the coupling capacitor between TIA and the LIMA.Advantage provided by the invention is that significantly to have reduced burst-mode receiver be the quantity that reaches balanced required lead code.This converts the upstream bandwidth that increases on the EPON to.
Left-hand side of the present invention is the difference output from transreactance amplifier (TIA).The right-hand side device is the input of limiting amplifier (LIMA) difference.In typical Ethernet passive optical network (EPON) type optical module, these two devices (TIA/LIMA) are to utilize the single series capacitor of every section differential signal being similar to Fig. 3 (for example 26 and 28) and AC coupled to each other.
Because the output signal from TIA has and the proportional common-mode voltage of being seen by photodiode in the TIA input of average light power, so TIA and LIMA are the AC couplings.LIMA requires its input to be biased to constant common-mode voltage (VBB).Therefore, the voltage V R-C between a R and some C takes different values according to the average light power that is received.
Current, Ethernet passive optical network (EPON) design needs a large amount of lead codes, thereby the AC capacitor has the time of charge or discharge to suitable value.This reason that will spend the relatively long time be because: for fear of the unwanted decay that will worsen receiver sensitivity, the biasing circuit in the LIMA input is a high impedance.Yet the high input impedance of LIMA has reduced the magnitude of current that can draw from the output of TIA.Need this TIA output current that coupling capacitor is charged to end value just, and less current is converted into the long time so that capacitor reaches stable.During this stabilization time, the signal of LIMA input does not concentrate on VBB, and the rapid Duty Cycle Distortion of LIMA generation, and this will stop activation clock recovery device, till Duty Cycle Distortion disappears.Required a large amount of lead codes are equivalent to waste 20% upstream bandwidth.
The present invention utilize PON MAC to received signal intensity indication (RSSI) information receive, to adjust the coupling capacitor on the optical receiver before arriving in data flow.
During the guard time 62 between upstream packet (also can referring to the label among Fig. 2 84), passive optical network media access controller be asserted CNTL3 (assert) becomes Q5 and Q6 transistor.This will remain on VBB with node C by Low ESR.Then media access controller will apply variable-length pulse to CNTL1 or CNTL2.CNTL1 is used to promote the voltage on the coupling capacitor, and CNTL2 is used to reduce the voltage on the coupling capacitor.The control of the width of pulse is injected into Node B or the quantity of the electric charge removed from Node B.In this way, voltage V B-C can rapid adjustment to the random desired value between 3.3V and the ground.After the of short duration time, all CNTL signals all will be disengaged and assert; Then, with respect to the primary signal path, adjusting circuit becomes high impedance, so that do not worsen the sensitivity of receiver during normal running.Because C1＞＞C3, most of AC coupled voltages shows as crosses over capacitor C3 (V B '-C '), and can be adjusted fully by media access controller.Therefore the voltage on the capacitor C1 is zero or very approaching zero.Resistor R 1 is used to keep capacitor C1 discharging (by discharging).In optional execution mode, replace resistor R 1 with field-effect transistor (FET).
This circuit is characterised in that the tracing table of setting up media access controller in advance.Next grouping is in power stage Y if the grouping of front is in power stage X, and then tracing table will show whether drive CNTL1 or CNTL2, and how long drive it.Final result is that coupling capacitor will be in correct common-mode voltage before guard time finishes, thus when lead code begins, near the signal of LIMA input has concentrated on VBB, the Duty Cycle Distortion that this will stop the data of LIMA to be exported.
Referring now to Fig. 2, show expense agreement 80.This agreement comprises the cell data stream 82 of front, follows by guard time 84, is the lead code 86 before the payload data 88 of subsequently data flow after guard time.
Referring now to Fig. 3,90 expressions have AC coupling but the typical prior art system of the burst mode optical receiver that do not reset.This system has the transreactance amplifier 92 of communicating by letter with optical receiver 96.Transreactance amplifier is connected to limiting amplifier 94, and this limiting amplifier relies on discharging (bleed down) resistor 98 that biasing is set.Capacitor C1 and C2 form the RC circuit with R11 and R12, and this circuit has the time constant of 100pF * 5kohm=500ns.This means that when the data rate of 1244Mb/s this will take 600 bits (75 bytes) and recover the conversion from the cell to the cell.
If can shorten this discharge time,, can save many bytes of lead code then in the transition period.This can set up by utilizing the equilibrium of reset circuit accelerated charge.
Referring now to Fig. 4, show second system 150 of burst mode optical receiver.Second execution mode of the present invention comprises second transreactance amplifier 152 with reverse output 154 and non-return output 156.The 3rd resistor 158 is connected to the non-return output of second transreactance amplifier.The 5th capacitor 160 is connected to the 3rd resistor.The 4th resistor 162 is connected to second transreactance amplifier and oppositely exports.The 6th capacitor 164 is connected to the 4th resistor.Second limiting amplifier 166 has non-return input 168 that is connected to the 5th capacitor and the reverse input 170 that is connected to the 5th capacitor.The grid 174 that the 7th transistor 172 has the drain electrode that is connected to the non-return output of second transreactance amplifier and is connected to the knot that resets that receives the 3rd control voltage.The 7th transistor has source electrode 176.The grid that the 8th transistor 178 has the drain electrode that is connected to the reverse output of second transreactance amplifier and is connected to the knot that resets.The 8th transistor has source electrode.The 5th resistor 180 is connected to the non-return input of second limiting amplifier.The 6th resistor 182 is connected to second limiting amplifier and oppositely imports.The 6th resistor is connected to the 5th resistor.Buffer amplifier 184 has the reverse input 186 that is connected to the 7th transistor source and is connected to the oppositely output 188 of input of buffer amplifier.Buffer output is connected to the 5th and the 6th resistor.Buffer amplifier has non-return input 190.The 7th capacitor 192 ground connection; The 7th capacitor is connected to the non-return input of buffer amplifier.
The quiescent voltage of crossing over capacitor will depend on the input optical power level thereby coupling capacitor is discharged, and this is the desirable bias point that is used for limiting amplifier (LIMA) input.VBB generates in LIMA, but has limited driving force.We advise inserting the buffer amplifier with high impedance input and Low ESR output, and it follows the tracks of input voltage and the VBB that do not load LIMA exports.The low output impedance of buffer amplifier (less than 10ohm) will approximately discharge to the 100pF capacitor in the 1ns; This is than there not being fast 500 times of reset circuit.
With reference now to Fig. 5,, the tertiary system system 200 of burst mode optical receiver is shown.In the 3rd execution mode of the present invention, second transreactance amplifier 202 has reverse output 204 and non-return output 206.The 3rd resistor 208 is connected to the non-return output of second transreactance amplifier.The 5th capacitor 210 is connected to the 3rd resistor.The 4th resistor 212 is connected to second transreactance amplifier and oppositely exports.The 6th capacitor 214 is connected to the 4th resistor.Second limiting amplifier 216 has reverse input 218 that is connected to the 6th capacitor and the non-return input 220 that is connected to the 5th capacitor.The 7th transistor 222 has the drain electrode that is connected to the non-return output of second transreactance amplifier and has the grid that is connected to the reset terminal 224 that receives the 3rd control voltage.The 7th transistor has source electrode.The 8th transistor 226 has drain electrode that is connected to the reverse output of second transreactance amplifier and the grid that is connected to reset terminal.The 8th transistor has the source electrode that is connected to the 7th transistor source.The 5th resistor 228 is connected to the non-return input of second limiting amplifier.The 6th resistor 230 is connected to second limiting amplifier and oppositely imports.The 6th resistor is connected to the 5th resistor.The tie-point of the 6th resistor and the 5th resistor (junction) locates to be connected to the 8th transistor source.The 7th resistor 232 is connected to the junction of the 5th and the 6th resistor.Buffer amplifier 234 has output 238 and the oppositely input 236 that is connected to reverse input of buffer amplifier and the 7th resistor.Buffer amplifier has non-return input 240.The 7th capacitor 242 ground connection and be connected to the non-return input of buffer amplifier.The 8th capacitor 244 is connected to the 7th transistor source and ground connection.The 9th capacitor 246 is connected to the 8th transistor source and ground connection.
The present invention has applied the reset signal that is generally for 10 to short time of 20ns.Coupling capacitor will be recharged or discharge, thereby is acceptable fully in end's data of reset pulse.Existing solution will need various time spans to finish conversion: the level difference between cell is big more, and the time that then obtains acceptable data is just long more.Utilize this new method that capacitor on the AC coupling circuit is carried out charge or discharge, can significantly shorten lead code, thereby obtain bandwidth bigger on the EPON.
Reset pulse will discharge by the cell level to the front during guard time.When new cell arrives and begin lead code, only need several bits to charge the capacitor to required level.The speed of charging depends on switch ON resistance and TIA output impedance, but very short usually.
Referring now to Fig. 6, show the first pass figure of the method 250 of the auxiliary clock recovery of passive optical network media access controller.This method makes optical receiver from being in a plurality of optical network unit received signals of different optical power levels, comprise: collect 252 received signal intensity indication informations from the data flow of the front of optical network unit, and adjust 254 optical receivers based on the received signal intensity indication information that data flow received from the front, with the reception of the data flow that enters subsequently of optimizing this optical network unit.This method can be implemented by the combination of software, hardware, firmware and/or software, hardware and/or firmware.
Referring now to Fig. 7, show second flow chart of the method 260 of passive optical network media access controller auxiliary clock recovery.This method makes optical receiver from being in a plurality of optical network unit received signals of different optical power levels, comprise: collect 262 received signal intensity indication informations from the data flow of the front of optical network unit, and based on adjust the reception of 264 optical receivers with the data flow that enters subsequently of optimizing optical network unit from the received signal intensity indication information that data flow received of front.This method also comprises utilizes the collected received signal intensity indication information in front to estimate that the indication of 266 received signal intensity is to adjust optical receiver, store 268 collected received signal intensity indication informations, link the collected received signal intensity indication information of 270 optical network units, and the tracing table that generates the collected received signal intensity indication information of 272 optical network units.This method can be implemented by the combination of software, hardware, firmware and/or software, hardware and/or firmware.
Referring now to Fig. 8, show the 3rd flow chart of the method 280 of passive optical network media access controller auxiliary clock recovery.This method makes optical receiver from being in a plurality of optical network unit received signals of different optical power levels, comprise: collect 282 received signal intensity indication informations from the data flow of the front of optical network unit, and based on adjusting of the reception of 284 optical receivers from the received signal intensity indication information that data flow received of front, and when utilizing the collected received signal intensity in front to indicate to adjust optical receiver, estimate the indication of 286 received signal intensity with the data flow that enters subsequently of optimizing optical network unit.This method can be implemented by the combination of software, hardware, firmware and/or software, hardware and/or firmware.
With reference now to Fig. 9,, shows first software flow pattern of the method 300 of passive optical network media access controller auxiliary clock recovery.This computer-readable medium comprises and is used for following instruction: estimate the indication of 302 received signal intensity from the data flow of the front of optical network unit, link the estimated received signal intensity indication information of 304 optical network units, and based on adjust the reception of 306 optical receivers with the data flow that enters subsequently of optimization optical network unit from the received signal intensity indication information that data flow received of front.Under the prerequisite that does not depart from the scope of the present invention, these steps can be by softwares but can also be implemented by the combination of hardware, firmware and/or software, hardware and/or firmware.
Referring now to Figure 10, show second software flow pattern of the method 310 of passive optical network media access controller auxiliary clock recovery.This computer-readable medium comprises and is used for following instruction: estimate the indication of 312 received signal intensity from the data flow of the optical network unit of front, link the estimated received signal intensity indication information of 314 optical network units, and based on adjust the reception of 316 optical receivers with the data flow that enters subsequently of optimization optical network unit from the received signal intensity indication information that data flow received of front.This computer-readable medium also comprises and is used for following instruction, collect the received signal intensity indication information of data flow of the front of 318 optical network units, store 320 collected received signal intensity indication informations, and the tracing table that generates the collected received signal intensity indication information of 322 optical network units.Under the prerequisite that does not depart from the scope of the present invention, these steps can be by softwares but can also be implemented by the combination of hardware, firmware and/or software, hardware and/or firmware.
Referring now to Figure 11, show the Quaternary system system 330 of burst mode optical receiver.The 4th execution mode of the present invention comprises memory 332 and can be coupled 336 media access controllers 334 to memory communicatedly, this media access controller is suitable for estimating the received signal intensity indication 342 of 338 optical network units and adjusts 340 optical receivers based on the indication of received signal intensity by applying the first control voltage, the second control voltage and the 3rd control voltage, the reception of the data flow of the optical network unit that enters with optimization.
Although the illustrative embodiments of system of the present invention has been illustrated in the accompanying drawings and describe in detail above, be appreciated that, under the prerequisite that does not break away from the spirit of the present invention that proposes and limit by following claims, the invention is not restricted to disclosed execution mode, but can have a plurality of rearrangements, change and replacement.For example, ability of the present invention can be come part or execution all sidedly by one or more ONT, OLT or media access controller.In addition, these abilities can be worked as that previous mode is carried out or carry out with distributed way, and can provide and/or any device of receiving wide-band signal on carry out, or via providing and/or any device of receiving wide-band signal is carried out.In addition, although illustrate in a particular manner, various modules or piece can reconfigure under the prerequisite that does not depart from the scope of the present invention.For example, can be autonomous type by the performed function of media access controller.In addition, although illustrate in a particular manner, can use ONT, the OLT of more or less number or media access controller according to the present invention to finish the present invention, to the invention provides additional known features and/or making the present invention more effective.In addition, for example, the MAC of memory communication can insert by cell phone, computer with external wireless ability (for example unruled card) or internal wireless ability (for example 802.11 or other 802 variants) arbitrarily, insert by the phone of supporting Internet protocol, or insert by any apparatus that can send and/or receive information.Communication as described herein via wireless protocols, wire protocol and/or wireless protocols are arranged and have at least a of combination of wire protocol to carry out.As described herein or module are the combinations of software, hardware and/or software, hardware and/or firmware.
Claims (10)
1. one kind is used to make optical receiver to comprise from the method for a plurality of optical network unit received signals of being in different optical power levels:
Collect received signal intensity indication information from the data flow of the front of optical network unit; And
Based on the received signal intensity indication information that receives from the data flow of described front, adjust optical receiver, with the reception of the data flow that enters subsequently of optimizing described optical network unit.
2. method according to claim 1 is included in predetermined interval and estimates described received signal intensity indication afterwards.
3. method according to claim 1 is included in and estimates described received signal intensity indication when utilizing the collected received signal intensity in front to indicate to adjust described optical receiver.
4. method according to claim 1 is included in and estimates described received signal intensity indication when utilizing the collected received signal intensity in front to indicate to adjust described optical receiver.
5. method according to claim 1 comprises the received signal intensity indication information that storage is collected.
6. method according to claim 1 comprises the collected received signal intensity indication information that links described optical network unit.
7. system that is used for burst mode optical receiver comprises:
Memory; And
Can be coupled to the media access controller of described memory communicatedly, described media access controller is suitable for:
Estimate the received signal intensity indication of optical network unit; And
Based on received signal intensity indication information, adjust optical receiver by applying the first control voltage, the second control voltage and the 3rd control voltage, with the reception of the data flow that enters of optimizing described optical network unit.
8. system according to claim 7 comprises:
First transreactance amplifier has anti-phase output, and described first transreactance amplifier has non-return output;
First resistor is connected to described first transreactance amplifier and oppositely exports;
Second resistor is connected to the non-return output of described first transreactance amplifier;
First capacitor is connected to described first transreactance amplifier and oppositely exports, and described first capacitor and described first resistor are connected in parallel;
Second capacitor is connected to the non-return output of described first transreactance amplifier, and described second capacitor and described second resistor are connected in parallel;
The 3rd capacitor is connected to described first resistor, and described the 3rd capacitor has the capacitance less than described first capacitor;
The 4th capacitor is connected to described second resistor, and described the 4th capacitor has the capacitance less than second capacitor;
First limiting amplifier has reverse input that is connected to described the 3rd capacitor and the non-return input that is connected to described the 4th capacitor;
The first transistor has the grid that receives the described first control voltage, and described the first transistor has the drain electrode that is connected to supply voltage, and described the first transistor has the source electrode that is connected to described first resistor;
Transistor seconds has the grid that receives the described second control voltage, and described transistor seconds has the drain electrode that is connected to the first transistor source electrode, and described transistor seconds has the source electrode of ground connection;
The 3rd transistor has the grid that receives the described first control voltage, and described the 3rd transistor has the drain electrode that is connected to supply voltage, and described the 3rd transistor has the source electrode that is connected to described second resistor,
The 4th transistor has the grid that receives the described second control voltage, and described the 4th transistor has the drain electrode that is connected to described the 3rd transistor source, and described the 4th transistor has the source electrode of ground connection;
The 5th transistor has the grid that receives described the 3rd control voltage, and described the 5th transistor has the drain electrode that is connected to supply voltage, and described the 5th transistor has the source electrode that is connected to the non-return input of first limiting amplifier; And
The 6th transistor has the grid that receives described the 3rd control voltage, and described the 6th transistor has the drain electrode that is connected to supply voltage, and described the 6th transistor has the source electrode that is connected to the reverse input of described first limiting amplifier.
9. system according to claim 7 comprises:
Second transreactance amplifier has reverse output, and described second transreactance amplifier has non-return output;
The 3rd resistor is connected to the non-return output of described second transreactance amplifier;
The 5th capacitor is connected to described the 3rd resistor;
The 4th resistor is connected to described second transreactance amplifier and oppositely exports;
The 6th capacitor is connected to described the 4th resistor;
Second limiting amplifier has non-return input that is connected to described the 5th capacitor and the reverse input that is connected to described the 6th capacitor;
The 7th transistor has the drain electrode that is connected to the non-return output of described second transreactance amplifier, and described the 7th transistor has the grid that is connected to the reset terminal that receives described the 3rd control voltage, and described the 7th transistor has source electrode;
The 8th transistor has the drain electrode that is connected to the reverse output of described second transreactance amplifier, and described the 8th transistor has the grid that is connected to described reset terminal, and described the 8th transistor has source electrode;
The 5th resistor is connected to the non-return input of second limiting amplifier;
The 6th resistor is connected to described second limiting amplifier and oppositely imports, and described the 6th resistor is connected to described the 5th resistor;
Buffer amplifier, has the reverse input that is connected to described the 7th transistor source, described buffer amplifier oppositely input is connected to described the 8th transistor source, described buffer amplifier output is connected to described buffer amplifier and oppositely imports, described buffer output is connected to described the 5th resistor, described buffer output is connected to described the 6th resistor, and described buffer amplifier has non-return input; And
The 7th capacitor of ground connection, described the 7th capacitor is connected to the non-return input of described buffer amplifier.
10. system according to claim 7 comprises:
Second transreactance amplifier has reverse output, and described second transreactance amplifier has non-return output;
The 3rd resistor is connected to the non-return output of described second transreactance amplifier;
The 5th capacitor is connected to described the 3rd resistor;
The 4th resistor is connected to described second transreactance amplifier and oppositely exports;
The 6th capacitor is connected to described the 4th resistor;
Second limiting amplifier has non-return input that is connected to described the 5th capacitor and the reverse input that is connected to described the 6th capacitor;
The 7th transistor has the drain electrode that is connected to the non-return output of described second transreactance amplifier, and described the 7th transistor has the grid that is connected to the reset terminal that receives described the 3rd control voltage, and described the 7th transistor has source electrode;
The 8th transistor, have and be connected to the oppositely drain electrode of output of described second transreactance amplifier, described the 8th transistor has the grid that is connected to described reset terminal, and described the 8th transistor has source electrode, and described the 8th transistor source is connected to described the 7th transistor source;
The 5th resistor is connected to the non-return input of described second limiting amplifier;
The 6th resistor is connected to described second limiting amplifier and oppositely imports, and described the 6th resistor is connected to described the 5th resistor, described the 6th resistor be connected to described the 8th transistor source being connected of described the 5th resistor;
The 7th transistor, be connected to the described the 5th with being connected of the 6th resistor;
Buffer amplifier, have reverse input, described buffer amplifier has the output that is connected to the reverse input of described buffer amplifier, and described buffer output is connected to described the 5th resistor, described buffer output is connected to described the 7th resistor, and described buffer amplifier has non-return input;
The 7th capacitor of ground connection, described the 7th capacitor is connected to the non-return input of buffer amplifier;
The 8th capacitor is connected to described the 7th transistor source, described the 8th capacitor grounding; And
The 9th capacitor is connected to described the 8th transistor source, described the 9th capacitor grounding.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US74009905P | 2005-11-28 | 2005-11-28 | |
| US60/740,099 | 2005-11-28 | ||
| US11/383,110 US7764886B2 (en) | 2005-11-28 | 2006-05-12 | Burst mode optical receiver |
| US11/383,110 | 2006-05-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1976260A true CN1976260A (en) | 2007-06-06 |
| CN1976260B CN1976260B (en) | 2012-06-20 |
Family
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Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200610146896XA Expired - Fee Related CN1976260B (en) | 2005-11-28 | 2006-11-27 | Burst mode optical receiver |
| CN200610146894.0A Expired - Fee Related CN1983881B (en) | 2005-11-28 | 2006-11-27 | Passive optical network media access controller assisted clock recovery |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200610146894.0A Expired - Fee Related CN1983881B (en) | 2005-11-28 | 2006-11-27 | Passive optical network media access controller assisted clock recovery |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN1976260B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106664236A (en) * | 2015-06-10 | 2017-05-10 | 华为技术有限公司 | Signal transmission method, controller and signal transmission system |
| CN113824506A (en) * | 2020-06-20 | 2021-12-21 | 华为技术有限公司 | Optical signal processing method, optical transceiver, controller and optical line terminal |
| CN114339481A (en) * | 2020-09-30 | 2022-04-12 | 上海诺基亚贝尔股份有限公司 | Method, apparatus, device and computer readable medium for optical communication |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8265484B2 (en) * | 2009-12-15 | 2012-09-11 | Broadcom Corporation | RF signal transport over passive optical networks |
| US9621972B2 (en) * | 2015-07-29 | 2017-04-11 | Rockley Photonics Limited | Burst-mode receiver |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5590140A (en) * | 1994-12-30 | 1996-12-31 | Lucent Technologies Inc. | Clock recovery extrapolation |
| JP3655770B2 (en) * | 1999-03-29 | 2005-06-02 | 日本電気株式会社 | Optical receiver circuit |
| US7151813B2 (en) * | 2002-07-17 | 2006-12-19 | Intel Corporation | Techniques to reduce transmitted jitter |
| CN1291341C (en) * | 2003-01-30 | 2006-12-20 | 烽火通信科技股份有限公司 | Method and apparatus for realizing Ethernet passive optical network system dynamic filtration data base |
-
2006
- 2006-11-27 CN CN200610146896XA patent/CN1976260B/en not_active Expired - Fee Related
- 2006-11-27 CN CN200610146894.0A patent/CN1983881B/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106664236A (en) * | 2015-06-10 | 2017-05-10 | 华为技术有限公司 | Signal transmission method, controller and signal transmission system |
| CN106664236B (en) * | 2015-06-10 | 2019-11-12 | 华为技术有限公司 | A kind of method for transmitting signals, controller and signal transmission system |
| CN113824506A (en) * | 2020-06-20 | 2021-12-21 | 华为技术有限公司 | Optical signal processing method, optical transceiver, controller and optical line terminal |
| WO2021254225A1 (en) * | 2020-06-20 | 2021-12-23 | 华为技术有限公司 | Optical signal processing method, optical transceiver, controller and optical line terminal |
| CN114339481A (en) * | 2020-09-30 | 2022-04-12 | 上海诺基亚贝尔股份有限公司 | Method, apparatus, device and computer readable medium for optical communication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1983881B (en) | 2014-09-03 |
| CN1983881A (en) | 2007-06-20 |
| CN1976260B (en) | 2012-06-20 |
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