CN1975931A

CN1975931A - Non-volatile semiconductor memory device

Info

Publication number: CN1975931A
Application number: CNA200610162911XA
Authority: CN
Inventors: 河合贤; 东亮太郎; 川原昭文; 诹访仁史; 春山星秀
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2005-11-29
Filing date: 2006-11-29
Publication date: 2007-06-06
Also published as: JP2007149241A; US20070133277A1

Abstract

The invention provides a memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.

Description

Non-volatile memory semiconductor device

The cross reference of related application

The present invention speciallys permit 2005-343479 number the disclosed content of instructions, accompanying drawing, claims with reference to the Japan in application on November 29th, 2005, and is fully incorporated in this.

Technical field

The present invention relates to a kind of non-volatile memory semiconductor device that the multiple threshold voltage distribution states of use is stored the memory of data unit that has.

Background technology

In non-volatile memory semiconductor device, have by the threshold voltage distribution that changes storer and store the memory of data part.In the past, when in such non-volatile memory semiconductor device, carrying out the rewriting of data, with pre-programmed (preprogram), wipe, write this triphasic rewriting order (sequence) and carry out the rewriting (for example with reference to TOHKEMY 2001-250388 communique) of data.

Specifically, the state that random data is written into temporarily becomes the state (pre-programmed) that data all are " 0 ".Afterwards, threshold voltage distribution is moved so that data all become state " 1 ".Then, threshold voltage distribution is moved, implement writing of random data according to the data that the user gave.

Yet, in rewriting order in the past as described above, need carry out pre-programmed and wipe this two stage action from before the writing of user's random data implementing, therefore be difficult to carry out high speed rewriting.For example, in pre-programmed, wipe, random data writes under the situation of the time that all spends same degree, the rewriting needed time of order is approximately 3 times of random data write time.

Summary of the invention

The present invention is conceived to the problems referred to above and makes, and its purpose is to realize a kind of non-volatile memory semiconductor device that can shorten the time that is used for the rewriting order.

For solving above-mentioned problem, a scheme of the present invention is:

A kind of non-volatile memory semiconductor device carries out writing and reading of data according to the instruction of being imported, and it is characterized in that, comprising:

Memory cell array comprises a plurality of memory cells that have the state of the threshold voltage distribution more than 3 at single charge storage position; With

The programmed order control circuit, each data that contained in the data set (data set) that will constitute by the data of a plurality of values, be stored in above-mentioned memory cell accordingly with any threshold voltage distribution in the above-mentioned threshold voltage distribution more than 3, and when rewriting is stored in the data of above-mentioned memory cell, make the threshold voltage distribution of in the storage of data, using move the rewriting of carrying out data to a direction.

Thus, the threshold voltage distribution of memory cell is moved overwriting data to a direction, therefore do not need erasing move, can reduce the rewriting time significantly.

Description of drawings

Fig. 1 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 1.

Fig. 2 is the figure of the transition state of the Vt level distribution when being illustrated in overwriting data in the embodiments of the present invention 1.

Fig. 3 is the process flow diagram of the write sequence of expression embodiments of the present invention 1.

Fig. 4 is the process flow diagram of the write sequence of expression embodiments of the present invention 2.

Fig. 5 is the figure of the transition state of the Vt level distribution when being illustrated in overwriting data in the embodiments of the present invention 2.

Fig. 6 is the process flow diagram of the write sequence of expression embodiments of the present invention 3.

Fig. 7 is the figure of the transition state of the Vt level distribution when being illustrated in overwriting data in the embodiments of the present invention 3.

Fig. 8 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 4.

Fig. 9 is the block diagram of the setting of reading decision level in the embodiments of the present invention 4.

Figure 10 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 5.

Figure 11 is expressed as the figure that concerns between threshold voltage distribution position of storing 2 Value Datas and using and the writing position of the monitoring position (monitor bit).

Figure 12 is the block diagram of the setting of reading decision level in the embodiments of the present invention 5.

Figure 13 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 5.

Figure 14 is the figure of the transition state of the Vt level distribution when being illustrated in overwriting data in the embodiments of the present invention 6.

Figure 15 is the process flow diagram of the write sequence of expression embodiments of the present invention 6.

Figure 16 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 7.

Figure 17 is the block diagram of the setting of reading decision level in the embodiments of the present invention 7.

Figure 18 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 8.

Figure 19 is the figure of the transition state of the Vt level distribution when being illustrated in overwriting data in the embodiments of the present invention 8.

Figure 20 is the process flow diagram of the write sequence of expression embodiments of the present invention 8.

Figure 21 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 9.

Figure 22 is the figure of the transition state of the Vt level distribution when being illustrated in overwriting data in the embodiments of the present invention 9.

Figure 23 is the process flow diagram of the compressed action of expression embodiment 8.

Figure 24 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 10.

Figure 25 is the block diagram of the setting of reading decision level in the embodiments of the present invention 10.

Figure 26 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 11.

Figure 27 is the process flow diagram of the compressed action of expression embodiment 11.

Figure 28 is the block diagram of the setting of the readout mode in the embodiments of the present invention 11.

Figure 29 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 12.

Figure 30 is the figure of the transition state of the Vt level distribution when being illustrated in overwriting data in the embodiments of the present invention 12.

Figure 31 is the process flow diagram of the initialization order of expression embodiment 12.

Figure 32 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 13.

Figure 33 is the process flow diagram of the initialization order of expression embodiment 13.

Figure 34 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 14.

Figure 35 is illustrated in usually to write to write the transition of fashionable Vt distribution under (the long-term assurance) pattern and writing the figure that writes the transition of fashionable Vt distribution under (short-term assurance) pattern at a high speed.

Figure 36 is the dependent figure of total write time of expression memory cell threshold voltage.

Figure 37 is illustrated in the figure that writes pattern usually and write the transition state of the Vt level distribution under the pattern at a high speed.

Figure 38 is the process flow diagram of the long-term assurance write sequence of expression embodiment 14.

Figure 39 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 15.

Figure 40 is the process flow diagram of the long-term assurance write sequence of expression embodiment 15.

Figure 41 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 16.

Figure 42 is the process flow diagram of wiping order of expression embodiment 16.

Figure 43 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 17.

Figure 44 is the process flow diagram of the initialization order of expression embodiment 17.

Figure 45 is the process flow diagram of the initialization order of expression embodiment 18.

Figure 46 is the process flow diagram of the initialization order of expression embodiment 19.

Figure 47 is the process flow diagram of the initialization order of expression embodiment 20.

Figure 48 is the block diagram of structure of the non-volatile memory semiconductor device of expression embodiments of the present invention 21.

Figure 49 is the process flow diagram of the write sequence of expression embodiments of the present invention 21.

Embodiment

Below, with reference to the description of drawings embodiments of the present invention.In the explanation of following each embodiment,, omit its explanation for being marked with identical Reference numeral with the inscape that once inscape has an identical function is described.

" embodiment 1 "

(structure of non-volatile memory semiconductor device 100)

Fig. 1 is the block diagram of structure of the non-volatile memory semiconductor device 100 of expression embodiments of the present invention 1.As shown in Figure 1, non-volatile memory semiconductor device 100 comprises: memory cell transistor array 1, line decoder 2, sensor amplifier 3, output data latch 4, output data commutation circuit 5, input data latch 6, checking circuit 7, write data latches 8, write circuit 9, control circuit 12, sector location decision level memory circuit 13, decision level control circuit 14 and voltage control circuit 15.Non-volatile memory semiconductor device 100 is according to carrying out the write activity of data and read action from the instruction (control signal) of outside input.

A plurality of memory cell configurations of memory cell transistor array 1 become array-like.Each memory cell is made of according to the transistor that the quantity of electric charge that is stored in single charge storage position changes threshold voltage levels (Vt level).This memory cell stores has the data corresponding to threshold voltage.This memory cell (transistor) has the distribution of the Vt level more than 3 at single charge storage position.Fig. 2 is the transition state of the Vt level distribution of expression when storing data.In Fig. 2, transverse axis is represented the Vt level.In the present embodiment, use the 1st two the continuous distributions that distribute in～the 3 Vt level that distributes to store data.Particularly, make two high position distribution sides in continuous Vt distribution distribute data " 0 " all the time, low-profile side distribute data " 1 ".That is the function of each memory cell performance 2 value storer.For example, in the transition state (1) of Fig. 2, the 1st distribution and the 2nd distributes and is used to store data, and the 3rd distribution and the 4th distributes and is not used to store data.Distribute and the 2nd distribute and be used to store under the data conditions the 1st, relatively being detected data as the output potential quilt of the memory cell of reading object of data with Readl decision level (with reference to Fig. 2) is " 0 " or " 1 ".

Line decoder 2 is selected column of memory cells arbitrarily.

Sensor amplifier 3 compares the output potential of selected memory cell and the current potential (reading decision level) that becomes the judgment standard of data, and detecting data is " 0 " or " 1 ".

Output data latch 4, the output data of latch sense 3.

Output data commutation circuit 5 is optionally switched the output of output data latch 4 is exported to leading to outside output Dout, still it is fed back to checking circuit 7.

Input data latch 6 latchs the input data Din from the outside.

Checking circuit 7, relatively from the data of input data latch 6 outputs and the data of exporting from output data commutation circuit 5, whether the output expression exists the compare result signal of difference.And checking circuit 7 compares any of data " 1 " and data " 0 " and the data that output data commutation circuit 5 is exported, and whether the output expression exists the compare result signal of difference.At this, will judge based on more all be called " 1 " of data " 1 ", will judge based on more all be called " 0 " of data " 0 ".

Write data latches 8, latch the data of being imported that write.

Write circuit 9 according to the output data content that writes data latches 8, writes in any position of memory cell transistor array 1.

Control circuit 12 comprises programmed order control circuit 10 and power-up sequence control circuit 11, control example as when reading, specify the decision level information of the reading actions that writes, reads in nonvolatile semiconductor memory member 100 such as (aftermentioneds) of each sector location.

Programmed order control circuit 10 is controlled at the write activity in the nonvolatile semiconductor memory member 100.

Power-up sequence control circuit 11 is read decision level when specifying energized.

Sector location decision level memory circuit 13 is stored in the specified decision level information of reading of power-up sequence control circuit 11.

Decision level control circuit 14, the output information of reception sector location decision level memory circuit 13 will be read decision level and will be set in the voltage control circuit 15.

Voltage control circuit 15 according to the output of decision level control circuit 14, is controlled the voltage of the column of memory cells of any sector in the memory cell transistor array 1.

(action of non-volatile memory semiconductor device 100)

In above-mentioned non-volatile memory semiconductor device 100, carry out the processing shown in the process flow diagram of Fig. 3, data in the sector that rewrites object, that be stored on the memory cell are rewritten.Step S100 shown in Figure 3～S103 is called the pre-programmed part, step S104～S107 is called the data programing part.

At first, illustrate at the pre-programmed part (circuit operation among the S100～S103).

(step S100)

Shown in the transition state (1) of Fig. 2, the state before beginning to rewrite, in memory cell transistor array 1, the 1st is distributed as data " 1 ", and the 2nd is distributed as data " 0 ".Under this state, the information of sector location decision level memory circuit 13 storage representation Read1 decision level.

(step S101)

At first, make memory cell temporarily become the 2nd distribution as the rewriting object.

At this moment, judge that the decision level that writes of write state is set to PPV level (aftermentioned), therefore send the signal (output information) of expression programmed check from 10 pairs of decision level control circuits 14 of programmed order control circuit.Decision level control circuit 14 with the output voltage of voltage control circuit 15 be controlled to than sector location decision level memory circuit 13 stored read the high slightly level of decision level (Read1 decision level), be the PPV level.Thus, the output voltage of voltage control circuit 15 rises to the PPV level from the Read1 decision level.The output voltage of voltage control circuit 15 is applied to the conduct of memory cell transistor array 1 by line decoder 2 and rewrites the word line that the memory cell of object is connected.

Then, activation signal is delivered to sensor amplifier 3 and output data latch 4 from control circuit 12.Thus, sensor amplifier 3 is activated, and the data of the memory cell that word line is activated are read out.And in the moment of the output data of having determined

sensor amplifier

3,4 pairs of data of output data latch latch.4 latched data of output data latch are sent to checking circuit 7 by output data commutation circuit 5.

Then, according to the order from control circuit 12, the data setting that will be compared by checking circuit 7 is to be used for the data that complete " 0 " is judged.Thus, in checking circuit 7, the output data of the output data latch 4 that is fed back to data " 0 " with from output data commutation circuit 5 compares, the output compare result signal.When comparative result was consistent, the TRUE signal was delivered to programmed order control circuit 10 from checking circuit 7.

(step S102)

In this step, programmed order control circuit 10 receives the compare result signal of self-checking circuit 7 to determine following action.That is, when the compare result signal that comes self-checking circuit 7 was the TRUE signal, (processing of step S104～S107) when compare result signal during for the inconsistent FALSE signal of expression, was carried out the processing of step S103 to forward data programing portion to.

(step S103)

In this step, the memory cell that stores data " 1 " is write data " 0 " (with reference to the transition state (2) of Fig. 2).That is, data " 0 " are sent to and write data latches 8 and be latched, and the data setting that is latched is in write circuit 9.Thus, 9 pairs of selected memory cells of write circuit are implemented writing of certain hour.When writing of data finished, forward the processing of step S101 to.So, to the processing of all the data implementation step S101～S103 in the sector, make all memory cells in the sector temporarily move to high-order threshold voltage distribution states (with reference to the transition state (3) of Fig. 2) from the threshold power distribution of low level.As mentioned above, in the following description, will make writing that threshold level moves be called pre-programmed.

Then, illustrate at the data programing part (circuit operation of step S104～S107).

(step S104)

Processing in the pre-programmed part finishes, handles when forwarding the data programing part to, becomes the 2nd state that distributes as the memory cell in the sector that rewrites object.

At this constantly, reading decision level is the Read1 decision level, so the 2nd state representation data " 0 " that distribute.In this step, at first the implication of the 2nd state that distributes is changed into data " 1 ".Particularly, be used for, the decision level information of reading that sector location decision level memory circuit 13 is stored is changed into the information of representing the Read2 decision level from the signal of controlling circuit 12.

Then, send the signal of expression programmed check to decision level control circuit 14 from programmed order control circuit 10.There is the limit in decision level control circuit 14 for the 2nd distribution level, high slightly level, the PV decision level of decision level (Read2 decision level) when therefore being arranged to the output voltage of voltage control circuit 15 than sense data.Thus, the output voltage of voltage control circuit 15 rises to the PV level from the Read2 decision level.The PV decision level is the voltage level that is used to judge write state when programmed check.The output voltage of voltage control circuit 15 is applied to the conduct of memory cell transistor array 1 by line decoder 2 and rewrites the word line that the memory cell of object is connected.

Then, activation signal is sent to sensor amplifier 3 and output data latch 4 from control circuit 12.Thus, sensor amplifier 3 is activated, and the data of the memory cell that word line is activated are read out.And in the moment of the output data of having determined

sensor amplifier

Checking circuit 7 is according to the order from control circuit 12, and the output data of the output data latch 4 that is fed back to the input data Din that latched by input data latch 6 with from output data commutation circuit 5 compares.When comparative result was consistent, the TRUE signal was sent to programmed order control circuit 10 from checking circuit 7.

(step S105)

In this step, programmed order control circuit 10 receives the compare result signal of self-checking circuit 7 to determine following action.That is, when the compare result signal that comes self-checking circuit 7 is the TRUE signal, forward step S107 end process to.In addition, when compare result signal during, move to the processing of step S106 for the inconsistent FALSE signal of expression.

(step S106)

In this step, the inconsistent memory cell of comparative result in the expression checking circuit 7 is write data " 0 ".That is, data " 0 " are sent to and write data latches 8 and be latched, and the data that are latched are set in the write circuit 9.Thus, 9 pairs of selected memory cells of write circuit are implemented write (with reference to the transition state (4) of Fig. 2) of certain hour.

When writing of 1 data finished, move to the processing of step S104, implement above-mentioned a series of actions (step S104～S106) finish repeatedly up to all writing of input data Din.

As mentioned above, in the present embodiment, use the memory cell that the distribution of the Vt level more than 3 is arranged at single charge storage locations.To continuous two Vt level distribution distribute data " 0 " and data " 1 ".And, when overwriting data, the 1st distribution or the 2nd distribution are temporarily become (that is, the Vt level distribution that will be used to store moves the back to a direction) after the 2nd distribution, overwriting data (with reference to the transition state (5) of Fig. 2).Therefore, according to present embodiment, when overwriting data, the erasing move that need be carried out in nonvolatile semiconductor memory member has not in the past shortened the rewriting time significantly.

" embodiment 2 "

The non-volatile memory semiconductor device 100 of embodiment 1 also can be controlled as the process flow diagram of Fig. 4.Its write sequence is characterised in that, directly moves to the 2nd distribution or the 3rd distribution (making Vt distribution transition) according to the information that will write from the 1st distribution or the 2nd distribution.

Below, the processing of each step in the process flow diagram of key diagram 4.Step S200～S203 is called the data programing part, step S204～S207 is called " 0 " data programing part.

At first, illustrate in (the action of S200～S203) of data programing part.

(step S200)

Shown in the transition state (1) of Fig. 5, the state before beginning to rewrite, in memory cell transistor array 1, the 1st is distributed as data " 1 ", and the 2nd is distributed as data " 0 ".

(step S201)

In this step, at first, change the 2nd distribution into expression data " 1 ".Particularly, be used for, the decision level information of reading that sector location decision level memory circuit 13 is stored is changed into the information of representing the Read2 decision level from the signal of controlling circuit 12.

Then, send the signal of expression programmed check to decision level control circuit 14 from programmed order control circuit 10.There is the limit in decision level control circuit 14 relative the 2nd distribution level, high slightly level, the PV decision level of decision level (Read2 decision level) when therefore being arranged to the output voltage of voltage control circuit 15 than sense data.Thus, the output voltage of voltage control circuit 15 rises to the PV level from the Read2 decision level.The PV decision level is the voltage level that is used to judge distribution when programmed check.The output voltage of voltage control circuit 15 is applied to the conduct of memory cell transistor array 1 by line decoder 2 and rewrites the word line that the memory cell of object is connected.

sensor amplifier

Then, checking circuit 7 is according to the order from control circuit 12, and the output data of the output data latch 4 that is fed back to the input data Din that latched by input data latch 6 with from output data commutation circuit 5 compares.When comparative result was consistent, the TRUE signal was sent to programmed order control circuit 10 from checking circuit 7.

(step S202)

In this step, programmed order control circuit 10 receives the compare result signal of self-checking circuit 7 and determines following action.That is, when the compare result signal that comes self-checking circuit 7 is the TRUE signal, forward the processing of step S204 to.When compare result signal during, move to the processing of step S203 for the inconsistent FALSE signal of expression.

(step S203)

In this step, the inconsistent memory cell of comparative result in the expression checking circuit 7 is write data " 0 ".That is, data " 0 " are sent to and write data latches 8 and be latched, and the data setting that is latched is in write circuit 9.Thus, 9 pairs of selected memory cells of write circuit are implemented write (with reference to the transition state (2) of Fig. 5) of certain hour.The decision level of reading of this moment is the PV level.

Writing when finishing of data handles moving to step S201.So, to the processing of all the data implementation step S201～S203 in the sector.

(step S204)

In this step, make the memory unit of the 1st distribution become the 2nd distribution.

At this moment, read decision level and be set to the PV2 level, so send the signal (output information) of expression programmed check from 10 pairs of decision level control circuits 14 of programmed order control circuit.Decision level control circuit 14 with the output voltage of voltage control circuit 15 be controlled to than sector location decision level memory circuit 13 stored read the high slightly level of decision level (Read1 decision level), be the PV2 level.Thus, the output voltage of voltage control circuit 15 rises to PV2 level (with reference to the transition state (3) of Fig. 5) from the Read1 decision level.The output voltage of voltage control circuit 15 is applied to the conduct of memory cell transistor array 1 by line decoder 2 and rewrites the word line that the memory cell of object is connected.

sensor amplifier

Then, according to order, will judge the data of usefulness for complete " 0 " by the data setting that checking circuit 7 compares from control circuit 12.Thus, in checking circuit 7, the output data of the output data latch 4 that is fed back to data " 0 " with from output data commutation circuit 5 compares, the output compare result signal.When comparative result was consistent, the TRUE signal was sent to programmed order control circuit 10 from checking circuit 7.

(step S205)

In this step, programmed order control circuit 10 receives the compare result signal of self-checking circuit 7 and determines following action.That is, when the compare result signal that comes self-checking circuit 7 is the TRUE signal, forward step S207 tenth skill to.When compare result signal during, move to the processing of step S206 for the inconsistent FALSE signal of expression.

(step S206)

In this step, the inconsistent memory cell of the comparative result that is illustrated in checking circuit 7 is write data " 0 ".That is, data " 0 " are sent to and write data latches 8 and be latched, and the data setting that is latched is to write circuit 9.Thus, 9 pairs of selected memory cells of write circuit are implemented writing of certain hour.

When writing of 1 data finished, move to the processing of step S204, implement above-mentioned a series of actions (step S204～S206) finish repeatedly up to all writing of input data Din.

As mentioned above, in the present embodiment, by using the 2nd distribution and the 3rd state that distributes to carry out the rewriting of canned data from using the 1st distribution and the 2nd state that distributes directly to move on to according to writing information.Therefore, according to present embodiment, when overwriting data, the erasing move that need be carried out in nonvolatile semiconductor memory member has not in the past shortened the rewriting time significantly.

" embodiment 3 "

The non-volatile memory semiconductor device 100 of embodiment 1 also can be controlled as the process flow diagram of Fig. 6.Its write sequence is characterised in that, distributes up to n+1 Vt from the employed distribution of state expansion transition that the Vt that uses below n distributes according to the information that writes.

Below, the processing of each step in the process flow diagram of key diagram 6.

(step S300)

Under the state before beginning to rewrite, the 1st distributes and the 2nd distribution is used for canned data.Shown in the transition state (1) of Fig. 7, in this case, in memory cell transistor array 1, the 1st is distributed as data " 1 ", and the 2nd is distributed as data " 0 ".

(step S301)

In this step, at first, change the implication of the 2nd distribution into data " 1 ".Particularly, be used for, the decision level information of reading that sector location decision level memory circuit 13 is stored is changed into the information of representing the Read2 decision level from the signal of controlling circuit 12.

Then, send the signal of expression programmed check to decision level control circuit 14 from programmed order control circuit 10.There is the limit in decision level control circuit 14 relative the 2nd distribution level, high slightly level, the PV decision level of decision level (Read2 decision level) when therefore being arranged to the output voltage of voltage control circuit 15 than sense data.Thus, the output voltage of voltage control circuit 15 rises to the PV level from the Read2 decision level.The output voltage of voltage control circuit 15 is applied to the conduct of memory cell transistor array 1 by line decoder 2 and rewrites the word line that the memory cell of object is connected.

sensor amplifier

(step S302)

In this step, programmed order control circuit 10 receives the compare result signal of self-checking circuit 7 to determine next action.That is, when the compare result signal that comes self-checking circuit 7 is the TRUE signal, forward step S304 end process to.When compare result signal during, move to the processing of step S303 for the inconsistent FALSE signal of expression.

(step 303)

In this step, the inconsistent memory cell of the comparative result that is illustrated in checking circuit 7 is write data " 0 ".That is, data " 0 " are sent to and write data latches 8 and be latched, and the data setting that is latched is in write circuit 9.Thus, 9 pairs of selected memory cells of write circuit are implemented write (with reference to the transition state (2) of Fig. 7) of certain hour.The decision level of reading of this moment is the PV level.

Writing when finishing of data handles moving to step S301.So, to the processing of all the data implementation step S301～S303 in the sector.

As mentioned above, in the present embodiment, according to writing information, from using the Vt distributed expansion below n individual to n+1.Therefore, in the present embodiment, remain when overwriting data, the erasing move that need be carried out in nonvolatile semiconductor memory member has not in the past shortened the rewriting time significantly.

" embodiment 4 "

In the non-volatile memory semiconductor device of above-mentioned embodiment 1～3, only otherwise judge that the Vt that is used for information stores distributes, just can't determine to read decision level, can not carry out correct reading.For this reason, in non-volatile memory semiconductor device 100, after energized, need distribute to carry out initialization according to memory cell transistor array 1 employed Vt to reading decision level.

The non-volatile memory semiconductor device 400 of embodiments of the present invention 4, with employed memory cell transistor array 1 difference of user non-volatile memory is set, above-mentioned non-volatile memory (below, being called and using the distributing position storage area) storage representation is in the information (using distributing position information) of memory cell transistor array 1 employed threshold voltage distribution position in advance, after energized, read the use distributing position from above-mentioned use distributing position storage area, set the decision level of reading in storage of subscriber data zone at once.

Fig. 8 is the block diagram of the structure of expression non-volatile memory semiconductor device 400.As shown in Figure 8, non-volatile memory semiconductor device 400 has increased the use distributing position storage area 16 corresponding with each sector with respect to non-volatile memory semiconductor device 100.

Use distributing position storage area 16, have memory cell with the memory cell identical type that constitutes memory cell transistor array 1.Use distributing position storage area 16 to be stored in the position that the employed Vt of memory cell in the corresponding sector distributes.Two Vt distributions that the Vt that uses in order to use distributing position storage area 16 canned datas distributes and determined regularly.

In above-mentioned non-volatile memory semiconductor device 400, carry out the processing shown in the process flow diagram of Fig. 9, set and read decision level.

(step S400)

Connect the power supply of non-volatile memory semiconductor device 400.

(step S401)

11 pairs in power-up sequence circuit is stored in the decision level information of reading of sector location decision level memory circuit 13 and carries out initialization, makes it can detect the data of being stored in using distributing position storage area 16.

(step S402)

Then, carry out reading of the use distributing position information of in using distributing position storage area 16, being stored with sensor amplifier 3.The use distributing position information of output data latch 4 latch sense 3 outputs.

(step S403)

Power-up sequence circuit 11, the decision level information of reading that will be corresponding with the use distributing position information that is latched by output data latch 4 is transferred to sector location decision level memory circuit 13 by output data commutation circuit 5.The decision level information of reading that the 13 storage transmission of sector location decision level memory circuit come.

(step S404)

Then, the output voltage of decision level control circuit 14 control voltage control circuits 15 be sector location decision level memory circuit 13 stored read decision level.

(step S405)

At last, reading the decision level setting when arriving step S405 finishes.

As mentioned above, according to present embodiment, after energized, can suitably set the decision level of reading to memory cell transistor array 1.Therefore, move, also can correctly read even if the Vt that uses in information stores is distributed.

" embodiment 5 "

Explanation is about reading initialized other embodiments of decision level.

Figure 10 is the block diagram of the structure of expression non-volatile memory semiconductor device 500.As shown in figure 10, non-volatile memory semiconductor device 500 has increased monitoring position 17 corresponding to each sector with respect to non-volatile memory semiconductor device 100.

Monitoring position 17 has the memory cell with the memory cell identical type that constitutes memory cell transistor array 1.Use and the identical Vt distribution of memory cell in corresponding sector monitoring position 17, stores data " 0 " all the time.Figure 11 is illustrated in the memory cell transistor array 1 figure that concerns between the writing position of storing threshold voltage distribution position that 2 Value Datas use and monitoring position.The 2nd distributes when using as data " 0 " and the 3rd distribute when using as data " 0 ", and the writing position of monitoring position 17 is represented with stain respectively.

Non-volatile memory semiconductor device 500 is characterised in that, uses monitoring position 17 after energized at once, specifies the threshold voltage distribution position that is used to store data " 0 ", sets the decision level of reading in storage of subscriber data zone.Particularly, in non-volatile memory semiconductor device 500, carry out the processing shown in the process flow diagram of Figure 12, set and read decision level.

(step S500)

Connect the power supply of non-volatile memory semiconductor device 500.

(step S501)

Make this read decision level in order to judge the reading decision level of monitoring position 17 and gradually change from maximum level, power-up sequence control circuit 11 is sent signal to decision level control circuit 14, makes the decision level of reading of monitoring position 17 become maximum level.Decision level control circuit 14 is read decision level (with reference to the Read3 decision level among Figure 11) with what the output voltage of voltage control circuit 15 was controlled to be maximum level.

(step S502)

Then, monitor reading of position 17 with sensor amplifier 3.The use distributing position information that output data latch 4 latch sense 3 are exported.The output data that output data latch 4 is latched is sent to checking circuit 7 by output data commutation circuit 5.

Power-up sequence control circuit 11 is set at data " 0 " with the comparison other data in advance in the checking circuit 7.

The output data of checking circuit 7 comparing datas " 0 " and output data latch 4 outputs to power-up sequence control circuit 11 with comparative result.

(step S503)

At the comparative result based on checking circuit 7 is the output data of data " 0 " and output data latch 4 when consistent, moves to the processing of step S505.In addition, as result when being inconsistent, move to the processing of step S504.

(step S504)

Power-up sequence control circuit 11 will be read decision level and be set at a lower level (for example, among Figure 11 from the Read3 decision level to the Read2 decision level).Then, move to the processing of step S502.

(step S505)

Read decision level in this step setting.

Power-up sequence control circuit 11 control decision level control circuits 14, make and present read decision level corresponding read the decision level information stores in sector location decision level memory circuit 13.Thus, reading the decision level setting finishes.

As mentioned above, according to present embodiment, also can after energized, suitably set the decision level of reading to memory cell transistor array 1.Therefore, move, also can correctly read even if the Vt that uses in information stores is distributed.

" embodiment 6 "

Figure 13 is the block diagram of structure of the non-volatile memory semiconductor device 600 of expression embodiments of the present invention 6.As shown in figure 13, non-volatile memory semiconductor device 600 replaces the programmed order control circuit 10 in the non-volatile memory semiconductor device 100 and is provided with programmed order control circuit 30, has also increased input data commutation circuit 20 and data reversal commutation circuit 21.

Whether input data commutation circuit 20 is exported the data and the some data in the data " 0 " of input data latch 6 according to the control switching of programmed order control circuit 30 to checking circuit 7.

Data reversal commutation circuit 21 according to the control of programmed order control circuit 30, outputs to output data latch 4 after directly reversing with the output data of sensor amplifier 3 or with the output data of sensor amplifier 3.

Programmed order control circuit 30, the write activity in the control non-volatile memory semiconductor device 600.

In non-volatile memory semiconductor device 600, to the 1st～the 4 distribute these 4 threshold voltage distribution alternately distribute data " 0 " and the data " 1 " that distribute.For example, at the transition state (1) of Figure 14, the 1st distribution table registration is according to " 1 ", and the 2nd distribution table registration is according to " 2 ".

Reading under the transition state (1), the information of setting expression Read1 decision level in sector location decision level memory circuit 13 is as reading decision level information.Data reversal commutation circuit 21 according to programmed order control circuit 30, is set at the pattern of the output data of direct output sensor amplifier 3.Thus, be read out as data " 1 " by the data of sensor amplifier 3, the 1 distributions, the data of the 2nd distribution are read out as data " 0 ".The output data of being read by sensor amplifier 3 is latched by data latches 4 by data reversal commutation circuit 21.By output data latch 4 latched data by output data commutation circuit 5 be output to output Dout thereafter.

Writing of data is to implement by the processing shown in the process flow diagram of Figure 15.As shown in figure 15, write activity was made of pre-programmed and this 2 stage of data programing of making random data temporarily become certain state.The following describes the action of each step.

(step S601)

Shown in the transition state (2) of Figure 14, programmed order control circuit 30 will write level of test (particularly being the control voltage of voltage control circuit 15) by decision level control circuit 14 and be set at the PV1 decision level when pre-programmed.The PV1 decision level is the voltage level that is used for judging distribution when programmed check.Programmed order control circuit 30 also makes data latches 8 latch datas " 0 ".

On the other hand, input data commutation circuit 20 is input to checking circuit 7 with data " 0 ".Checking circuit 7, the output data of comparing data " 0 " and output data commutation circuit 5, whether the output data of check output data commutation circuit 5 is data " 1 ".

(step S602)

When the compare result signal that comes self-checking circuit 7 is the FALSE signal, move to the processing of step S603.In addition, when compare result signal is the TRUE signal, move to the processing of step S604.

(step S603)

Write circuit 9 writes data " 0 " (pre-programmed).

As mentioned above, by carrying out the action of step S601～S603 repeatedly, all memory cells in the sector all become the 2nd distribution.

After data temporarily were set as the 2nd distribution, the data of carrying out step S604～S606 write (data programing).

(step S604)

Shown in the transition state (3) of Figure 14, programmed order control circuit 30 is set at PV2 with the control voltage of voltage control circuit 15 when pre-programmed.Programmed order control circuit 30 is set at data reversal commutation circuit 21 pattern that will export behind the data reversal.Thus, the 2nd distribution table registration is according to " 0 ", and the 3rd distribution table registration is according to " 1 ".

Input data commutation circuit 20 is switched according to programmed order control circuit 30, outputs to checking circuit 7 with the output data with input data latch 6.Thus, checking circuit 7 carries out the check of the output data of the output data of input data latch 6 and output data commutation circuit 5.

(step S605)

When the compare result signal that comes self-checking circuit 7 is the FALSE signal, move to the processing of step S606.In addition, when compare result signal is the TRUE signal, end process.

(step S606)

The memory cell that writes the data " 1 " that gone out by the check motion detection carries out write activity by write circuit 9 after being written into data latches 8 latch datas " 1 ".

When reading the data that are written into as described above, level information changes over expression Read2 decision level from the information of expression Read1 decision level the information of reading of sector location decision level memory circuit 13 will be stored in.Data reversal commutation circuit 21 according to programmed order control circuit 30, is set to the pattern that will export behind the data reversal.

Write fashionablely in next time, make the 3rd distribution corresponding data " 1 ", the 4th distribution corresponding data " 0 " store data.In this case, data reversal commutation circuit 21 is set to the pattern of direct output sensor amplifier 3 data according to programmed order control circuit 30.Read decision level and be set at Read3 decision level (with reference to Figure 11).

As mentioned above,,, do not pay particular attention to that data " 0 " etc. and which Vt are distributed is corresponding, just can read action and check and move as the non-volatile memory semiconductor device 400 of enforcement mode 4 according to present embodiment.Therefore, do not need to use distributing position storage area 16 and monitoring position 17, carry out the control of write activity easily, and the non-volatile memory semiconductor device area is diminished.

" embodiment 7 "

Figure 16 is the block diagram of structure of the non-volatile memory semiconductor device 700 of expression embodiments of the present invention 7.As shown in figure 16, non-volatile memory semiconductor device 700 increases power-up sequence control circuit 31 and constitutes in non-volatile memory semiconductor device 600.

When determining energized, power-up sequence control circuit 31 reads decision level.Particularly, the control carried out shown in the process flow diagram of Figure 17 of power-up sequence control circuit 31.Below, the action of each step is described.

(step S701)

When detecting energized, power-up sequence control circuit 31 control decision level control circuits 14 will be read decision level and be set at the Read2 decision level.Power-up sequence control circuit 31 is set at positive revolving die formula with data reversal commutation circuit 21.

(step S702)

Then, power-up sequence control circuit 31 makes its action of testing by control test circuit 7, attempt thus can be from memory cell transistor array 1 sense data " 1 ".

(step S703)

The result's that tests PASS/FALL judges, when can not be from memory cell transistor array 1 during sense data " 1 ", moves to the processing of step S704.When energy sense data " 1 ", move to the processing of step S705.

(step S704)

With read decision level be reset to improved 1 grade read decision level (for example,, then being set at the Read3 decision level) if the present decision level of reading is the Read2 decision level.Then, move to the processing of step S702.

(step S705)

About reading decision level, with expression reduced by 1 grade (for example read decision level, if the present decision level of reading is the Read2 decision level, then be set at the Read1 decision level) read the decision level information transmission and store sector location decision level memory circuit 13 into.

According to above-mentioned non-volatile memory semiconductor device 700, automatic setting is read decision level after energized, therefore the time that does not need to select to read level.Therefore improved user convenience.

" embodiment 8 "

To realizing that further the example of the high speed of write activity describes by non-volatile memory semiconductor device 600 grades.

Figure 18 is the block diagram of structure of the non-volatile memory semiconductor device 800 of expression embodiments of the present invention 8.Non-volatile memory semiconductor device 800 has omitted the sector location decision level memory circuit 13 of the non-volatile memory semiconductor device 600 of embodiment 6, and replaces output data latch 4 and be provided with data latches 23.

Data latches 23 only latchs according to read the selected data of decision level from the data of data reversal commutation circuit 21 output, when temporarily latching, preserve data when checking next time till.

In non-volatile memory semiconductor device 800, to the 1st～the 4 distribute these 4 threshold voltage distribution alternately distribute data " 0 " and the data " 1 " that distribute.For example, at the transition state (1) of Figure 19, the 1st distribution table registration is according to " 1 ", and the 2nd distribution table registration is according to " 2 ".

Reading under the transition state (1), with these a plurality of level of Read1 decision level, Read2 decision level, Read3 decision level, Read4 decision level as reading decision level, by amplifier 3 from more than 1 sense data of memory cell transistor array.The data of being read are output data latches 23 and latch, and the 1st data that distribute are output as data " 1 ", and the 2nd data that distribute are output as data " 0 ".

In non-volatile memory semiconductor device 800, carry out writing of data by programmed order control circuit 32 controls flow process shown in Figure 20.

At first, write activity will write level of test earlier and be set at PV1, PV2, PV3 or PV4 as shown in figure 19.As the expected value data, the data of input data latch 6 are imported into checking circuit 7 by input data commutation circuit 20.

(step S801)

By programmed order control circuit 32 control test circuit 7, the action of testing of a plurality of level of test of checking circuit 7 usefulness is carried out changing to the memory cell of data " 0 " and changing to the check of the memory cell of data " 1 " from the 2nd distribution (data " 0 ") from the 1st distribution (data " 1 ").

(step S802)

When the compare result signal that comes self-checking circuit 7 is the FALSE signal, move to the processing of step S803.In addition, when compare result signal is the TRUE signal, end process.

(step S803)

In this step, the data that write to the memory cell that data change are written into data latches 8 and latch, and are write by write circuit 9.

By carrying out the processing of above-mentioned step S801～S803, the data " 1 " of the 1st threshold distribution that data change are programmed to the data " 0 " of the 2nd threshold distribution, and the data of the 2nd threshold distribution " 0 " are programmed to the data " 1 " of the 3rd threshold distribution.

According to present embodiment as described above,, therefore write figure place and reduced owing to do not need to carry out writing of unconverted memory cell.Therefore, can further realize the high speed of write activity by non-volatile memory semiconductor device 600 grades.

" embodiment 9 "

Figure 21 is the block diagram of structure of the non-volatile memory semiconductor device 900 of expression embodiments of the present invention 9.As shown in figure 21, non-volatile memory semiconductor device 900 has increased data compression sequencing circuit 33 with respect to non-volatile memory semiconductor device 800, and replaces sector location decision level memory circuit 13 and be provided with the decision level/distribution compact token memory circuit 22 of sector-specific.This non-volatile memory semiconductor device 900 has to use a plurality ofly to be read pattern (many level readout mode) that decision level reads, reads the pattern (1 level readout mode) that decision level is read with 1.For preserving backstage execution mark from the compression executing state (aftermentioned) that external detection goes out under backstage (background), the value of the backstage being carried out mark outputs to not shown microcomputer (be designated as BG among Figure 21 and carry out mark).

The decision level of sector-specific/distribution compact token memory circuit 22 is preserved distribution compact token (aftermentioned).The decision level of sector-specific/distribution compact token memory circuit 22 is also preserved the decision level information of reading.

In the present embodiment, output data latch 23 has following two kinds of patterns: reading under the situation that decision level reads with a plurality of, output data latch 23 only latchs according to read the data that level is selected from the data of being exported by data reversal commutation circuit 21, in case latch the pattern of just preserving till latching when checking next time; Under the situation of reading, preserve data from data reversal commutation circuit 21 pattern till when checking next time by a level.

Data compression sequencing circuit 33 reduces (compression) employed threshold voltage distribution number, makes from using the state of the threshold voltage distribution more than 3 to the state with 2 threshold voltage canned datas for the storage data.The above-mentioned compression of being undertaken by data compression sequencing circuit 33 after data rewrite finishes, is implemented when the state of executable operations (being the backstage) not.Being stored in the distribution compact token of the decision level/distribution compact token memory circuit 22 of sector-specific, is the mark of representing whether to have carried out the compression of threshold voltage distribution number.When the distribution compact token was data " 0 ", the expression compression was finished, and during for data " 1 ", the expression compression is not finished.For convenience of explanation, for the value of each mark, also data " 1 " are called " L " (low level), and data " 0 " are called " H " (high level).

Below, use Figure 22,23 to describe the action of non-volatile memory semiconductor device 900 in detail.

Figure 22 is the figure that is illustrated in the non-volatile memory semiconductor device 900 the transition state of the threshold voltage distribution when carrying out compressed action on the backstage.Figure 23 is the figure of flow process of compressed action that is illustrated in the threshold voltage distribution number on backstage.Processing in each step is controlled by data compression sequencing circuit 33.

In the transition state (1) of Figure 22, the 1st distributes is used to store data " 1 ", and the 2nd distributes is used to store data " 0 ", and the 3rd distributes is used to store data " 1 ", and the 4th distributes is used to store data " 0 ".

Read when action, by sensor amplifier 3 usefulness Read1 decision level, Read2 decision level, Read3 decision level, these a plurality of decision level of reading of Read4 decision level from memory cell transistor array 1 sense data.The data of being read latch with output data latch 23, the 1st data that distribute are exported as data " 1 ", the 2nd data that distribute are as data " 0 " output, and the data of the 3rd threshold voltage distribution are as data " 1 " output, and the data of the 4th threshold voltage distribution are exported as data " 0 ".

In the data compression write activity on backstage, the data " 0 " that will be positioned at data " 1 " that the 1st of low level distributes, the 2nd threshold voltage distribution are programmed for and are positioned at the 3rd high-order data " 1 " that distribute, the 4th data " 0 " (with reference to the transition state (2) of Figure 22) that distribute.

As shown in figure 23, check current write state, therefore read action, by output data latch 23, output

data commutation circuit

5 and 20 pairs of checking circuits of input data commutation circuit, 7 input expected value data with many level by step S901, S902.Thereafter, write level of test at step S903 and be set to the PV2 level, the action of testing is checked to be positioned at the 1st data " 1 " that distribute.Being written into data latches 8 by the data " 1 " of checking motion detection to go out latchs.

Then, at step S905,, carry out the programming of data " 1 " by write circuit 9 according to being written into 8 latched data of data latches.In step S904, carry out step S903 repeatedly, till programmed check is qualified.

Data " 1 " write qualified after, level of test is set to the PV3 level.Thereafter, by step S906, S907, and S908 data " 0 " are write similarly.

After writing end, the distribution compact token of the decision level/distribution compact token memory circuit 22 of sector-specific is set at data " 0 " (" H ") by step S909.Thus, output data latch 23 is set at 1 level readout mode.Read decision level and be set to the Read3 decision level, only read (with reference to the transition state (3) of Figure 22) with 1 level.

As mentioned above, in non-volatile memory semiconductor device 900, on the backstage threshold voltage distribution number that uses is compressed, make from using the state of the threshold voltage distribution more than 3 to having stored the state of information with 2 threshold voltage distribution for the storage data.Therefore, owing to the read-around number that can reduce when reading, so a kind of non-volatile memory semiconductor device that makes the writing speed variation, eliminated the loss when reading that do not have can be provided.

" embodiment 10 "

Figure 24 is the block diagram of structure of the non-volatile memory semiconductor device 1000 of expression embodiments of the present invention 10.As shown in figure 24, non-volatile memory semiconductor device 1000 has increased power-up sequence control circuit 34 with respect to non-volatile memory semiconductor device 900.

Power-up sequence control circuit 34 is judged the setting of readout mode and whether the compression of the distribution number that uses is finished when having connected power supply.Particularly, the control carried out shown in the process flow diagram of Figure 25 of power-up sequence control circuit 34.

After having connected power supply, power-up sequence control circuit 34 will be read decision level at step S1001 and be set at the Read2 level.At step S1002 carry out the action of reading of data " 1 " thereafter.

At step S1003, be judged as when defective when reading action, by step S1004 decision level is moved to the Read3 level, carry out step S1002 repeatedly, till qualified.

After step S1003 is qualified, changes to and reduced by 2 grades the decision level of reading from the present decision level of reading by step S1005.

At step S1006, carry out the action of reading of data " 0 ", be judged as at step S1007 and read action when qualified, judge into the compression of employed distribution number and finish.

At step S1008, making the distribution compact token is data " 0 " (" H "), and making readout mode is 1 level readout mode.To the decision level/distribution compact token memory circuit 22 of sector-specific, set and improved 1 grade the decision level of reading from the present decision level of reading.

In step S1007, judge and to read action when defective, be judged as employed distribution number and be not compressed, by step S1009, the distribution compact token is made as data " 1 " (" L "), readout mode is made as many level readout mode.

As mentioned above, in non-volatile memory semiconductor device 1000, by carrying out to judge easily from the reading of memory cell transistor array 1 whether background process finishes when the energized.That is, can select playback mode automatically, therefore not need to select the time of playback mode, improve user convenience.

" embodiment 11 "

Figure 26 is the figure of structure of the non-volatile memory semiconductor device 1100 of expression embodiments of the present invention 11.As shown in figure 26, non-volatile memory semiconductor device 1100 has increased distribution compact token zone 24 with respect to non-volatile memory semiconductor device 1000, and replaces data compression sequencing circuit 33 and be provided with data compression sequencing circuit 35, replace power-up sequence control circuit 34 and be provided with power-up sequence control circuit 36.

Distribution compact token zone 24 is nonvolatile storage same with the memory cell of memory cell transistor array 1.The distribution the compressed information whether compression of preserving expression threshold voltage distribution number in distribution compact token zone 24 has been finished is as the distribution compact token.In the present embodiment, when the distribution compact token being made as data " 0 " (" H "), the compression of expression threshold voltage distribution number is finished, and when the distribution compact token was made as data " 1 " (" L "), the compression of expression threshold voltage distribution number was not finished.Also write expression in the distribution compact token zone 24 and read the information of decision level.

Data compression sequencing circuit 35, the compressed action of control threshold voltage distribution number.

Power-up sequence control circuit 36, use in the decision level/distribution compact token memory circuit 22 be stored in sector-specific, expression threshold voltage distribution number compressed information and read the information of decision level whether, when energized, select playback mode.

In non-volatile memory semiconductor device 1100, the information that the decision level of sector-specific/22 storages of distribution compact token memory circuit are read from distribution compact token zone is as above-mentioned distribution compact token.

Figure 27 is the figure of flow process of the compressed action of expression threshold voltage distribution number.The processing of each step is by 35 controls of data compression sequencing circuit.

Data are write fashionable, with the non-volatile memory semiconductor device 900 of embodiment 9 similarly, after the threshold voltage distribution number has been compressed on the backstage, step S1100 with the decision level/distribution compact token memory circuit 22 of sector-specific read decision level and the represented information of distribution compact token is input to input data commutation circuit 20, generate expected value.S1101 tests in step, up to till the judgement of step S1102 is qualified, by step S1103 distribution compact token zone 24 is write data.

Figure 28 is the process flow diagram of the control carried out of the power-up sequence control circuit 36 of expression during by energized.

After the energized, at step S1111, read after decision level is set to the Read1 decision level, at step S1112, read write distribution compact token zone 24 read decision level and distribution compressed information, it is stored in the decision level/distribution compact token memory circuit 22 of sector-specific.

At step S1113, check the distribution compact token, being judged as the distribution compact token when being set at data " 1 " (" L "), move to the processing of step S1114, readout mode is set at many level readout mode, carry out the action of reading thereafter.

In step S1113, be judged as the distribution compact token when being set at data " 0 " (" H "), move to the processing of step S1115, readout mode is set at 1 level readout mode, carry out the action of reading thereafter.

According to above-mentioned non-volatile memory semiconductor device 1100, when energized, read the information that is stored in distribution compact token zone 24, with the information transmission of reading decision level/distribution compact token memory circuit 22, can judge easily thus whether background process finishes to sector-specific.That is, can select playback mode automatically, therefore not need to select the time of playback mode, improve user convenience.

" embodiment 12 "

Figure 29 is the figure of structure of the non-volatile memory semiconductor device 1200 of expression embodiments of the present invention 12.As shown in figure 29, non-volatile memory semiconductor device 1200 has increased alternate sector 41 and initialization order control circuit 43 with respect to non-volatile memory semiconductor device 1100, and replace distribution compact token zone 24 and be provided with transition and finish marked region 42, also replace write circuit 9 and be provided with write/erase circuit 44.

Alternate sector 41 contains the same Nonvolatile memery unit of a plurality of and memory cell transistor array 1.Alternate sector 41 shifts the sectors of data (data " 0 " and " 1 ") that is recorded in the memory cell transistor array 1, and the data in the predetermined sector of memory cell transistor array 1 are temporarily backed up.

Marked region 42 is finished in transition, contains the same Nonvolatile memery unit of a plurality of and memory cell transistor array 1.Transition are finished marked region 42 after repeatedly writing data " 0 ", " 1 ", and whether preservation has been finished the information (information is finished in transition) that is transitted towards maximum Vt distribution level by the expression Vt distribution of every sector and finished mark as transition.In the present embodiment, when transition were finished flag settings and are data " 0 " (" H "), expression had reached maximum Vt distribution level, finished when being labeled as data " 1 " (" L ") when transition, represented no show still.The value that marked region 42 is finished in transition outputs to not shown microcomputer by control circuit 12, and the maximum Vt distribution level that makes above-mentioned microcomputer can detect each sector in the memory cell transistor array 1 has reached maximum Vt distribution level.

The initialization action (erasing move) of initialization order control circuit 43 control store unit.Particularly, initialization order control circuit 43, use each circuit block in alternate sector 41 control stores, make that not losing matching addresses ground collects at least 1 pair of data (data " 0 " and data " 1 "), and be " 0 ", " 1 " DATA DISTRIBUTION of lowest order its initialization (rewriting).

Write/erase circuit 44 according to the control signal S1 from control circuit 12, carries out the data erase of memory cell and writing of data with sector location.Particularly, data erase is to applying 6V as whole memory cell drain electrode ends of wiping the object sector by bit line.At this moment, become high impedance as all memory cell drain electrode ends of wiping the object sector.Its result, write/erase circuit 44 is connected with the word line that is applied in negative voltage and draws electronics from the charge storage locations that whole memory cells of object sector are wiped in the conduct that has applied 6V at drain electrode end by bit line and wipe, and the threshold value of memory cell descends to negative direction.

Below, the action of above-mentioned non-volatile memory semiconductor device 1200 is described.

Figure 30 is illustrated in the transition that the Vt distribution when rewriteeing the data of Vt value distribution of (initialization) lowest order into the sector of maximum Vt distribution level is finished in Vt distribution transition.

Certain sector in the memory cell transistor array 1 is when using the random data distribution (with reference to the transition state (1) of Figure 30) of the 1st distribution, the 2nd distribution, only data is changed to " 1 " and change to " 0 " from " 1 " from " 0 " to write.

When occupying maximum distribution level (the 3rd distribute), finish zone 42 by control circuit 12 in transition and write transition and finish information (being data " 0 " (" H ") under this situation) (with reference to the transition state (2) of Figure 30).Then, when detecting at least one data " 0 " (" H ") by control circuit 12, control circuit 12 is finished mark to decision level/distribution compact token memory circuit 22 output datas " 0 " (" H ") of sector-specific as transition, when detecting all data when being data " 1 " (" L "), control circuit 12 is finished mark to decision level/distribution compact token memory circuit 22 output datas " 1 " (" L ") of sector-specific as transition.Control circuit 12 is also finished information to not shown microcomputer output transition.What marked region 42 was finished in transition reads action and write activity, with memory cell transistor array 1 in the embodiment 11 to read action identical with write activity, so in this description will be omitted.

Then, as shown in figure 31, mark is finished in not shown microcomputer inspection transition, if transition are finished and being labeled as data " 1 " (" L "), then all sectors do not reach the maximum distribution level, and therefore above-mentioned microcomputer is not indicated the execution of initialization action.If transition are finished and are labeled as data " 0 " (" H "), then initialized at least one sector of needs is indicated the execution of initialization action.

According to the indication of above-mentioned microcomputer, during the beginning initialization, according to initialization order flow process shown in Figure 31, initialization order control circuit 43 control initialization action.

At first, playback record is in all data " 0 ", " 1 " of initialization object sector, by output data commutation circuit 5 sense data is transferred to input data commutation circuit 20, input data commutation circuit 20 makes by checking circuit 7 and writes data latches 8 and latch the data that are transmitted.

Then, the data that are latched are write alternate sector 41.That is, the sectors of data of initialization object is transferred to alternate sector 41 (with reference to the transition state (3) of Figure 30).Write activity to alternate sector 41 is identical with the action of embodiment 11, therefore in this description will be omitted.

Then, wipe the executory object sector data of initialization, all bit data are become the data " 1 " (with reference to the transition state (4) of Figure 30) of lowest order distribution level.

At this, specify erasing move.By the decision level control circuit 14 that reception is controlled from the control circuit 12 of the control signal of above-mentioned microcomputer, voltage control circuit 15 is controlled.Thus, the negative voltage of voltage control circuit 15 output-5V offers line decoder 2.At this moment, by the line decoder that control signal S1 controlled 2 of control circuit 12, whole memory cell gate ends of wiping the object sector are applied-negative voltage of 5V by word line.By the write/erase circuit 44 that control signal S1 is controlled, whole memory cell drain electrode ends of the sector of object being wiped in conduct by word line apply 6V voltage.At this moment, whole memory cell source terminals of wiping the object sector become high impedance.Its result, write/erase circuit 44 is connected with the word line that is applied in negative voltage, and carries out by word line drain electrode end being applied the wiping of the whole memory cell of wiping the object sector of 6V, attract electronics from charge storage locations, the threshold value of memory cell descends to negative direction.

Behind the erasing move (with reference to the transition state (4) of Figure 30) of this initialization object sector, playback record arrives input data commutation circuit 20 by output data commutation circuit 5 with the data transmission of reading in all data " 0 ", " 1 " of alternate sector 41.And input data commutation circuit 20 makes by checking circuit 7 and writes data latches 8 and latch the data that are transmitted.At this, from the memory cell transistor array 1 of the action of the sense data of alternate sector 41 and embodiment 11 to read action identical, therefore in this description will be omitted.

Then, carry out data " 0 ", " 1 " that initialization (rewriting) distributes as lowest order the data that are latched being carried out the executory memory array of initialization sector.That is, write/erase circuit 44 is transferred to initialization object sector (with reference to the transition state (5) of Figure 30) with the data of alternate sector 41.After shift finishing, wipe the pre-determined bit that marked region 42 is finished in the transition corresponding with shifting sector after finishing, reset to data " 1 " (" L ") by the action identical with the sector erasing of memory cell transistor array 1.After resetting, wipe alternate sector 41 (storing the state of data " 1 "), be equipped with in next initialization action (with reference to the transition state (6) of Figure 30).

Then, as shown in figure 31, finish mark by not shown microcomputer inspection transition once more.Thus, carry out initialization action repeatedly, up to transition finish be labeled as data " 1 " (" L ") till.

According to above-mentioned non-volatile memory semiconductor device 1200, can carry out the initialization of sector by not shown microcomputer.For writing of data " 1 ", " 0 ", only get final product with 1 erasing move, all need the non-volatile memory semiconductor device in the past of erasing move to compare during therefore with each overwriting data " 1 ", " 0 ", reduced erasing times, therefore the reliability of memory cell improves, and can improve the indegree of writing of data.

In the present embodiment, explanation be that Vt distribution number is 3 a situation, even if but use the individual Vt distribution of N (natural number that N:3 is above) also can obtain same effect.

In the present embodiment, finish when being labeled as data " 0 " (" H ") in transition, initialization is carried out in this sector, certainly, also can finish when being labeled as data " 1 " (" L ") in transition, that is, when the Vt of the data " 1 " to " 0 " of most significant digit distributes Vt distribution before occupying maximum Vt distribution level, carry out initialization.

" embodiment 13 "

Figure 32 is the figure of structure of the non-volatile memory semiconductor device 1300 of expression embodiments of the present invention 13.Shown in figure 32, non-volatile memory semiconductor device 1300 replaces the power-up sequence control circuit 36 of non-volatile memory semiconductor device 1200 and is provided with background action sequencing circuit 46.Whether the initialization action that non-volatile memory semiconductor device 130 has the expression sector is that executory BG carries out mark under backstage (BG), carries out mark to not shown microcomputer output BG.Thus, not shown microcomputer can detect the initialization action of sector whether just (BG) carries out on the backstage.

Utilize background action sequencing circuit 46, BG carries out when being marked at the initialization action of sector, because non-volatile memory semiconductor device 1300 is a busy condition, so data of being arranged to " 0 " (" H ").After the initialization action of sector finishes, be arranged to data " 1 " (" L ").

Below, the action of above-mentioned non-volatile memory semiconductor device 1300 is described.

When never not illustrated microcomputer input control signal, background action sequencing circuit 46 is read by output data commutation circuit 5 and is kept at the data that marked region 42 is finished in transition.When marked region 42 sense datas " 0 " (" H ") are finished in transition, exist transition to finish the sector at least.In this case, output data " 0 " (" H ") is carried out mark as BG, and (BG) carries out transition and finish the initialization action of sector on the backstage according to the initialization order flow process of Figure 33.

At this moment, non-volatile memory semiconductor device 1300 uses BG to carry out mark, can not receive this situation of control signal and be sent to not shown microcomputer.After the sector of backstage (BG) initialization action finishes, be sent to not shown microcomputer in order to have finished this situation of preparation that receives control signal, background action sequencing circuit 46 output datas " 1 " (" L ") are carried out mark as BG.

As mentioned above, according to embodiment 13, obtain the effect same with the non-volatile memory semiconductor device 1200 of embodiment 12, and have background action sequencing circuit 46 and BG and carry out mark, thus can be in the free time of not importing from not shown Controlled by Microcomputer signal, carry out the sector initialization action, do not have tangible initialization action.That is, can shorten data and write fashionable initialization time, can improve user convenience.

" embodiment 14 "

Figure 34 is the figure of structure of the non-volatile memory semiconductor device 1400 of expression embodiments of the present invention 14.As shown in figure 34, non-volatile memory semiconductor device 1400 has increased short-term assurance marked region 45 in non-volatile memory semiconductor device 1200.

Short-term guarantees that marked region 45 is by constituting with the same Nonvolatile memery unit of memory cell transistor array 1.

In non-volatile memory semiconductor device 1400, write/erase circuit 44 is by the control signal S1 control of exporting from control circuit 12, and the action of selecting to write (the long-term assurance) pattern usually and using the high speed of carrying out than the time that writes the pattern weak point usually to write the arbitrary pattern in (short-term assurance) pattern is moved.Particularly, write/erase circuit 44 is when writing (the long-term assurance) pattern usually, check voltage in the time of will writing data " 1 ", " 0 " be set at PV1 (=4.5V), PV2 (=7.0V), when at a high speed writing (short-term assurance) pattern, the check voltage in the time of will writing data " 1 ", " 0 " be set at PVS1 (=3.3V), PVS2 (=5.8V).Wherein, the Read1 decision level (=3V), the Read2 decision level (=it all is constant 5.5V) writing fashionable under any pattern.

Writing under (short-term assurance) pattern at a high speed, by the Vt tolerance limit is diminished to short-term assurance tolerance limit from long-term assurance tolerance limit (margin), can reduce to write fashionable Vt distribution amount of movement, carry out than writing more writing of high speed usually, but this will sacrifice the Vt tolerance limit, therefore data preservation characteristics variation guarantees data and handles as the short-term than common weak point.

Guarantee marked region 45 in short-term, preserve such information, promptly writing (long-term guarantee) pattern usually and writing the information whether expression under any state in (short-term assurance) pattern preserves each sector location of data at a high speed, and this information is being guaranteed mark as short-term.

As shown in figure 34, control circuit 12, control by control signal, to guarantee that the label information that marked region 45 is read is taken into by output data commutation circuit 5 from short-term, so that at least one sector that not shown microcomputer can detect in the memory cell transistor array 1 guarantees data and is written into this situation as short-term, under the situation that has at least 1 short-term value preserving sector, export short-term as data " 0 " (" H ") and guarantee mark.

Below, the action of above-mentioned non-volatile semiconductor devices 1400 is described.

Figure 35 is illustrated in usually to write to write fashionable Vt distribution transition under (the long-term assurance) pattern and writing the figure that writes fashionable Vt distribution transition under (short-term assurance) pattern at a high speed.

at a high speed write the write activity under (short-term assurances) pattern and writing usually write activity difference under (long-term assurance) pattern only be when writing data " 1 ", " 0 " check voltage PVS1 (=3.3V), PVS2 (=5.8V).About other write activities, identical with the action of the non-volatile semiconductor devices 1100 of embodiment 11, therefore in this detailed.

Write (short-term assurance) pattern by the high speed that check voltage is reduced, for example distribute and write under the situation of data " 1 ", " 0 " in data " 1 " from lowest order, with shown in Figure 36 dependent figure of total write time of memory cell threshold voltage (expression), the situation of having implemented to write (about 10ms) under (the long-term assurance) pattern is different writing usually, the total write time with about 1/10 (about 1ms), the transition of threshold voltage have been finished.That is, improved the writing speed of about 1 order of magnitude.

Then, write this situation of short-term assurance data in order to detect to write the sector that is write under (short-term assurance) pattern in such high speed, and utilize control circuit 12, short-term is guaranteed that marked region 45 writes short-term guarantee information (data " 0 " (" H ")).

Then, read the data that the short-term corresponding with each sector guarantees marked region 45.Detecting by control circuit 12 under the situation of at least 1 data " 0 ", control circuit 12 output datas " 0 " (" H ") guarantee mark as short-term, detecting under the situation that all are data " 1 ", output data " 1 " (" L ") guarantees mark as short-term.What short-term guaranteed marked region 45 reads action and write activity, with the memory cell transistor array 1 of the 1st embodiment to read action identical with write activity, so in this description will be omitted.

Then, use Figure 37 and Figure 38 that long-term assurance action is described.Figure 38 is the figure of the long-term assuranceization write sequence flow process of expression.

Not shown microcomputer checks that short-term guarantees mark, if its value is data " 1 " (" L "), then all memory array sectors write writing usually under (the long-term assurance) pattern.Therefore, do not carry out long-term assurance action.If short-term guarantees to be labeled as data " 0 " (" H "), then there is 1 needs sector of assurance for a long time at least, therefore long-term assuranceization is carried out in this sector and write.

Then, all data " 1 ", " 0 " of playback record in the sector of long-term assuranceization object is arrived input data commutation circuit 20 by output data commutation circuit 5 with the data transmission of reading.Import data commutation circuit 20, make by checking circuit 7 to write the data that data latches 8 latchs transmission.

Then, write/erase circuit 44 is set under the writing usually of PV1, PV2 (the long-term assurance) pattern will writing level of test, to for a long time the sector of assurance write institute's latched data (the long-term assuranceization in (2) of Figure 37 writes).To the above-mentioned write activity of the sector of assurance for a long time, identical with the action of embodiment 11, therefore in this detailed.

Implemented after this a succession of long-term assuranceization writes, write the corresponding short-term in object sector with long-term assuranceization at last and guarantee marked region 45, by being wiped free of with the same action of the sector erasing of memory cell transistor array 1, predetermined position is reset data " 1 ".

Then, shown in the long-term assurance write sequence flow process of Figure 38, check that by not shown microcomputer short-term guarantees mark once more, assurance write activity for a long time repeatedly is till short-term guarantees that mark becomes data " 1 " (" L ").

As mentioned above, according to present embodiment, short-term is set guarantees that marked region 45 and short-term guarantee mark, the high speed that has reduced check voltage also is set writes (short-term assurance) pattern, can reduce the amount of movement (write time) and the amount of testing (proving time) of the threshold voltage when writing data " 1 ", " 0 " thus.That is, can carry out data " 1 " more at a high speed, the rewriting of " 0 ".

In addition because can carry out control based on the sector assurance action for a long time of not shown microcomputer, so write at a high speed implemented to write under (short-term assurances) pattern after, implementing for a long time between can be at one's leisure, assuranceization writes.Therefore, can realize significantly writing at a high speed and can realizing long-term assurance.

Guarantee to be labeled as data " 0 " (" H ") and maximum Vt distribution level arrival predetermined level in short-term, mark is finished in transition to be become under the situation of data " 0 " (" H "), can make initialization action preferential, according to initialization order flow process shown in Figure 31, utilize alternate sector 41, can not diminish matching addresses ground and collect and a pair of at least data of initialization (data " 0 " and data " 1 "), make it become long-term assurance data in the distribution of lowest order.Thus, long-term assurance write activity can be omitted, power consumption can be reduced.

In the present embodiment, carry out writing of data writing under (short-term assurances) pattern at a high speed all, but when writing data the 1st time, carry out under (long-term assurance) pattern writing usually, the 2nd time later when writing data, can implement writing under (short-term assurance) pattern at a high speed.

" embodiment 15 "

Figure 39 is the figure of structure of the non-volatile memory semiconductor device 1500 of expression embodiments of the present invention 15.As shown in figure 39, non-volatile memory semiconductor device 1500 replaces the power-up sequence control circuit 36 of non-volatile memory semiconductor device 1400 and is provided with background action sequencing circuit 46.

The initialization action of background action sequencing circuit 46 control sectors is so that wait for that in instruction time of reception carries out the initialization of sector on the backstage.

Non-volatile memory semiconductor device 1500, have with expression the zone (not shown) that just information of the long-term assurance write activity of (BG) execution sector is preserved as BG execution mark on the backstage, not shown microcomputer can detect just long-term this situation of assurance write activity of (BG) execution sector on the backstage.When carrying out the long-term assurance write activity of sector, non-volatile memory semiconductor device is a busy condition, so BG carries out mark and is set to data " 0 " (" H ") by background action sequencing circuit 46.After the long-term assurance write activity of sector finished, BG carried out mark and is set to data " 1 " (" L ") by background action sequencing circuit 46.

Below, the action of above-mentioned non-volatile memory semiconductor device 1500 is described.

When the never not illustrated microcomputer of control signal was input to control circuit 12, background action sequencing circuit 46 was read the data that are kept in the short-term assurance marked region 45 by output data commutation circuit 5.If short-term is guaranteed that marked region 45 writes data " 0 " (" H "), then exist at least 1 short-term to guarantee the sector.Background action sequencing circuit 46 is when existing short-term to guarantee the sector, and output data " 0 " (" H ") is carried out mark as BG.Short-term guarantees the long-term assurance write sequence flow process of the long-term assurance write activity of sector according to Figure 40, controls to make that (BG) carries out on the backstage.At this moment, background action sequencing circuit 46 is carried out mark by BG, can't receive this situation of control signal to not shown microcomputer transmission.

After the assurance release for a long time of the sector of backstage (BG), be sent to not shown microcomputer for having finished this situation of preparation that receives control signal, background action sequencing circuit 46 is carried out mark with data " 1 " (" L ") as BG and is outputed to above-mentioned not shown microcomputer.

As mentioned above, according to present embodiment, obtain the effect same with the non-volatile memory semiconductor device 1400 of embodiment 14, and be provided with background action sequencing circuit 46 and BG and carry out mark, thus can be at the free time of not importing from not shown Controlled by Microcomputer signal, assurance write activity for a long time.Therefore, there is not the action of obvious long assuranceization.That is, the write time of data " 1 ", " 0 " can be shortened, user convenience can be improved.

Guaranteeing that to short-term marked region writes data " 0 " (" H ") and maximum Vt distribution level arrives predetermined level, existing data " 0 " to be written to transition finishes under the situation of sector of marked region (" H "), can make initialization action preferential, according to initialization order flow process shown in Figure 33, utilize alternate sector 41, can not diminish matching addresses ground and collect at least 1 pair of data (data " 0 " and data " 1 "), and make it be initialized as long-term assurance data in the distribution of lowest order.Thus, long-term assurance write activity can be omitted, power consumption can be reduced.

" embodiment 16 "

Figure 41 is the figure of structure of the non-volatile memory semiconductor device 1600 of expression embodiments of the present invention 16.As shown in figure 41, non-volatile memory semiconductor device 1600 has increased to wipe to finish marked region 50 and wipe with respect to non-volatile memory semiconductor device 1200 and has finished marker stores circuit 53.

Wiping and finishing marking circuit 50 is non-volatile memory same with memory cell transistor array 1.Finish marked region 50 and finish mark and preserve each sector is represented whether each sector is that the information (wipe and finish label information) of wiping completion status is finished mark as wiping wiping as wiping.

Wipe and finish marker stores circuit 53, have to be stored in to write to wipe and finish the register area that wiping of marked region 50 finished label information, based on writing the address and wiping the information of finishing mark, to control circuit 12 output writing prohibition signals.

Below, the action of above-mentioned non-volatile memory semiconductor device 1600 is described.

At first, use Figure 42's wipes sequence flow to describing based on wiping of erasing instruction.

At first, by above-mentioned microcomputer, erasing instruction is sent in the sector that wipe.(normally writing at this moment, the state of the random data of data " 0 ", " 1 ") in the sector that will wipe

Then, initialization order control circuit 43 is that the information of this situation of erase status writes to wipe and finishes marked region 50 with the sector of indicating to wipe, and wipes the state that mark becomes data " 0 " (" H ") of finishing., with wipe the information (wipe the finish state that be labeled as data " 0 " (" H ")) of finishing marked region 50 be transferred to wipe finish marker stores circuit 53, finished and wiped thereafter.At this moment, write on " 0 " of the sector that will wipe, the random data of " 1 " does not change, just wipe the information of finishing mark and change.

Then, use the write sequence process description write activity of Figure 42.

At first, by above-mentioned microcomputer the sector that will write is sent and write instruction.

Then, check the information of finishing marker stores circuit 53 of wiping by initialization order control circuit 43.If the wiping to finish of the sector that will write is labeled as data " 1 " (" L "), then user's data is written into, therefore to control circuit 12 output writing prohibition signals.If the wiping to finish of the sector that will write is labeled as data " 0 " (" H "), then can write, wiped the information of finishing marked region 50, make the state that is labeled as data " 1 " (" L ") of finishing of wiping.The sector enforcement " 0 " that write, the random data of " 1 " write thereafter.And, finish marker stores circuit 53 transmission and wipe the information of finishing marked region 50 to wiping, write and finish." 0 " in this case, the random data of " 1 " write identical with embodiment 12.

As mentioned above,, be provided with to wipe to finish marked region 50 and wipe and finish marker stores circuit 53, when wiping according to erasing instruction thus, threshold voltage distribution is moved, just can wipe mark realization erase status by foundation according to present embodiment.Therefore, compare, can reduce the needed time of erasing move itself, can shorten the erasing time largely with wiping in the past.

" embodiment 17 "

Figure 43 is the figure of structure of the non-volatile memory semiconductor device 1700 of expression embodiments of the present invention 17.

As shown in figure 43, non-volatile memory semiconductor device 1700 is characterised in that, structure at the non-volatile memory semiconductor device 1600 of embodiments of the present invention 16, be provided with exchange message storage area 51, erasing times storage area 52, address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish marker stores circuit 55, make it possible to thus when initialization, the erasing times of search free sector, with initialized sector of needs and the minimum free sector exchange of erasing times, the free sector minimum to erasing times shifts " 0 ", initialization is implemented in " 1 " pairing distribution.

Exchange message storage area 51 is, the erasing times of search free sector when initialization, during free sector exchange that the initialized sector of needs and erasing times is minimum, each sector record has been represented whether to carry out the non-volatile memory of the sector auxiliary information (exchange sector auxiliary information) of exchange.

Erasing times storage area 52 can be to the non-volatile memory of each sector storage to the mobile mobile number of times of the lowest order distribution corresponding with data " 1 ".

Address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish marker stores circuit 55, have to preserve to write to wipe and finish the register area that wiping of marked region 50 finished label information, preservation writes the register area that wiping of exchange message storage area 51 finished label information, write the register area of the erasing times information of erasing times storage area 52 with preservation, has following function: based on the exchange sector auxiliary information of each sector and erasing times with wipe information such as finishing mark, carry out the function of sevtor address conversion, with based on writing the address and wiping the information of finishing mark, to the function of control circuit 12 output writing prohibition signals.

Below, the action of above-mentioned non-volatile memory semiconductor device 1700 is described.

At first, use the sequence flow of wiping of Figure 44 to describe initialization.Flow process before initialization begins is identical with embodiments of the present invention 12.After initialization begins, inspection address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe the wiping of each sector of finishing marker stores circuit 55 to finish mark, if all sectors all do not have free sector (all sectors wipe to finish be labeled as data " 1 " (" L ")), then initialization is implemented in the sector that will wipe.If there is free sector (existence is wiped and finished the sector that is labeled as data " 0 " (" H ")), the erasing times information of finishing marker stores circuit 55 according to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and wipe and finish label information then, selective erasing are finished and are labeled as object sector in return, the minimum sector of data " 0 " (" H ") and erasing times.

, exchange message storage area 51 write exchange sector auxiliary information, the exchange sector auxiliary information of exchange message storage area 51 is transferred to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish marker stores circuit 55 thereafter.And based on address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe the register information of the exchange message memory circuit of finishing marker stores circuit 55, conversion sevtor address, the object sector is wiped in exchange.(initialization) data " 0 ", " 1 " are shifted in sector after the exchange.Thus, implemented to wipe to being scheduled to implement initialized sector (sector after the exchange) originally.Wiping of exchange message storage area 51 finished marked region to be write, to wipe and finish mark as data " 0 " (" H "), with this information transmission to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish the register that wiping of marker stores circuit 55 finished the marker stores circuit.

Thereafter, no matter carrying out under the common initialized situation, still carrying out after the exchange under the initialized situation, all carry out the renewal of erasing times storage area 52, make erasing times add 1, and with the erasing times information transmission to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe register of the erasing times memory circuit of finishing marker stores circuit 55.Like this, initialization finishes, and flow process thereafter is identical with embodiments of the present invention 12.

As mentioned above, according to non-volatile memory semiconductor device 1700, structure at the non-volatile memory semiconductor device 1600 of embodiment 16, be provided with exchange message storage area 51, erasing times storage area 52, address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish marker stores circuit 55, make it possible to thus when initialization, the erasing times of search free sector, with initialized sector of needs and the minimum free sector exchange of erasing times, the free sector minimum to erasing times shifts " 0 ", initialization is implemented in " 1 " pairing distribution.Therefore, can make the erasing times equalization, can realize the non-volatile memory semiconductor device that reliability is high all sectors.

" embodiment 18 "

When having the minimum free sector of a plurality of erasing times, can shown in the process flow diagram of Figure 45, control the non-volatile memory semiconductor device 1700 of embodiment 17 like that.

Embodiment 18 is characterised in that, in the non-volatile memory semiconductor device 1700 of embodiments of the present invention 17, when having the minimum free sector of a plurality of erasing times, the position of search most significant digit threshold voltage distribution makes the minimum sector of most significant digit threshold voltage distribution and need carry out the exchange of initialized sector.Below, its action is described.

At first, use the initialization order process description initialization of Figure 45.Flow process before initialization begins is identical with embodiments of the present invention 12.After initialization begins, inspection address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe the wiping of each sector of finishing marker stores circuit 55 to finish mark, if all sectors all do not have free sector (all sectors wipe to finish be labeled as data " 1 " (" L ")), then initialization is implemented in the sector that will wipe.If there is free sector (existence is wiped and finished the sector that is labeled as data " 0 " (" H ")), the erasing times information of finishing marker stores circuit 55 according to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and wipe and finish label information then, search is wiped to finish and is labeled as data " 0 " (" H ") and the minimum sector of erasing times.

Thereafter, exist a plurality of wiping to finish when being labeled as the minimum sector of data " 0 " (" H ") and erasing times, the position of the threshold voltage distribution of the sector of search erasing times minimum, the minimum sector of selection most significant digit threshold voltage distribution is the object sector in return., exchange message storage area 51 write exchange sector auxiliary information, the exchange sector auxiliary information of exchange message storage area 51 is transferred to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish marker stores circuit 55 thereafter.

Then, based on address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe the register information of the exchange message memory circuit of finishing marker stores circuit 55, conversion sevtor address, the object sector is wiped in exchange.(initialization) data " 0 ", " 1 " are shifted in sector after the exchange.Thus, implemented to wipe to being scheduled to implement initialized sector (sector after the exchange) originally.Finish wiping of marked region 50 and finish marked region and write wiping, to wipe and finish mark as data " 0 " (" H "), with this information transmission to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish the register that wiping of marker stores circuit 55 finished the marker stores circuit.

Thereafter, no matter carrying out under the common initialized situation, still carrying out after the exchange under the initialized situation, all carry out the renewal of erasing times storage area 52, make erasing times add 1, and with the erasing times information transmission to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe register of the erasing times memory circuit of finishing marker stores circuit 55.Like this, the initialization that is through with, flow process thereafter is identical with embodiments of the present invention 12.

As mentioned above, according to embodiment 18, in the non-volatile memory semiconductor device 1700 of embodiment 17, when having the minimum free sector of a plurality of erasing times, the position of search most significant digit threshold voltage distribution makes the minimum sector of most significant digit threshold voltage distribution and need carry out the exchange of initialized sector.Thus, can not increase the most significant digit threshold voltage distribution and reach maximum level number of rewrites before.Therefore, compare, can further realize the raising of user convenience with embodiment 17.

" embodiment 19 "

Also can shown in the process flow diagram of Figure 46, control the non-volatile memory semiconductor device 1700 of embodiment 17 like that.In the present embodiment, erasing times storage area 52 has or not and all can.

Present embodiment 19 is characterised in that, non-volatile memory semiconductor device 1700 to embodiments of the present invention 17, formation exchange message storage area 51 and address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish marker stores circuit 55, make when initialization, the position of search most significant digit threshold voltage distribution, exchange need be carried out the minimum sector of initialized sector and most significant digit threshold voltage distribution, to the minimum sector transferring data of most significant digit threshold voltage distribution, implement initialization.Below, its action is described.

At first, use the initialization order process description initialization of Figure 46.Flow process before initialization begins is identical with embodiments of the present invention 12.After initialization begins, inspection address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe the wiping of each sector of finishing marker stores circuit 55 to finish mark, if all sectors all do not have free sector (all sectors wipe to finish be labeled as data " 1 " (" L ")), then initialization is implemented in the sector that will wipe.If there is free sector (existence is wiped and finished the sector that is labeled as data " 0 " (" H ")), then utilize address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe to finish wiping of marker stores circuit 55 and finish label information and threshold voltage distribution search, obtain to wipe and finish the minimum sector that is labeled as data " 0 " (" H ") and most significant digit threshold voltage distribution, the minimum sector of selection most significant digit threshold voltage distribution is the object sector in return.Thereafter, write the exchange sector auxiliary information of exchange message storage area 51, the exchange sector auxiliary information of exchange message storage area 51 is transferred to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe register of the exchange message memory circuit of finishing marker stores circuit 55.

Then, based on address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe information of the register of the exchange message memory circuit of finishing marker stores circuit 55, the conversion sevtor address, the object sector is wiped in exchange, and (initialization) data " 0 ", " 1 " are shifted in the sector after the exchange.Thus, implemented to wipe to being scheduled to implement initialized sector (sector after the exchange) originally.Finish marked region 50 and write wiping, to wipe and finish mark as data " 0 " (" H "), with this information transmission to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish the register that wiping of marker stores circuit 55 finished the marker stores circuit.Like this, the initialization that is through with, flow process thereafter is identical with embodiments of the present invention 17.

As mentioned above, according to embodiment 19, can be when initialization, the position of search most significant digit threshold voltage distribution, exchange need be carried out the minimum sector of initialized sector and most significant digit threshold voltage distribution, to the minimum sector transferring data of most significant digit threshold voltage distribution, implement initialization.Thus, can not increase the most significant digit threshold voltage distribution and reach maximum level number of rewrites before, can further realize the raising of user convenience.

" embodiment 20 "

Also can shown in the process flow diagram of Figure 47, control the non-volatile memory semiconductor device 1700 of embodiment 17 like that.

Embodiment 20 is characterised in that, in the non-volatile memory semiconductor device of embodiments of the present invention 19, when having the minimum sector of a plurality of most significant digit threshold voltage distribution, the search erasing times makes the minimum sector of erasing times and need carry out the exchange of initialized sector.Below, its action is described.

At first, use the initialization order process description initialization of Figure 47.Flow process before initialization begins is identical with embodiments of the present invention 17.After initialization begins, inspection address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe the wiping of each sector of finishing marker stores circuit 55 to finish mark, if all sectors all do not have free sector (all sectors wipe to finish be labeled as data " 1 " (" L ")), then initialization is implemented in the sector that will wipe.If there is free sector (existence is wiped and finished the sector that is labeled as data " 0 " (" H ")), then finish wiping of marker stores circuit 55 and finish label information and threshold voltage distribution search according to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe, obtain to wipe and finish the minimum sector that is labeled as data " 0 " (" H ") and most significant digit threshold voltage distribution, when having the minimum sector of a plurality of most significant digit threshold voltage distribution, according to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe the erasing times information of finishing marker stores circuit 55, the sector of selective erasing least number of times is the object sector in return.

, exchange message storage area 51 write exchange sector auxiliary information, the exchange sector auxiliary information of exchange message storage area 51 is transferred to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish marker stores circuit 55 thereafter.Then, based on address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe register information of the exchange message memory circuit of finishing marker stores circuit 55, the conversion sevtor address, the object sector is wiped in exchange, and (initialization) data " 0 ", " 1 " are shifted in the sector after the exchange.Thus, implemented to wipe to being scheduled to implement initialized sector (sector after the exchange) originally.Finish marked region 50 and write wiping, to wipe and finish mark as data " 0 ", with this information transmission to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe and finish the register that wiping of marker stores circuit 55 finished the marker stores circuit.Thereafter, no matter carrying out under the common initialized situation, still carrying out after the exchange under the initialized situation, all carry out the renewal of erasing times storage area 52, make erasing times add 1, and with the erasing times information transmission to address translation circuit/exchange message memory circuit/erasing times memory circuit/wipe register of the erasing times memory circuit of finishing marker stores circuit 55.Like this, initialization finishes, and flow process thereafter is identical with embodiments of the present invention 17.

As mentioned above, according to embodiment 20, in the non-volatile memory semiconductor device of embodiments of the present invention 19, when having the minimum sector of a plurality of most significant digit threshold voltage distribution, the search erasing times makes the minimum sector of erasing times and need carry out the exchange of initialized sector.Thus, compare, can make the erasing times equalization, can realize the non-volatile memory semiconductor device that reliability is high all sectors with the non-volatile memory semiconductor device of embodiments of the present invention 19.

" embodiment 21 "

Figure 48 is the figure of structure of the non-volatile memory semiconductor device 2100 of expression embodiments of the present invention 21.

As shown in figure 48, this embodiment 21 is characterised in that the non-volatile memory semiconductor device 1600 to embodiments of the present invention 16 is provided with data address admin table 56, can the data in the zone shown in the data address admin table 56 be fixed.Particularly, data address admin table 56 is made of non-volatile memory.

Non-volatile memory semiconductor device 2100, finish mark and wiping of mixing of data " 0 ", " 1 " finished the sector to carry out writing of a few-bit fashionable according to wiping, do not need the data of certain address scope (to the scope of data for " 1 " that write of this scope) are write, therefore has the function that is data " 1 " when reading the data that are written to the address realm in the data address admin table all the time, so that can write efficiently, below, the action of non-volatile memory semiconductor device 2100 is described.

Use the write sequence process description write activity of Figure 49.At first, never illustrated microcomputer sends the instruction that the sector that will write is write.Then, utilize initialization write control circuit 43, check the information of finishing marker stores circuit 53 of wiping.Finish and be labeled as data " 1 " if will write wiping of sector, user's data is written into, and therefore wipes and finishes marker stores circuit 53 to control circuit 12 output writing prohibition signals.Finish and be labeled as data " 0 " (" H ") if will write wiping of sector, then can write, wipe, make the state that is labeled as data " 1 " (" L ") of finishing of wiping wiping the information of finishing marked region 50.

Check if whether write be all objects that will write sector in, will write all objects sector in, then implement random data write thereafter.If not, then random data is carried out in the position that writes object address and write, for the position that writes outside the object, write data address admin table 56 with writing the outer address information of object.In this case, for example only start address and the FA final address information that writes the outer address of object is write.Under any circumstance, all will wipe the information transmission of finishing marked region 50 and finish marker stores circuit 53, and write and finish to wiping.In this case, the random data of data " 0 ", " 1 " writes identical with embodiment 12.

Then, use the sequence flow explanation of reading of Figure 49 to read.At first, send sense order, begin to read from above-mentioned microcomputer.Then, above-mentioned microcomputer read address data admin table 56 if the address of reading object does not enter in the address realm of reading from data address admin table 56, then carries out common reading.If the address of reading object enters in the address realm of reading from data address admin table 56, then from sensor amplifier 3 output fixed datas (being data " 1 " in this embodiment) as sense data.For common read identical with embodiments of the present invention 12.

As mentioned above,, the non-volatile memory semiconductor device 1600 of embodiments of the present invention 16 is provided with data address admin table 56 according to embodiment 21, thus can be to the data in the zone shown in the data address admin table 56, fixedly sense data.Thus, wiping of mixing of data " 0 ", " 1 " finished the sector, and to carry out writing of a few-bit fashionable, can not move writing the threshold voltage distribution of the position beyond the object, can realize the non-volatile memory semiconductor device that the write time is short.

As mentioned above, non-volatile memory semiconductor device of the present invention is when rewriteeing data, no The erasing move of the data that need in non-volatile memory semiconductor device in the past, carry out, Therefore has the effect that can shorten significantly the rewriting time, as using multiple threshold voltage branch It is useful that the cloth state is stored non-volatile memory semiconductor device of data etc.

Claims

1. a non-volatile memory semiconductor device carries out writing and reading of data according to the instruction of being imported, and it is characterized in that, comprising:

The programmed order control circuit, each data that data centralization contained that will constitute by the data of a plurality of values, be stored in above-mentioned memory cell accordingly with any threshold voltage distribution in the above-mentioned threshold voltage distribution more than 3, and when rewriting is stored in the data of above-mentioned memory cell, make the threshold voltage distribution of in the storage of data, using move the rewriting of carrying out data to a direction.

2. non-volatile memory semiconductor device according to claim 1 is characterized in that:

Above-mentioned programmed order control circuit makes the threshold voltage distribution of lowest order in identical all the time data and the above-mentioned threshold voltage distribution more than 3 in the above-mentioned data set or most significant digit corresponding, makes above-mentioned memory cell stores data.

3. non-volatile memory semiconductor device according to claim 2 is characterized in that:

Above-mentioned programmed order control circuit uses two continuous in the above-mentioned threshold voltage distribution more than 3 threshold voltage distribution to store data.

4. non-volatile memory semiconductor device according to claim 3 is characterized in that:

Above-mentioned programmed order control circuit rewrite to use n-1 to distribute and n distributes these two when distributing the data of being stored, it is become the state that only uses the n distribution after, according to the data of being given, the threshold voltage distribution of using is moved to n+1 distribute, wherein, n is a natural number.

5. non-volatile memory semiconductor device according to claim 3 is characterized in that:

Above-mentioned programmed order control circuit rewrite to use n-1 to distribute and n distributes these two when distributing the data of being stored, and according to the data of being given, the threshold voltage distribution of using is moved to directly n distributes and the n+1 distribution, and wherein, n is a natural number.

6. non-volatile memory semiconductor device according to claim 2 is characterized in that:

Above-mentioned data set is made of 2 Value Datas,

Above-mentioned programmed order control circuit uses the threshold voltage distribution more than 3, makes above-mentioned 2 Value Datas of above-mentioned memory cell stores.

7. non-volatile memory semiconductor device according to claim 6 is characterized in that:

Above-mentioned programmed order control circuit, make data of above-mentioned data centralization fixing corresponding with the threshold voltage distribution of most significant digit or lowest order, and when rewriteeing the data of being stored, only make the memory cell that need change move threshold voltage distribution to the threshold voltage distribution of above-mentioned most significant digit or lowest order.

8. non-volatile memory semiconductor device according to claim 1 is characterized in that:

Above-mentioned programmed order control circuit makes the multi-group data collection corresponding with above-mentioned threshold voltage distribution more than 3, makes above-mentioned memory cell stores data.

9. non-volatile memory semiconductor device according to claim 8 is characterized in that:

Above-mentioned data set is made of 2 Value Datas,

Above-mentioned programmed order control circuit makes above-mentioned 2 Value Datas is stored accordingly with two continuous threshold voltage distribution respectively.

10. non-volatile memory semiconductor device according to claim 9 is characterized in that, also comprises:

Writing unit in advance becomes the n+1 distribution with the memory cell of n distribution; With

Data write unit, only make to write with corresponding to the different memory of data cell moving of the data of n+1 distribution to the n+2 distribution.

11. non-volatile memory semiconductor device according to claim 8 is characterized in that:

Above-mentioned data set is made of 2 Value Datas,

12. non-volatile memory semiconductor device according to claim 11 is characterized in that:

Above-mentioned programmed order control circuit when overwriting data, only makes the threshold voltage distribution of the memory cell that data change move to a high position.

13. non-volatile memory semiconductor device according to claim 11 is characterized in that, also comprises:

The data compression sequencing circuit, operation after data rewrite finishes is not under the executing state, on the backstage with above-mentioned memory cell array from the state that uses the threshold voltage distribution more than three kinds to the state that has used m threshold voltage distribution and these two threshold voltages of m+1 threshold voltage distribution, employed distribution number is compressed, wherein, m is a natural number.

14. non-volatile memory semiconductor device according to claim 13 is characterized in that, also comprises:

Distribution compact token memory circuit, information is finished in the compression whether storage representation is finished based on the compression of the distribution number of above-mentioned data compression sequencing circuit;

Sensing circuit, finish information based on the above-mentioned compression that is stored in the distribution compact token memory circuit, use a plurality of decision level of reading successively, from many level readout mode of above-mentioned memory cell sense data with use 11 level readout mode of reading the decision level sense data and select any readout mode, from above-mentioned memory cell sense data.

15. non-volatile memory semiconductor device according to claim 14 is characterized in that, also comprises:

The decision level information of decision level memory circuit, the storage representation decision level during from above-mentioned memory cell sense data;

The power-up sequence control circuit when energized, makes above-mentioned compression finish information stores in above-mentioned distribution compact token memory circuit, and makes above-mentioned decision level information stores in above-mentioned decision level memory circuit.

16. non-volatile memory semiconductor device according to claim 14 is characterized in that:

Also comprise

Non-volatile distribution compact token zone is stored above-mentioned compression and is finished information;

Non-volatile decision level storage area is stored above-mentioned decision level information; And

The power-up sequence control circuit, above-mentioned data compression sequencing circuit has carried out compression to distribution number after, write the compression that is stored in above-mentioned distribution compact token zone to above-mentioned distribution compact token memory circuit and finish information, and the decision level information that will be stored in above-mentioned decision level storage area writes above-mentioned decision level memory circuit

Above-mentioned data compression sequencing circuit after having compressed distribution number, makes above-mentioned compression finish information stores in above-mentioned distribution compact token zone, and makes above-mentioned decision level information stores in above-mentioned decision level storage area.

17. non-volatile memory semiconductor device according to claim 1 is characterized in that, also comprises:

The power-up sequence control circuit by each storage unit is read action, selects to use the decision level of reading in data, with its as above-mentioned decision level information stores at above-mentioned decision level memory circuit.

18. non-volatile memory semiconductor device according to claim 17 is characterized in that:

Also comprise non-volatile use distributing position storage area, the threshold voltage distribution positional information of the position of its storage representation employed threshold voltage distribution in above-mentioned memory cell,

Above-mentioned power-up sequence control circuit makes the corresponding decision level information stores of the threshold voltage distribution positional information of being stored with above-mentioned use distributing position storage area in above-mentioned decision level memory circuit.

19. non-volatile memory semiconductor device according to claim 17 is characterized in that:

Also comprise the monitoring position, it has the structure identical with above-mentioned memory cell, stores identical data all the time,

Above-mentioned power-up sequence control circuit by reading from above-mentioned monitoring position, is specified the position of above-mentioned threshold voltage distribution, and the decision level information stores that will try to achieve according to specified position is in above-mentioned decision level memory circuit.

20. non-volatile memory semiconductor device according to claim 1 is characterized in that:

Also comprise the initialization order control circuit, this initialization order control circuit makes the threshold voltage distribution of using in the storage of data move to writing the opposite direction of fashionable moving direction with data, so that it is be stored in the data of each memory cell, corresponding successively or corresponding successively from the highest threshold voltage distribution from minimum threshold voltage distribution.

21. non-volatile memory semiconductor device according to claim 20 is characterized in that:

Comprise that also transition finish mark, it is illustrated under the situation of the threshold voltage distribution of having used spendable maximum voltage, has finished threshold voltage distribution moving to ascent direction.

22. non-volatile memory semiconductor device according to claim 20 is characterized in that:

Above-mentioned initialization order control circuit carries out above-mentioned initialization action in the input stand-by period of above-mentioned instruction on the backstage.

23. non-volatile memory semiconductor device according to claim 1 is characterized in that, also comprises:

Writing unit when the data that the above-mentioned memory cell of rewriting is stored, has respectively corresponding to respectively writing data, writes the 1st write-in functions that level writes as target with the 1st; With corresponding to respectively writing data, will with the above-mentioned the 1st write level different the 2nd write the 2nd write-in functions that level writes as target;

Write the level selected cell, each data is write select the above-mentioned the 1st to write level and above-mentioned the 2nd any one that writes in the level.

24. non-volatile memory semiconductor device according to claim 23 is characterized in that, also comprises:

Judgement unit is differentiated the data of utilizing above-mentioned the 1st write-in functions to be write;

Data are preserved the unit, preserve the data of being differentiated by above-mentioned judgement unit;

Long-term assuranceization writing unit uses above-mentioned data to preserve the data of preserving the unit and appends write activity.

25. non-volatile memory semiconductor device according to claim 23 is characterized in that:

Also comprise the write-in functions identification marking, after it was illustrated in and utilizes above-mentioned the 1st write-in functions to write data, the data that write were the data of utilizing above-mentioned the 1st write-in functions to be write.

26. non-volatile memory semiconductor device according to claim 24 is characterized in that:

Above-mentioned long-term assurance writing unit in the input stand-by period of above-mentioned instruction, carries out the above-mentioned write activity that appends on the backstage.

27. non-volatile memory semiconductor device according to claim 23 is characterized in that:

Also comprise the initialization order control circuit, this initialization order control circuit makes the threshold voltage distribution used in the storage of data move and carry out initialization to writing the opposite direction of fashionable moving direction with data, so that be stored in the data of each memory cell, corresponding successively from minimum threshold voltage distribution

Above-mentioned data set is made of 2 Value Datas.

28. non-volatile memory semiconductor device according to claim 27 is characterized in that:

Above-mentioned initialization order control circuit in the input stand-by period of above-mentioned instruction, carries out above-mentioned initialization action on the backstage.

29. non-volatile memory semiconductor device according to claim 1 is characterized in that:

Comprise also whether the data of representing above-mentioned memory cell are that wiping of erase status finished mark,

Above-mentioned programmed order control circuit is under the situation of erase status making above-mentioned memory cell, does not rewrite the data of above-mentioned memory cell, finishes mark so that above-mentioned wiping finished mark and represented that memory cell is an erase status and rewrite above-mentioned wiping.

30. non-volatile memory semiconductor device according to claim 29 is characterized in that:

Also comprise with sector location making memory cell be initialized as the initialization order control circuit of erase status,

Above-mentioned initialization order control circuit, when initialization, search erasing times minimum free sector, exchange be as the data of the minimum free sector of the sectors of data of initialization object and above-mentioned erasing times, and the minimum free sector of above-mentioned erasing times is carried out initialization.

31. non-volatile memory semiconductor device according to claim 30 is characterized in that:

Above-mentioned initialization order control circuit, when initialization, when having the minimum free sector of a plurality of above-mentioned erasing times, the position of the threshold voltage distribution of search most significant digit, the minimum sectors of data of exchange most significant digit threshold voltage distribution with need above-mentioned initialized sectors of data.

32. non-volatile memory semiconductor device according to claim 29 is characterized in that:

Above-mentioned initialization order control circuit, the position of the threshold voltage distribution of search most significant digit, exchange needs above-mentioned initialized sectors of data and the minimum sectors of data of most significant digit threshold voltage distribution, and initialization is carried out in the sector that above-mentioned most significant digit threshold voltage distribution is minimum.

33. non-volatile memory semiconductor device according to claim 32 is characterized in that:

Above-mentioned initialization order control circuit, when initialization, under the situation that has the minimum sector of a plurality of above-mentioned most significant digit threshold voltage distribution, search erasing times, minimum sectors of data of exchange erasing times and sectors of data as the initialization object.

34. non-volatile memory semiconductor device according to claim 1 is characterized in that:

The data address admin table that also comprises the zone in the above-mentioned memory cell array of storage representation,

Above-mentioned programmed order control circuit, fixing data by the represented zone of the information in the above-mentioned data address admin table of being stored in.

35. non-volatile memory semiconductor device according to claim 25 is characterized in that: