CN1971754B - Read-amplifier circuit of memorizer - Google Patents
Read-amplifier circuit of memorizer Download PDFInfo
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- CN1971754B CN1971754B CN2005101107878A CN200510110787A CN1971754B CN 1971754 B CN1971754 B CN 1971754B CN 2005101107878 A CN2005101107878 A CN 2005101107878A CN 200510110787 A CN200510110787 A CN 200510110787A CN 1971754 B CN1971754 B CN 1971754B
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- pipe
- sense amplifier
- amplifier circuit
- reading
- circuit
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Abstract
A sense amplifier circuit of memory is disclosed that includes: series switch tubes (N1) and reading gating switches (N2) connected with each other. The series switch tubes (N1) represent all series switch tubes playing a gating function. The invention is characterized in by comprising an accelerating circuit serial connected between the series switch tubes (N1) and the reading gating switches (N2) to adjust the discharge current and the reading velocity. The accelerating circuit contains a constant current source (Ibias) and two NMOS tubes (N4, N5). Because of using said technical project, that is to say, the accelerating circuit is serial connected between the N1 and N2 of the prior sense amplifier circuit, the invention has advantages of rapid sense amplifier speed, no relationship of reading time and the power voltage, simple structure, convenient adjustment of reading speed, low power consumption and so on.
Description
Technical field
The present invention relates to a kind of sense amplifier circuit of memorizer.
Technical background
In memory circuitry, generally need judge that the data that change the unit storage are " 1 " or " 0 " by the conducting or the disconnection that detect a path.The convenience of be describing, in the following description, we will be that example describes with the eeprom memory, to the storer of other type, except the implementation method of memory cell conducts and shutoff and criterion were different, crucial the reading mechanism of putting was identical.
The EEPROM storage unit is exactly a metal-oxide-semiconductor that is called floating gate structure, after drain terminal and grid end apply the program voltage of opposed polarity, the storage pipe will have different threshold values, the pipe that threshold value is high is considered to turn-off, data " 1 " have been represented, the pipe that threshold value is low is considered to conducting, and representative data " 0 " has so just reached and utilized the floating boom pipe to store the purpose of data.If high threshold pipe threshold value is V
Th, low threshold value pipe threshold value is V
TlDuring data in wanting readout memory, just can adopt simple sense amplifier circuit as shown in Figure 1.
Its principle of work is: voltage V
CGBe one between " 1 " pipe threshold V
Th" 0 " pipe threshold V
TlBetween the discharge of fixedly reading press and electric current I
ReadBe a fixed current source, generally be taken as 1/2nd of storage pipe EE_cell saturation current, N according to the design of " 0 " threshold size
1Play all tandem tap pipes of address strobe effect, N
2Be the read gate switch.N
1And N
2Breadth length ratio all design enough greatly.When EE storage pipe storage data are " 0 ", mean the pipe unlatching, and owing to read the discharge stream source less than the EE_cell saturation current, EE_cell, N1, N2 all are operated in linear zone, A point current potential is moved to closely, so sense amplifier circuit output low level signal " 0 ".And when EE storage pipe storage data be " 1 ", mean that pipe closes, so A point current potential is moved vdd to, sense amplifier circuit is exported high level signal " 1 ".
Although above-mentioned sense amplifier circuit can be realized simply reading playing function, there is following defective:
1. owing to the stray capacitance C that exists from storage tube EE_cell to the path of reading the discharge stream source as shown in Figure 1
P1, C
P2So, when reading " 1 ", read the discharge stream source and at first will charge stray capacitance, have only when stray capacitance to be charged to phase inverter I
1Threshold value (being generally vdd/2) time, the output of sense amplifier circuit just can be called the readout time of storer during this period of time from " 0 " upset for " 1 ".When memory span was multiplied, it is increasing that stray capacitance can become, and causes reading speed more and more slower.
2. and owing to read " 1 " to be charged to vdd/2 (threshold value of phase inverter is located at vdd/2 and has better anti-interference) to stray capacitance, cause reading speed also relevant with supply voltage vdd, supply voltage is high more, and reading speed is slow more, and this is to wish in the general circuit design to be avoided.
3. in A point voltage uphill process, arrive vdd-V
ThnIn the process of (threshold value of switch NMOS pipe), phase inverter I just
1Switching process in, I
1Bigger punchthrough current appears in middle meeting.
Summary of the invention
At the problem that above-mentioned simple sense amplifier circuit exists, the present invention proposes a kind of sense amplifier circuit of low-power consumption, has that to read the speed of putting fast, readout time and independent of power voltage, and simple in structure.
A kind of sense amplifier circuit of memorizer provided by the present invention, comprise continuous tandem tap pipe and read gate switch, the tandem tap pipe is represented the switching tube that plays the address strobe effect of all series connection, it is characterized in that: this sense amplifier circuit of memorizer comprises that also one seals in the accelerating circuit between described tandem tap pipe and read gate switch, is used for adjusting reading speed according to the requirement of physical circuit; This accelerating circuit comprises a constant current source, NMOS pipe and the 2nd NMOS pipe, wherein, constant current source connects the drain terminal of a NMOS pipe and the grid of the 2nd NMOS pipe respectively, and the grid of a NMOS pipe links to each other with the source end of the 2nd NMOS pipe, and NMOS pipe source end ground connection.
Owing to adopted above-mentioned technical solution, at the N of existing sense amplifier circuit
1And N
2Between seal in an accelerating circuit, have that to read the speed of putting fast, readout time and independent of power voltage, and simple in structure are read characteristics such as discharge stream, reading speed are easy to adjust, low-power consumption.
Description of drawings
Fig. 1 is the synoptic diagram of existing simple sense amplifier circuit;
Fig. 2 is the schematic diagram of sense amplifier circuit of the present invention.
Embodiment
As shown in Figure 2, sense amplifier circuit of memorizer of the present invention comprises two continuous all tandem tap pipe (N that play the address strobe effect
1) and read gate switch (N
2), be characterized in: it comprises that also one seals at described tandem tap pipe (N
1) and read gate switch (N
2) between accelerating circuit, be used for adjusting reading speed according to the requirement of physical circuit.
Accelerating circuit comprises a constant current source (I
Bias) and two NMOS pipe (N
4, N
5), wherein, constant current source (I
Bias) connect NMOS pipe (N respectively
4) drain terminal and NMOS pipe (N
5) grid, this NMOS pipe (N
4) grid and NMOS pipe (N
5) the source end link to each other and this NMOS pipe (N
4) source end ground connection.
Design feature of the present invention is, at the switching tube N of existing sense amplifier circuit
1With read gate switch N
2Between seal in one as the accelerating circuit shown in Fig. 2 frame of broken lines, I
BiasBe a constant current source, electric current and gate voltage equal certain given voltage V
B0(for convenience of description, might as well make V
b=1v).Its principle of work is briefly described as follows: when reading " 0 ", and memory cell conducts, the B point is in a current potential closely, so NMOS pipe N
4Close, C point current potential is pulled to vdd, so N5 opens fully, sense amplifier circuit is equivalent to short circuit, so its working condition and former sense amplifier circuit are just the same.And when reading " 1 ", B point current potential is low at the beginning, so N
5Still complete opening is read discharge stream to stray capacitance C
P1, C
P2Charging.When the B point is charged to specific voltage V
B0The time, this moment N4 saturation current big than Ibias, so C point current potential dragged down at once, thereby switching tube N
5Close, A point current potential is being read discharge stream source I
ReadEffect under rise to vdd rapidly, Dout also is turned to logic high " 1 " at once, has realized reading of " 1 ".
The sense amplifier circuit that uses the present invention to propose because read " 1 " as long as the time stray capacitance be charged to a relatively low voltage V
b(V
bValue can pass through I
BiasAdjust), shortened readout time; Simultaneously, because N
4Saturation current only depend on that gate voltage and vdd are irrelevant, so V
bThe influence that not changed by vdd also can not be subjected to the influence of power source change readout time; In addition, owing to being to suddenly change to vdd, so I by a low voltage at the readout A of whole " 1 " point
1In the punchthrough current that also can not occur continuing, read to put power consumption thereby also saved.
Though sense amplifier circuit of the present invention is described with reference to current instantiation, but those skilled in the art should be realized that, above example only is to be used for illustrating the present invention, also can make the variation and the modification of various equivalences under the situation that does not break away from spirit of the present invention.Therefore, if in connotation scope of the present invention to the variation of above-mentioned example, modification all will drop in the scope of claims of the present invention.
Claims (1)
1. a sense amplifier circuit of memorizer comprises continuous tandem tap pipe (N
1) and read gate switch (N
2), described tandem tap pipe (N
1) represent the switching tube that plays the address strobe effect of all series connection, it is characterized in that: this sense amplifier circuit of memorizer comprises that also one seals at described tandem tap pipe (N
1) and read gate switch (N
2) between accelerating circuit, be used for adjusting reading speed according to the requirement of physical circuit; Described accelerating circuit comprises a constant current source (I
Bias), a NMOS manages (N
4) and the 2nd NMOS pipe (N
5), wherein, described constant current source (I
Bias) connect NMOS pipe (N respectively
4) drain terminal and the 2nd NMOS pipe (N
5) grid, a NMOS manages (N
4) grid and the 2nd NMOS pipe (N
5) the source end link to each other and NMOS pipe (N
4) source end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101107878A CN1971754B (en) | 2005-11-25 | 2005-11-25 | Read-amplifier circuit of memorizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101107878A CN1971754B (en) | 2005-11-25 | 2005-11-25 | Read-amplifier circuit of memorizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1971754A CN1971754A (en) | 2007-05-30 |
| CN1971754B true CN1971754B (en) | 2011-05-25 |
Family
ID=38112509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005101107878A Active CN1971754B (en) | 2005-11-25 | 2005-11-25 | Read-amplifier circuit of memorizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1971754B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5191834B2 (en) * | 2008-08-12 | 2013-05-08 | セイコーインスツル株式会社 | Semiconductor nonvolatile memory device |
| CN102543199B (en) * | 2010-12-22 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | One time programmable (OTP) circuit |
-
2005
- 2005-11-25 CN CN2005101107878A patent/CN1971754B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN1971754A (en) | 2007-05-30 |
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Owner name: SHANGHAI HUAHONG INTEGRATED CIRCUIT CO., LTD. Free format text: FORMER OWNER: BEILING CO LTD, SHANGHAI Effective date: 20110519 |
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Free format text: CORRECT: ADDRESS; FROM: 200233 NO. 810, YISHAN ROAD, SHANGHAI TO: 201203 NO. 39, LANE 572, BIBO ROAD, ZHANGJIANG, SHANGHAI |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20110519 Address after: 201203 No. 572, Lane 39, blue wave road, Zhangjiang, Shanghai Applicant after: Shanghai Huahong Integrated Circuit Co., Ltd. Address before: 200233 No. 810, Shanghai, Yishan Road Applicant before: Beiling Co., Ltd., Shanghai |
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| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG INTEGRATED CIRCUIT CO., LTD. Free format text: FORMER OWNER: BEILING CO LTD, SHANGHAI Effective date: 20110701 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 200233 NO. 810, YISHAN ROAD, SHANGHAI TO: 201203 NO. 39, LANE 572, BIBO ROAD, ZHANGJIANG, SHANGHAI |
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| TR01 | Transfer of patent right |
Effective date of registration: 20110701 Address after: 201203 No. 572, Lane 39, blue wave road, Zhangjiang, Shanghai Patentee after: Shanghai Huahong Integrated Circuit Co., Ltd. Address before: 200233 No. 810, Shanghai, Yishan Road Patentee before: Beiling Co., Ltd., Shanghai |