CN1965398A - Heterojunction bipolar transistor - Google Patents
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- CN1965398A CN1965398A CN 200580000417 CN200580000417A CN1965398A CN 1965398 A CN1965398 A CN 1965398A CN 200580000417 CN200580000417 CN 200580000417 CN 200580000417 A CN200580000417 A CN 200580000417A CN 1965398 A CN1965398 A CN 1965398A
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Abstract
An n-type InP sub collector layer 2 heavily doped with silicon (Si), an InP collector layer 3, a p-type GaAs(0.51)Sb(0.49) base layer 4 heavily doped with carbon (C), an n-type In(1-y)Al(y)P emitter layer 7 doped with Si, an n-type InP cap layer 8 heavily doped with Si, and an n-type In(0.53)Ga(0.47). As contact layer 9 heavily doped with Si are stacked on a substrate 1.
Description
Technical field
The present invention relates to a kind of heterojunction bipolar transistor with the base stage that constitutes by GaAsSb.
Background technology
As a kind of compound semiconductor of the base layer material that is used as InP base heterojunction structure bipolar transistor (HBT), GaAsSb is attracting people's attention.GaAsSb is by mixture GaAs
(0.51)Sb
(0.49)Mate with the InP substrate lattice.Use the InP/GaAs of GaAsSb as base stage
(0.51)Sb
(0.49)/ InP base HBT can realize good high frequency characteristics and high-breakdown-voltage characteristic (list of references 1: " 300 GHz InP/GaAsSb/InP Double HBTs with HighCurrent Capability and BVceo 〉=6V " simultaneously, M.W.Dvorak, Student Member, IEEE, C.R.Bolognesi, Member, IEEE, O.J.Pitts, and S.P.Watkins, Member, IEEE: IEEE ELECTRON DEVICE LETTERS, VOL.22, NO.8, AUGUST 2001 are p.361).Heterostructure comprises I type heterostructure and II type heterostructure, in I type heterostructure, and the conduction band E of semiconductor A
CAWith valence band E
VAAnd the conduction band E of semiconductor B
CBWith valence band E
VBPotential energy (energy potential) by " E
CA＞E
CB" and " E
VA＞E
VB" expression, as shown in figure 14; And in II type heterostructure, E
CA＜E
CB" and " E
VA＜E
VB", as shown in figure 15.Above-mentioned heterojunction bipolar transistor is made of II type heterostructure.
Work as GaAs
(0.51)Sb
(0.49)When the base stage, the potential energy of its conduction band edge becomes the potential energy that is higher than conduction band edge in the InP collector layer, and this has eliminated the current blocking effect in the collector electrode, and this is a problem in InGaAs/InP base HBT.Therefore, as mentioned above, can obtain good high frequency characteristics and high-breakdown-voltage characteristic simultaneously.In addition, when GaAsSb is applied to base layer, carbon atom that can the little diffusion coefficient of high-concentration dopant, and this is favourable for reducing the base stage dead resistance.
Even when InGaAs is applied to base layer, also can uses carbon atom as p type alloy, but be difficult to reach 5 * 10
19Cm
-3Or higher ultrahigh concentration mixes.To point out that also when will be by metal-organic chemical vapor deposition equipment (MOCVD) (this is a kind of common growing method) when forming the InGaAs layer, carbon be subjected to main by the hydrogen atom passivation.This passivation that hydrogen is led carbon is not only owing to increased base layer resistance and the deterioration of device performance, and (burn-in) effect that causes wearing out, since this effect, the resistance value fluctuation, because the ratio of being led by the carbon of hydrogen passivation changes, go back the reliability of deterioration of device thus when applying electric current.GaAsSb has very high resistance for this hydrogen passivation.
Unfortunately, InP/GaAsSb/InP base HBT still has an open question still.Problem is because the excessive accumulation that the discontinuous emitter that causes of emitter/base conduction band edge injects electronics, and the emitter junction electric capacity that brings thus increases.In the conduction band edge of the heterostructure of InP emitter layer and GaAsSb base layer, shown in the energy band diagram of Figure 16, the potential energy of the base layer that is made of p type GaAsSb is higher than the potential energy of the emitter layer that is made of InP.This can be with discontinuous may cause electronics in the emitter space charge region excessively the accumulation.In addition, provide high electric current, local potential energy drop then near the conduction band edge at emitter/base interface, occurs, and this further increases electron accumulation if increase forward voltage.Any one all is equivalent to capacitive element with respect to device operation in these problems, and hinders the high speed operation of device.These problems have also increased the tunnelling recombination current by the defect state (defectlevel) of emitter/base near interface, have reduced current gain thus.
In order to address these problems, in InP/GaAsSb base HBT structure, must reduce the discontinuity (Δ Ec) of emitter/base conduction band edge, and inverse relation (potential energy in the conduction band edge of the potential energy＞base stage in the conduction band edge of emitter).As this method, following two kinds of trials have been carried out.
(1) make the potential energy in the conduction band edge of base layer be lower than GaAs
(0.51)Sb
(0.49)Conduction band edge in potential energy.
(2) use such material, this material is higher than as the potential energy in the conduction band edge of the InP of emitter layer the potential energy in the conduction band edge.
By making GaAs
(x)Sb
(1-x)The content x of As is greater than 0.51 in the base layer, and (for example, list of references 2: Japanese Patent Laid Open Publication No.2002-270616) can to realize said method (1).Basically only just can easily realize this method, but elongation strain occur, because the lattice constant of GaAsSb becomes the lattice constant less than InP by the formation condition that changes the GaAsSb mould.Therefore, when increasing As content, the critical film thickness of the GaAsSb layer (thickness that surpasses the accumulation restriction of stress, for example, coefficient of elasticity according to lattice mismatch between substrate and the grown layer and grown layer material obtains) reduce, if surpass critical film thickness, will in the GaAsSb layer, form fine crack.This has limited the increase of As content, and makes and can not reduce Δ Ec well.Equally, when will be by metal-organic chemical vapor deposition equipment (MOCVD) when forming hierarchy, the increase of above-mentioned tensile stress have brought new problem: the hydrogen passivation resistance that the carbon among the GaAsSb that carbon mixes is led reduces greatly.
Said method (2) will use the In with the InP lattice match
(0.52)Al
(0.48)(for example, list of references 3: Japanese Patent Laid Open Publication No.2002-270615) for As.Yet in this material system, it is 0.48 so big that Al content has, therefore to the resistance of autoxidation much smaller than InP.Except the low problem of the n type doping efficiency of InAlAs layer, this material system has also brought such problem: charge carrier has been easy to be doped fluorine (F) passivation among the InAlAs of Si (usually as n type alloy).In addition, in the time will forming the film that comprises numerous Al, must increase growth temperature usually, so that obtain the film (when carrying out crystal growth by metal-organic chemical vapor deposition equipment, temperature is generally 600 ℃ or higher) of high-crystal quality by crystal growth.This increased and the growth temperature (being approximately 500 ℃ under the same conditions) of base layer between temperature contrast, worsened the crystal mass in base layer and base stage/collector electrode cross section thus.In addition, described in list of references 2, be difficult to obtain satisfied InAlAs/GaAsSb interface.
Make the present invention and solved the problems referred to above, and the objective of the invention is to allow to use GaAsSb as the heterojunction bipolar transistor of base stage for example by reducing the capacitive element of emitter/base near interface, suppress current gain decline and increase service speed, suppress the problem such as impurity passivation and interface deterioration in the manufacture process simultaneously.
Summary of the invention
Basically, heterojunction bipolar transistor according to the present invention has such structure as the heterojunction bipolar transistor structure of using the GaAsSb sill as base layer: have the layer that at least one is made of the material that comprises In, Al and P in emitter layer.The composition device that forms the compound semiconductor of base layer comprises Ga, As and Sb at least, and the composition device of the compound semiconductor of formation emitter layer comprises In, Al and P at least.As a result, can improve the potential energy of emitter layer in the conduction band edge at the interface between emitter layer and the base layer.
In addition, heterojunction bipolar transistor according to the present invention comprises at least: the substrate that is made of InP; The collector layer that on described substrate, forms and constitute by the compound semiconductor that comprises indium and phosphorus; The base layer that on described collector layer, forms and constitute by the p type compound semiconductor that comprises gallium, arsenic and antimony; And the emitter layer that on described base layer, forms and constitute by the n type compound semiconductor that comprises indium, aluminium and phosphorus, the component ratio of indium and aluminium is in following scope in the wherein said emitter layer: in this scope, the potential energy of described emitter layer in the conduction band edge of described base layer one side is equal to or higher than the potential energy in the conduction band edge of described base layer.
In above-mentioned heterojunction bipolar transistor, in described base layer, use a GaAs at least
(x)Sb
(1-x)Layer uses at least one In in described emitter layer
(1-y)Al
(y)The P layer, and x and y represent the mixed crystal composition, and drop on respectively in the scope of 0＜x＜1 and 0＜y＜1.In addition, the scope of composition x is 0.2≤x≤0.8 preferably, and the scope of composition y 0＜y≤0.5 preferably.Relation between x and the y is 0.49x+1.554y 〉=0.25.In addition, the scope of composition x and y preferably is respectively 0.45≤x≤0.55 and 0＜y≤0.25, and 0.49x+1.554y 〉=0.36 preferably of the relation between x and the y.
In above-mentioned heterojunction bipolar transistor, the component ratio of Al can also be the gradual change composition in the described emitter layer, that is, can also reduce along the direction of leaving described base layer.Similarly, the component ratio of As can also be the gradual change composition in the described base layer, that is, can also reduce along the direction of leaving described base layer.
In above-mentioned heterojunction bipolar transistor, described collector layer can also be made of the compound semiconductor that comprises indium, aluminium and phosphorus.In this case, described base layer is by GaAs
(x)Sb
(1-x)Constitute, described collector layer is by In
(1-z)Al
(z)P constitutes, and x and z represent the mixed crystal composition, and preferably drop on 0＜x respectively＜1 and the scope of 0＜z＜1 in.In addition, the scope of composition z is 0＜z≤0.18 preferably, and the relation between composition x and the z is 0.49x+1.554y≤0.36.In addition, the component ratio of Al can also be the gradual change composition in the described collector layer, that is, can also reduce along the direction of leaving described base layer.
Note, in above-mentioned heterojunction bipolar transistor, preferably utilize metal-organic chemical vapor deposition equipment to form each layer, and preferably to described base layer doping carbon as alloy.Be also noted that if form base layer with 480 ℃ or higher growth temperature, then the ratio of being led by the carbon of hydrogen passivation drops to 15% or lower.
In aforesaid the present invention, in using the heterojunction bipolar transistor of GaAsSb sill as base layer, emitter layer is made of the compound semiconductor that comprises indium, aluminium and phosphorus, and emitter/base Δ Ec therefore can reduce or reverse.This is for example by reducing base-emitter electric capacity and increasing current gain, and do not reduce resistance and the device reliability of GaAsSb to hydrogen, obtained to allow to use GaAsSb to suppress the remarkable result that current gain descends and increases service speed as the heterojunction bipolar transistor of base stage.
Description of drawings
Fig. 1 shows the schematic sectional view according to the layout example of the heterojunction bipolar transistor of the embodiment of the invention;
Fig. 2 is the figure on 4 the band rank (band lineup) from emitter layer 7 to base layer;
Fig. 3 relatively uses In with the form of gummel figure
(0.85)Al
(0.15)The base current I of the heterojunction bipolar transistor of P emitter layer
BChart with the base current of the heterojunction bipolar transistor that uses the InP emitter layer;
Fig. 4 is used for explaining by In of the present invention
(1-y)Al
(y)P/GaAs
(x)Sb
(1-x)In the chart of the effective range of the present invention that obtained of composition x and y;
Fig. 5 A shows the sectional view according to the layout example of another heterojunction bipolar transistor of the embodiment of the invention;
Fig. 5 B shows the vertical view according to the layout example of the heterojunction bipolar transistor among Fig. 5 A of the embodiment of the invention;
Fig. 6 relatively uses by In
(0.85)Al
(0.15)The gummel figure of the heterojunction bipolar transistor of the emitter layer that P constitutes and the chart of the gummel figure of the heterojunction bipolar transistor that uses the emitter layer that constitutes by InP;
Fig. 7 shows the chart of collector current Ic-current gain characteristic;
Fig. 8 shows the sectional view according to the layout example of another heterojunction bipolar transistor of the embodiment of the invention;
Fig. 9 is the chart of gummel figure and the gummel figure of the heterojunction bipolar transistor that uses the emitter layer that is made of InP that relatively uses the heterojunction bipolar transistor of the emitter layer that is made of InAlP;
Figure 10 shows the chart of the current gain characteristic of heterojunction bipolar transistor shown in Figure 8;
Figure 11 shows the sectional view according to the layout example of another heterojunction bipolar transistor of the embodiment of the invention;
Figure 12 is the schematic diagram when the band rank from the base layer to the collector layer when GaAsSb/InP forms the boundary layer that mainly comprises InSb at the interface;
Figure 13 is the schematic diagram on band rank from the base layer to the collector layer in heterojunction bipolar transistor shown in Figure 11;
Figure 14 is the schematic diagram on the I type band rank that are made of two types semiconductor;
Figure 15 is the schematic diagram on the II type band rank that are made of two types semiconductor;
Figure 16 is the schematic diagram on the band rank in the heterostructure of InP emitter layer and GaAsSb base layer.
Embodiment
Embodiments of the invention are described below with reference to the accompanying drawings.
Fig. 1 shows the schematic section according to the layout example of the heterojunction bipolar transistor of the embodiment of the invention.In this heterojunction bipolar transistor shown in Figure 1, heavy doping the secondary collector layer 2 of n type InP of silicon (Si), InP collector layer 3, heavy doping the p type GaAs of carbon (C)
(0.51)Sb
(0.49)The n type In of base layer 4, the Si that mixed
(1-y)Al
(y)P emitter layer 7, heavy doping the n type InP block layer 8 of Si and heavy doping the n type In of Si
(0.53)Ga
(0.47)As contact layer 9 is stacked on the InP substrate 1, and wherein substrate 1 has been owing to the iron that mixed (Fe) has increased resistance as impurity, and has (100) first type surface.
In addition, in secondary collector layer 2, do not form and form ohmic contact collector electrode 6 on the zone of collector layer 3, in base layer 4, do not form and form ohmic contact base electrode 5 on the zone of emitter layer 7, and on contact layer 9, form ohmic contact emitter electrode 10.
Secondary collector layer 2 concentration of for example having mixed is 2 * 10
19Cm
-3Si, base layer 4 concentration of for example having mixed is 1.1 * 10
20Cm
-3C, emitter layer 7 concentration of for example having mixed is 5 * 10
17Cm
-3Si, block layer 8 concentration of for example having mixed is 2 * 10
19Cm
-3Si, and contact layer 9 concentration of for example having mixed is 3 * 10
19Cm
-3Si.
Note,, omitted the details of the structure of heterojunction bipolar transistor shown in Figure 1 as long as do not hinder explanation.Be also noted that, alloy of each layer and composition material be not limited to above-mentioned these, can also use other materials, as long as can realize the device operation be scheduled to.For example, Sn rather than Si can be used, and Zn or Be rather than C (carbon) can be used as p type alloy as n type alloy.
Below simplicity of explanation is made the example of the method for heterojunction bipolar transistor shown in Figure 1.At first, by the known crystal technique (device) such as MBE (molecular beam epitaxy) or MOCVD (metal-organic chemical vapor deposition equipment), obtain to have formed successively on the substrate 1 structure of (piling up) above-claimed cpd semiconductor layer.Then, by known photoetching technique and lithographic technique, form mesa structure shown in Figure 1.Then by photoetching, be formed on electrode and form the mask pattern that has the hole in the part, and on this mask pattern depositing Ti/Pt/Au.After this, remove (throwing off) mask pattern, to form base electrode 5, collector electrode 6 and emitter electrode 10.
In the heterojunction bipolar transistor shown in Figure 1 that as above forms, emitter layer 7 is by In
(1-y)Al
(y)P (y＞0) constitutes.Therefore, shown in the energy band diagram of Fig. 2, in conduction band edge, the potential energy of the emitter layer at the interface 7 between emitter layer 7 and base layer 4 is higher than the potential energy of base layer 4.On the contrary, in the band rank (band lineup) of the emitter/base near interface of traditional InP/GaAsSb based transistor, as shown in figure 16, the potential energy in the InP emitter one side conduction band edge is lower than GaAsSb base stage one side.
In heterojunction bipolar transistor shown in Figure 1, this species diversity has been eliminated the potential barrier of the emitter/base near interface existence of traditional devices.As a result, in heterojunction bipolar transistor shown in Figure 1, suppressed the electron accumulation of emitter/base near interface, and this has reduced base-emitter electric capacity.Simultaneously, the difference between the valence band of the conduction band of emitter layer 7 one sides and base layer 4 one sides increases, so emitter/base tunnelling recombination current at the interface reduces.As the result of these effects, the current gain of heterojunction bipolar transistor shown in Figure 1 becomes the gain greater than traditional devices.
As shown in Figure 3, with the expression traditional devices (emitter is made of InP) dotted line compare, when emitter layer by In
(0.85)Al
(0.15)Characteristic was improved greatly when P constituted, and shown in solid line, but Al content is low, is 15%.Notice that Fig. 3 has compared use by In with the form of gummel figure
(0.85)Al
(0.15)The base current I of the heterojunction bipolar transistor of the emitter layer that P constitutes
BBase current with the heterojunction bipolar transistor that uses the emitter layer that constitutes by InP.
To explain the composition of the InAlP that forms emitter layer and the composition that forms the GaAsSb of base layer below.In the explanation below, will be from following (a) and (b), (c) and (d) represented viewpoint, describe being used for more effectively obtaining the composition of above-mentioned characteristic.
(a) owing to making composition depart from relation between the thickness that critical film thickness reduces and device property is required that lattice match point causes.
(b) reduce the combination of the composition of Δ Ec.
(c) hydrogen passivation resistance and the strain relation of GaAsSb.
(d) reducing of the critical film thickness that causes owing to the interaction between the layer that strain takes place, and the generation of defective in the interface.
To explain viewpoint (a) at first, below.Since the mismatch of lattice constant, the GaAs that forms on the InP substrate
(x)Sb
(1-x)O'clock experience elongation strain in 0.51＜x≤1, and some experience compression strain in 0≤x＜0.5.Equally, if y＞0, In
(1-y)Al
(y)P just experiences elongation strain.The thickness that can not make the layer that strain takes place usually is greater than critical film thickness.On the other hand, owing to following reason, can not unrestrictedly make each layer attenuate.At GaAs
(x)Sb
(1-x)In the base layer, if doping carbon, the doping content that then can not worsen crystal mass is up to about 4 * 10
20Cm
3Therefore, when reducing base resistance when increasing the speed of heterojunction bipolar transistor, for example, when base resistance is 600 Ω/(cm
2) time, thickness approximately is 15nm.
Equally, as attenuate In
(1-y)Al
(y)During the P emitter layer, its band curvature becomes precipitous.Therefore, In
(1-y)Al
(y)The conduction band of P layer is near the valence band edge and the emitter/base interface of GaAsSb base layer, and the increase of tunnelling recombination current becomes serious.Therefore, still attenuate In unrestrictedly
(1-y)Al
(y)The P emitter layer.As mentioned above, by GaAs
(x)Sb
(1-x)The base layer that constitutes and by In
(1-y)Al
(y)The formed thickness of emitter layer that P constitutes all must be equal to or less than critical film thickness, and device property can not worsen thus.As the condition that satisfies this requirement, the scope of composition x and y can only be respectively 0.2≤x≤0.8 and 0＜y≤0.5.
Then, will explain viewpoint (b) below.In order to obtain aforementioned effect of the present invention, Δ Ec must be less than GaAs
(0.51)Sb
(0.49)Δ Ec in the/InP situation.Utilize composition x and y, can estimate the potential energy and the GaAs of the conduction band of InP
(x)Sb
(1-x)And In
(1-y)Al
(y)Difference between the potential energy of the conduction band of P.Because GaAs
(0.51)Sb
(0.49)The Δ Ec of/InP is estimated as about 0.18eV, so Δ Ec is that 0.18eV or littler condition are 0.49x+1.554y 〉=0.25 on the basis of composition x and y.
Except above-mentioned viewpoint (a) with (b), in order to obtain effect of the present invention, especially wish service condition (0.49x+1.554y 〉=0.36), under this condition, Δ Ec near 0 or the conduction band potential energy of emitter layer one side higher.Under this condition, below will be and (d) come further research can not cause the composition range of adverse effect to the high speed operation of heterojunction bipolar transistor from viewpoint (c).
At first explain viewpoint (c).If As content x is x 〉=0.51, then GaAs
(x)Sb
(1-x)The elongation strain of layer experience, and hydrogen passivation resistance reduces.When be subjected to the main GaAs that mixes with carbon by the carbon of hydrogen passivation
(x)Sb
(1-x)The ratio that all carbon that exist in the layer are led is approximately 5% or more hour, in fact the hydrogen passivation can ignore.As GaAs
(x)Sb
(1-x)The composition of layer, the allowed band of this condition is x＜0.55.This is the GaAs that the angle from hydrogen passivation resistance obtains
(x)Sb
(1-x)The upper limit of the composition of layer.
Then, will explain viewpoint (d).At first, in the scope of 0≤x＜0.51, when x reduces, In
(1-y)Al
(y)P/GaAs
(x)Sb
(1-x)Δ Ec increase because the potential energy of the conduction band of GaAsSb rises.This can compensate by increasing y.In this state, GaAs
(x)Sb
(1-x)Compression strain and In in the layer
(1-y)Al
(y)The interaction of the elongation strain in the P layer makes critical film thickness less than the critical film thickness on the InP substrate, and has increased emitter/base defect concentration at the interface.This is the GaAs that obtains from the interactional angle between the layer that strain takes place
(x)Sb
(1-x)The lower limit and the In of the composition of layer
(1-y)Al
(y)The upper limit of the composition of P layer.
Fig. 4 shows together from above-mentioned viewpoint (a) and (b), (c) and the condition that (d) obtains.As shown in Figure 4, zone 401 represented condition and ranges are zones that effect of the present invention obviously manifests.Zone 402 is the zones that obtain effect of the present invention.Zone 403 is zones of the discontinuity (Δ Ec) of the emitter/base conduction band edge Δ Ec when becoming greater than emitter by InP.Zone 404 is the zones that can not design the device (heterojunction bipolar transistor) with practicable thickness because the strain of formed film is serious.
As the influence that further reduces strain and improve the method for the conduction band potential energy of emitter layer one side, can also use composition gradual change (compositionally-graded) layer, wherein In
(1-y)Al
(y)The Al content of P emitter layer reduces (base layer one side) along the direction of leaving the base-emitter knot, so that InAlP is near InP.
On the other hand, can also reduce As content in the GaAsSb base layer along the direction of leaving emitter layer one side.In this case, the potential energy of conduction band edge reduces with respect to emitter layer in the base layer, and has quickened the minority carrier in the base layer by the internal electric field that this inclination produced.This makes has further increased the probability of recombination that can reduce minority carrier in the base layer current gain, and has increased the service speed of device.
Below with reference to Fig. 5 A and 5B another heterojunction bipolar transistor according to the embodiment of the invention is described.Fig. 5 A shows the sectional view according to the layout example of other heterojunction bipolar transistors of the embodiment of the invention, and Fig. 5 B is a vertical view.In this heterojunction bipolar transistor shown in Fig. 5 A and the 5B, heavy doping the secondary collector layer 502 of n type InP of silicon (Si), InP collector layer 503, heavy doping the p type GaAs of carbon (C)
(0.51)Sb
(0.49)The n type In of base layer 504, the Si that mixed
(0.85)Al
(0.15) P emitter layer 507, heavy doping the n type InP block layer 508 of Si and heavy doping the n type In of Si
(0.53)Ga
(0.47)As contact layer 509 is stacked on the InP substrate 501, and wherein substrate 501 has been owing to the iron that mixed (Fe) has increased resistance as impurity, and has (100) first type surface.
In addition, in secondary collector layer 502, do not form and form ohmic contact collector electrode 506 on the zone of collector layer 503, in base layer 504, do not form and form ohmic contact base electrode 505 on the zone of emitter layer 507, and on contact layer 509, form ohmic contact emitter electrode 510.
Note,, omitted the details of the structure of the heterojunction bipolar transistor shown in Fig. 5 A and the 5B as long as do not hinder explanation.Be also noted that, alloy of each layer and composition material be not limited to above-mentioned these, can also use other materials, as long as can realize the device operation be scheduled to.
Below with the example of the method for the heterojunction bipolar transistor shown in simplicity of explanation shop drawings 5A and the 5B.At first, by the known crystal technique (device) such as MBE or MOCVD, obtain to have formed successively on the substrate 501 structure of (piling up) above-claimed cpd semiconductor layer.Especially when utilizing MOCVD to form each layer from base layer 504 beginnings, the underlayer temperature during film forms wishes it is 480 ℃, so that minimize the passivation that hydrogen is led C.Notice that if suppressed the passivation that C is led in the base layer 504, for example, if utilize MBE to form each layer that begins from base layer 504 utilizing MOCVD to form, then underlayer temperature is opened and can be lower than above-mentioned value until each layer of collector layer 503 after.
Then, by known photoetching technique and lithographic technique, form the mesa structure shown in Fig. 5 A.When forming this mesa structure, only otherwise break away from the spirit and scope of the present invention, during etching process, can also use etching barrier layer and so on to obtain high selectivity.
Then by photoetching, be formed on electrode and form the mask pattern that has the hole in the part, and on this mask pattern depositing Ti/Pt/Au.After this, remove (throwing off) mask pattern, to form base electrode 505, collector electrode 506 and emitter electrode 510.The stepped construction of these electrodes can also be made of other materials, perhaps can take different shapes, needs only the ohmic contact that can obtain in each electrode with lower floor.
In Fig. 5 A that as above forms and the heterojunction bipolar transistor shown in the 5B, emitter layer 507 is made of InAlP.Therefore, with the same in the heterojunction bipolar transistor shown in Figure 1, in conduction band edge, the potential energy of the emitter layer at the interface 507 between emitter layer 507 and base layer 504 is higher than the potential energy of base layer 504.In the heterojunction bipolar transistor shown in Fig. 5 A and the 5B, the potential barrier that this emitter/base near interface of having eliminated traditional devices exists.
As a result, in the heterojunction bipolar transistor shown in Fig. 5 A and the 5B, suppressed the electron accumulation of emitter/base near interface, and this has reduced base-emitter electric capacity.Simultaneously, the difference between the valence band of the conduction band of emitter layer 507 1 sides and base layer 504 1 sides increases, so emitter/base tunnelling recombination current at the interface reduces.As the result of these effects, the current gain of Fig. 5 A and the heterojunction bipolar transistor shown in the 5B is compared with the gain of traditional devices also and is increased.
As shown in Figure 6, compare with the dotted line of expression traditional devices (emitter is made of InP), characteristic is improved greatly when emitter layer is made of InAlP, and shown in solid line, but Al content is reduced to 15%.Notice that Fig. 6 has compared use by In with the form of gummel figure
(0.85)Al
(0.15)The base current I of the heterojunction bipolar transistor of the emitter layer that P constitutes
BBase current with the heterojunction bipolar transistor that uses the emitter layer that constitutes by InP.
In addition, as shown in Figure 7, in the heterojunction bipolar transistor shown in Fig. 5 A and the 5B, compare as the traditional devices of emitter with using InP, the current gain overall improvement, and the characteristic of heterojunction bipolar transistor is improved greatly.Notice that Fig. 7 shows collector current Ic-current gain characteristic.
Below with reference to Fig. 8 description another heterojunction bipolar transistor according to the embodiment of the invention.Fig. 8 shows the sectional view according to the layout example of the heterojunction bipolar transistor of the embodiment of the invention.In this heterojunction bipolar transistor shown in Figure 8, heavy doping the secondary collector layer 802 of n type InP of silicon (Si), InP collector layer 803, heavy doping the p type GaAs of carbon (C)
(0.51)Sb
(0.49)The n type InAlP emitter layer 807 (wherein the composition of In and Al changes at thickness direction) of base layer 804, the Si that mixed, heavy doping the n type InP block layer 808 of Si and heavy doping the n type In of Si
(0.53)Ga
(0.47)As contact layer 809 is stacked on the InP substrate 801, and wherein substrate 801 has been owing to the iron that mixed (Fe) has increased resistance as impurity, and has (100) first type surface.Emitter layer 807 is in gradual change composition state, and 808 the direction from base layer 804 towards block layer wherein, In component ratio change into 1.00 from 0.75, and the Al component ratio changes into 0 from 0.25, that is, In increases and Al reduces.
In addition, in secondary collector layer 802, do not form and form ohmic contact collector electrode 806 on the zone of collector layer 803, in base layer 804, do not form and form ohmic contact base electrode 805 on the zone of emitter layer 807, and on contact layer 809, form ohmic contact emitter electrode 810.
Secondary collector layer 802 concentration of for example having mixed is 2 * 10
19Cm
-3Si, base layer 804 concentration of for example having mixed is 7 * 10
19Cm
-3C, emitter layer 807 concentration of for example having mixed is 5 * 10
17Cm
-3Si, block layer 808 concentration of for example having mixed is 1 * 10
19Cm
-3Si, and contact layer 809 concentration of for example having mixed is 1.5 * 10
19Cm
-3Si.The thickness of collector layer 803, base layer 804 and emitter layer 807 is respectively about 180,20 and 30nm.
Note,, omitted the details of the structure of heterojunction bipolar transistor shown in Figure 8 as long as do not hinder explanation.Be also noted that, alloy of each layer and composition material be not limited to above-mentioned these, can also use other materials, as long as can realize the device operation be scheduled to.In addition, can make heterojunction bipolar transistor shown in Figure 8 in the mode identical with the heterojunction bipolar transistor shown in above-mentioned Fig. 1 and Fig. 5 A and the 5B.
In the heterojunction bipolar transistor shown in Figure 8 that as above forms, emitter layer 807 is made of InAlP.Therefore, with the same in the heterojunction bipolar transistor shown in Figure 1, in conduction band edge, the potential energy of the emitter layer at the interface 807 between emitter layer 807 and base layer 804 is higher than the potential energy of base layer 804.In heterojunction bipolar transistor shown in Figure 8, the potential barrier that this emitter/base near interface of having eliminated traditional devices exists.
As a result, in heterojunction bipolar transistor shown in Figure 8, suppressed the electron accumulation of emitter/base near interface, and this has reduced base-emitter electric capacity.Simultaneously, the difference between the valence band of the conduction band of emitter layer 807 1 sides and base layer 804 1 sides increases, so emitter/base tunnelling recombination current at the interface reduces.As the result of these effects, the current gain of heterojunction bipolar transistor shown in Figure 8 is compared with the gain of traditional devices also and is increased.
In addition, in heterojunction bipolar transistor shown in Figure 8, emitter layer 807 has the gradual change composition, that is, the Al component ratio with base layer 804 be high at the interface, and reduce towards the direction of block layer 808.This has alleviated the problem of the strain that is caused by high Al component ratio.
As shown in Figure 9, compare with the dotted line of expression traditional devices (emitter is made of InP), characteristic is improved greatly when emitter layer is made of above-mentioned InAlP with gradual change composition, shown in solid line.Equally, with have similar gradual change composition and be In at composition at the interface with base layer
(0.85)Al
(0.15)The emitter layer of P (dotted line that length replaces) is compared, and is clear that, when Al component ratio in the emitter layer rose in the zone near base layer, the recombination current component reduced in the low-pressure area.Notice that Fig. 9 has compared the base current I that uses the heterojunction bipolar transistor of the emitter layer that is made of InAlP with the form of gummel figure
BBase current with the heterojunction bipolar transistor that uses the emitter layer that constitutes by InP.
In addition, as shown in figure 10, in heterojunction bipolar transistor shown in Figure 8, compare as the traditional devices of emitter with using InP, the current gain overall improvement, and the characteristic of heterojunction bipolar transistor is improved greatly.In addition, in heterojunction bipolar transistor shown in Figure 8, current gain is higher than the current gain when the Al component ratio is low in the emitter layer near the zone of base layer.This may be because high Al component ratio has been added the effect that discharges electronics from emitter to base stage.As mentioned above, when using Al component ratio wherein near the zone of base layer, during for the emitter layer of high gradual change composition, can obtain the effect of more significant current gain increase.
Below with reference to Figure 11 description another heterojunction bipolar transistor according to the embodiment of the invention.Figure 11 shows the sectional view according to the layout example of the heterojunction bipolar transistor of the embodiment of the invention.In this heterojunction bipolar transistor shown in Figure 11, heavy doping the secondary collector layer 1102 of n type InP of silicon (Si), InP collector layer 1103, InAlP collector electrode composition graded bedding 1104, heavy doping the p type GaAs of carbon (C)
(0.51)Sb
(0.49)The n type InAlP emitter layer 1108 (wherein the composition of In and Al changes at thickness direction) of base layer 1105, the Si that mixed, heavy doping the n type InP block layer 1109 of Si and heavy doping the n type In of Si
(0.53)Ga
(0.47)As contact layer 1110 is stacked on the InP substrate 1101, and wherein substrate 1101 has been owing to the iron that mixed (Fe) has increased resistance as impurity, and has (100) first type surface.
Collector electrode composition graded bedding 1104 is in gradual change composition state, and 1105 the direction from collector layer 1103 towards base layer wherein, In component ratio change into 0.92 from 1.00, and the Al component ratio changes into 0.08 from 0, that is, In reduces and Al increases.Equally, emitter layer 1108 is in gradual change composition state, and 1109 the direction from base layer 1105 towards block layer wherein, In component ratio change into 1.00 from 0.75, and the Al component ratio changes into 0 from 0.25, that is, In increases and Al reduces.
In addition, in secondary collector layer 1102, do not form and form ohmic contact collector electrode 1107 on the zone of collector layer 1103, in base layer 1105, do not form and form ohmic contact base electrode 1106 on the zone of emitter layer 1108, and on contact layer 1110, form ohmic contact emitter electrode 1111.
Note,, omitted the details of the structure of heterojunction bipolar transistor shown in Figure 11 as long as do not hinder explanation.Be also noted that, alloy of each layer and composition material be not limited to above-mentioned these, can also use other materials, as long as can realize the device operation be scheduled to.In addition, can make heterojunction bipolar transistor shown in Figure 11 in the mode identical with above-mentioned Fig. 1, Fig. 5 A and 5B and heterojunction bipolar transistor shown in Figure 8.
In having the heterojunction bipolar transistor shown in Figure 11 of above-mentioned layout, emitter layer 1108 is made of InAlP.Therefore, with the same in the heterojunction bipolar transistor shown in above-mentioned Fig. 1,5A and 8, in conduction band edge, the potential energy of the emitter layer at the interface 1108 between emitter layer 1108 and base layer 1105 is higher than the potential energy of base layer 1105.In heterojunction bipolar transistor shown in Figure 11, the potential barrier that this emitter/base near interface of having eliminated traditional devices exists.
As a result, in heterojunction bipolar transistor shown in Figure 11, suppressed the electron accumulation of emitter/base near interface, and this has reduced base-emitter electric capacity.Simultaneously, the difference between the valence band of the conduction band of emitter layer 1,108 one sides and base layer 1,105 one sides increases, so emitter/base tunnelling recombination current at the interface reduces.As the result of these effects, the current gain of heterojunction bipolar transistor shown in Figure 11 is compared with the gain of traditional devices also and is increased.
In addition, in heterojunction bipolar transistor shown in Figure 11, emitter layer 1108 has the gradual change composition, that is, the Al component ratio with base layer 1105 be high at the interface, and reduce towards the direction of block layer 1109.This has alleviated the problem of the strain that is caused by high Al component ratio, therefore equally with heterojunction bipolar transistor shown in Figure 8 has obtained higher current gain.
In addition, in heterojunction bipolar transistor shown in Figure 11, with base stage 1105 contacted zones in the composition of collector electrode be InAlP.This makes and can solve the following problem in collector electrode/base stage boundary layer at the interface that will explain.
The fusing point that comprises the compound semiconductor of Sb only is lower than the fusing point of the compound semiconductor that is made of P and As other V group atoms.The example of the compound semiconductor that is made of two kinds of devices is GaSb (712 ℃) and InSb (525 ℃), and relative therewith GaP (1,467 ℃), InP (1,060 ℃), GaAs (1,240 ℃) and InAs (924 ℃).In addition, the general growth temperature range of GaAsSb is 500 ℃ to 600 ℃.On the other hand, because the fusing point of InSb is low, if the contact interface place between InP and GaAsSb forms InSb, then the InP/GaAsSb interface temporarily becomes near liquid phase (" Growth Monitoring of GaAsSb:C/InP Heterostructure with Reflectance AnisotropySpectroscopy ", F.Brunner and three others, TMS, Abstract of12th ICMOVPE, 2004, p.2).In this state, not sharply to switch between the layer, therefore forming the boundary layer at the interface, wherein the two-layer composition device of these both sides, interface mixes each other at random.If have this boundary layer every layer of etching optionally when forming device architecture, then etching can not be carried out rapidly or carry out unusually, and this makes and can not process designed device shape.
In addition, owing to produce strong strain in the part, this one deck has generated the transition defective, and increases or reduced potential energy near interface conduction band edge or the valence band edge in the part.For example, if form the boundary layer that mainly comprises InSb at the interface at GaAsSb/InP, then as shown in figure 12, local decline appears in conduction band edge.Therefore, the recombination current by defective increases, thereby reduces current gain, and the decline of conduction band edge or rise and hinder the electron-propagation of collector electrode to base stage, and the deterioration of device characteristic for example, reduces the service speed of device thus.
In order to address these problems, prevent that atom is normally important from another layer of course diffusion (for example, In is from the diffusion of InP course GaAsSb layer, and perhaps Sb is from the diffusion of GaAsSb course InP layer).Yet, in the situation of InP/GaAsSb based transistor, on the contact-making surface between InP and the GaAsSb, forming potential In-Sb key inevitably, therefore, only can not deal with problems fully by suppressing diffusion.Can also make the growth temperature of GaAsSb base layer be lower than the fusing point of InSb, even can prevent that also the interface from becoming liquid phase when forming the In-Sb key on the contact-making surface between collector layer that constitutes by InP and base layer (GaAsSb) thus.
Yet in this case, low-temperature epitaxy usually worsens the crystal mass of GaAsSb base layer.In addition, when utilizing MOCVD to make hierarchy, the hydrogen passivation resistance that carbon is led among the GaAsSb that the carbon mixes (list of references: " Suppression of hydrogenpassivation in carbon-doped GaAsSb grows by MOCVD " that descends greatly, Y.Oda andfive others, ELSEVIER, Journal of Crystal Growth, 2004, Vol.261, p. 393).
On the contrary, heterojunction bipolar transistor shown in Figure 11 comprises InAlP collector electrode composition graded bedding 1104 in the zone that will form base layer 1105, thereby forms base layer 1105 on this InAlP layer.As a result, can suppress forming of the boundary layer that constitutes by In and Sb.To explain the inhibition in boundary layer in more detail below.
As mentioned above, the compound semiconductor that comprises Sb has low melting point, and the compound semiconductor that comprises Al has high-melting-point.Example is AlP (distillation in the time of about 1,060 ℃), AlAs (1,740 ℃) and AlSb (1,080 ℃).In addition, the binding energy of atom increases with the order of Al-Sb＞Ga-Sb＞In-Sb, and the most stable in Al-Sb.Therefore, when the interface between compound semiconductor insertion collector layer that comprises aluminium and the base layer, perhaps work as collector layer by In
(1-z)Al
(z)When P constituted, Al-Sb key ratio formation In-Sb key was preferential forming at the interface.In this case, on the interface of collector electrode one side of base layer, form dystectic InAlSb rather than low-melting InSb, and this makes and can prevent that the interface from temporarily becoming liquid phase in the starting stage of growth GaAsSb.
Yet, not only have high-melting-point because comprise the compound semiconductor of Al, also in conduction band edge, have high potential energy, so if add Al indiscreetly, the potential energy in the conduction band edge of collector layer becomes the potential energy in the conduction band edge that is higher than base layer.This state is the potential barrier to the electronics of propagating in conduction band, has reduced the service speed of heterojunction bipolar transistor thus greatly.This problem also is the reason that is difficult to InAlAs is applied to collector layer, although comprise Al with the InAlAs of InP lattice match.
On the basis of Miao Shuing, will from viewpoint (i) extremely (iv) explain that being used for using effectively one-tenth of the present invention grades below in front:
(i) owing to making composition depart from relation between the thickness that critical film thickness reduces and device property is required that lattice match point causes.
(ii) hydrogen passivation resistance and the strain relation of GiAsSb.
(iii) reducing of the critical film thickness that causes owing to the interaction between the layer that strain takes place, and the generation of defective in the interface.
Relation when (iv) potential energy is (collector layer＜base layer) in the conduction band edge between the composition.
To explain viewpoint (i) at first, below.Since the mismatch of lattice constant, the GiAs that forms on the InP substrate
(x)Sb
(1-x)O'clock experience elongation strain in 0.51＜x≤1, and some experience compression strain in 0≤x＜0.5.Equally, if y＞0, In
(1-z)Al
(z)P just experiences elongation strain.The thickness that can not make the layer that strain takes place usually is greater than critical film thickness.On the other hand, owing to following reason, can not unrestrictedly make each layer attenuate.At GiAs
(x)Sb
(1-x)In the base layer, if doping carbon, the doping content that then can not worsen crystal mass is up to about 4 * 10
20Cm
3Therefore, when reducing base resistance when increasing the speed of heterojunction bipolar transistor, for example for 600 Ω/(cm
2) base resistance and 4 * 10
20Cm
3Doping content, thickness is necessary for about 15nm, and for 8 * 10
19Cm
3Doping content, thickness is necessary for about 35nm.Therefore, must be to GiAs
(x)Sb
(1-x)And In
(1-z)Al
(z)P forms thickness and is equal to or less than critical film thickness and film that can the deterioration of device characteristic.Specifically, from the viewpoint of critical film thickness, the concrete scope of x is 0.2≤x≤0.8, the processing leeway that this has considered base resistance and has caused owing to thickness fluctuation, and under this condition,, can not reach critical condition even thickness is 15nm yet.
Then, will explain viewpoint (ii).If As content x is x 〉=0.51, then GiAs
(x)Sb
(1-x)The elongation strain of layer experience, and hydrogen passivation resistance reduces.When be subjected to the main GiAs that mixes with carbon by the carbon of hydrogen passivation
(x)Sb
(1-x)The ratio that all carbon that exist in the layer are led is approximately 5% or more hour, in fact the hydrogen passivation can ignore.As GiAs
(x)Sb
(1-x)The composition of layer, the allowed band of this condition is x＜0.55.This is the GiAs that the angle from hydrogen passivation resistance obtains
(x)Sb
(1-x)The upper limit of the composition of layer.
To explain viewpoint (iii) below.At first, in the scope of 0≤x＜0.51, when x reduces, In
(1-z)Al
(z)P/GiAs
(x)Sb
(1-x)Δ Ec (conduction band edge discontinuity) increase because the potential energy of the conduction band of GiAsSb rises.In this case, can further increase z.In this state, GiAs
(x)Sb
(1-x)Compression strain and In in the layer
(1-z)Al
(z)The interaction of the elongation strain in the P layer makes critical film thickness less than the critical film thickness on the InP substrate, and has increased collector electrode/base stage defect concentration at the interface.This is the GiAs that obtains from the interactional angle between the layer that strain takes place
(x)Sb
(1-x)The lower limit and the In of the composition of layer
(1-z)Al
(z)The upper limit of the composition of P layer.
To explain viewpoint (iv) now.In order to prevent the device characteristic degradation, must keep potential energy in the conduction band of collector layer to be lower than potential energy in the conduction band of base layer.Utilize composition x and z, can estimate the potential energy and the GiAs of the conduction band of InP
(x)Sb
(1-x)And In
(1-z)Al
(z)Difference between the potential energy of the conduction band of P.Because GiAs
(0.51)Sb
(0.49)The Δ Ec of/InP is estimated as about 0.18eV, so the lower condition of potential energy in the conduction band edge of collector layer one side is 0.49x+1.554z≤0.36 on the basis of composition x and z.Because according to (i) to (iii) 0.45≤x≤0.55, so the possible range of y is 0＜z≤0.18.
Generally speaking, if base layer by GaAs
(x)Sb
(1-x)Constitute, the interface of collector layer one side of base layer is by In
(1-z)Al
(z)P constitutes, and the scope of composition x and z is respectively 0.45≤x≤0.55 and 0＜z≤0.18, and the relation between x and the z is 0.49x+1.554y≤0.36, then can eliminate the problem in boundary layer, as the method that reduces the strain influence, can also use the composition graded bedding, wherein In
(1-z)Al
(z)The Al content of P collector layer reduces (base layer one side) along the direction of leaving base junction plane (base layer one side), so that InAlP is near InP.
In above-mentioned heterojunction bipolar transistor shown in Figure 11, because formed collector electrode composition graded bedding 1104, so the composition at base stage/collector electrode interface suddenly changes.Therefore, shown in the energy band diagram of Figure 13, the part that has suppressed base stage/collector electrode near interface conduction band edge descends, and therefore can realize electronics is passed clog-free state.
In addition, if on the collector layer that constitutes by InP, form the base layer of supporting by GaAsSb, forming above-mentioned boundary layer at the interface.Carrying out wet chemical etch when forming structure shown in Figure 11, this may hinder from the selective etch of base layer to collector layer.If have the boundary layer at the interface at base stage/collector layer, no matter etching agent is used for base stage or collector electrode, and the etching behavior all changes near interface, and this makes and to be difficult to realize designed structure.
On the contrary, in the stepped construction of collector layer 1103, collector electrode composition graded bedding 1104 and base layer 1105, carrying out wet chemical etch when forming structure shown in Figure 11, do not form the boundary layer from base layer 1105 to collector electrode composition graded bedding 1104 and collector layer 1103, therefore can carry out selective etch smoothly.
Industrial applicibility
Above-mentioned the present invention can provide can high speed operation heterojunction bipolar transistor.
Claims (14)
1, a kind of heterojunction bipolar transistor is characterized in that, the composition device that forms the compound semiconductor of base layer comprises Ga, As and Sb at least, and the composition device of the compound semiconductor of formation emitter layer comprises In, Al and P at least.
2, heterojunction bipolar transistor according to claim 1 is characterized in that comprising:
The substrate that constitutes by InP;
The collector layer that on described substrate, forms and constitute by the compound semiconductor that comprises indium and phosphorus;
Described base layer is formed on the described collector layer, and is made of the p type compound semiconductor that comprises gallium, arsenic and antimony; And
Described emitter layer is formed on the described base layer, and is made of the n type compound semiconductor that comprises indium, aluminium and phosphorus,
The component ratio of indium and aluminium is in following scope in the wherein said emitter layer: in this scope, the potential energy of described emitter layer in the conduction band edge of described base layer one side is not less than the potential energy in the conduction band edge of described base layer.
3, heterojunction bipolar transistor according to claim 1 is characterized in that using at least a GaAs in described base layer
(x)Sb
(1-x)Layer uses at least one In in described emitter layer
(1-y)Al
(y)The P layer, and x and y represent the mixed crystal composition, and drop on respectively in the scope of 0＜x＜1 and 0＜y＜1.
4, heterojunction bipolar transistor according to claim 3, the scope that it is characterized in that composition x are 0.2≤x≤0.8, and the scope of composition y is 0＜y≤0.5.
5, heterojunction bipolar transistor according to claim 4 is characterized in that the relation between x and the y is 0.49x+1.554y 〉=0.25.
6, heterojunction bipolar transistor according to claim 5, the scope that it is characterized in that composition x and y are respectively 0.45≤x≤0.55 and 0＜y≤0.25, and the relation between x and the y is 0.49x+1.554y 〉=0.36.
7, heterojunction bipolar transistor according to claim 1 is characterized in that the component ratio of Al in the described emitter layer reduces along the direction of leaving described base layer.
8, heterojunction bipolar transistor according to claim 1 is characterized in that the component ratio of As in the described base layer reduces along the direction of leaving described emitter layer.
9, heterojunction bipolar transistor according to claim 1 is characterized in that described collector layer is made of the compound semiconductor that comprises indium, aluminium and phosphorus.
10, heterojunction bipolar transistor according to claim 9 is characterized in that
Described base layer is by GaAs
(x)Sb
(1-x)Constitute,
Described collector layer is by In
(1-z)Al
(z)P constitutes, and x and z represent the mixed crystal composition, and drops on respectively in the scope of 0＜x＜1 and 0＜z＜1.
11, heterojunction bipolar transistor according to claim 10 is characterized in that
The scope of composition y is 0＜y≤0.18, and
Relation between composition x and the y is 0.49x+1.554z≤0.36.
12, heterojunction bipolar transistor according to claim 9 is characterized in that the component ratio of Al in the described collector layer reduces along the direction of leaving described base layer.
13, heterojunction bipolar transistor according to claim 1 is characterized in that
Utilize metal-organic chemical vapor deposition equipment to form to comprise the described base layer that forms heterojunction bipolar transistor and each layer of emitter layer, and
To described base layer doping carbon as alloy.
14, heterojunction bipolar transistor according to claim 13 is characterized in that forming described base layer under 480 ℃ the growth temperature being not less than.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102246283B (en) * | 2008-10-21 | 2014-08-06 | 瑞萨电子株式会社 | Bipolar transistor |
| CN103999224A (en) * | 2011-11-16 | 2014-08-20 | 天工方案公司 | Devices and methods related to a barrier for metallization of a gallium based semiconductor |
| CN107482057A (en) * | 2017-06-29 | 2017-12-15 | 厦门市三安集成电路有限公司 | The cascode transistor of multiple epitaxial layer |
| CN113745324A (en) * | 2021-07-29 | 2021-12-03 | 西安电子科技大学 | Quasi-vertical structure radio frequency device and manufacturing method |
| CN115207089A (en) * | 2022-07-19 | 2022-10-18 | 江苏华兴激光科技有限公司 | Radio frequency chip epitaxial wafer |
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| US4935797A (en) * | 1988-10-31 | 1990-06-19 | International Business Machines Corporation | Heterojunction bipolar transistors |
| JP2003086602A (en) * | 2001-09-14 | 2003-03-20 | Nippon Telegr & Teleph Corp <Ntt> | Heterojunction bipolar transistor |
| JP2004214576A (en) * | 2003-01-09 | 2004-07-29 | Nippon Telegr & Teleph Corp <Ntt> | Hetero-bipolar transistor |
| JP2005086135A (en) * | 2003-09-11 | 2005-03-31 | Nippon Telegr & Teleph Corp <Ntt> | Epitaxial wafer for hetero bipolar transistor and its manufacturing method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102246283B (en) * | 2008-10-21 | 2014-08-06 | 瑞萨电子株式会社 | Bipolar transistor |
| CN103999224A (en) * | 2011-11-16 | 2014-08-20 | 天工方案公司 | Devices and methods related to a barrier for metallization of a gallium based semiconductor |
| CN107482057A (en) * | 2017-06-29 | 2017-12-15 | 厦门市三安集成电路有限公司 | The cascode transistor of multiple epitaxial layer |
| CN113745324A (en) * | 2021-07-29 | 2021-12-03 | 西安电子科技大学 | Quasi-vertical structure radio frequency device and manufacturing method |
| CN113745324B (en) * | 2021-07-29 | 2023-07-25 | 西安电子科技大学 | Radio frequency device with quasi-vertical structure and manufacturing method |
| CN115207089A (en) * | 2022-07-19 | 2022-10-18 | 江苏华兴激光科技有限公司 | Radio frequency chip epitaxial wafer |
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