CN1964199A - A method and device to realize low density parity check code - Google Patents

Abstract

The invention discloses a method for realizing a class of low-density parity-check codes, which is characterized in that the method includes the following steps: A. According to the preset code length, code rate and line weight, set the method for generating the parity-check matrix digital sequence; B, according to the digital sequence, adopt the mode of cyclic shift to construct the parity check matrix of low density parity check code (LDPC) code; C, utilize described parity check matrix, input data is transformed into LDPC codewords. The invention also discloses a low-density parity check code realization device, which comprises: a storage module, a check matrix generation module and a codeword generation module. The application of the present invention can reduce the storage space required for storing the parity check matrix.

Description

Method and device for implementing a class of low-density parity-check codes

technical field

The invention relates to the encoding and decoding technology of the digital communication system, in particular to a method and device for realizing a class of low-density parity check codes.

Background technique

Due to the influence of factors such as random noise and multipath fading in wireless transmission, various errors often occur in data transmission in communication systems, especially in digital multimedia broadcasting systems, where data volume is large, bandwidth is limited, and various bursts There is a lot of interference, which makes the reliability problem of data transmission more prominent.

Typically, channel coding is used to ensure reliable communication in noisy communication channels. Among the existing implementation methods, Low Density Parity Check Code (LDPC) is widely considered as one of the best error correction implementation methods. This is because the performance of a code can be measured by the degree close to the Shannon limit, while the LDPC code has low decoding complexity but has a performance close to the Shannon limit. The existing LDPC codes are briefly introduced below.

LDPC code is a kind of linear error correction code based on sparse parity check matrix H. The characteristic of the H matrix is that the element 0 in the matrix accounts for the vast majority, and the density of the element 1 is very low, which is the so-called low density. There are several basic concepts in LDPC codes:

The code length refers to the length of the output data obtained after the input data is encoded, that is, the length of the LDPC code word; the length of the check digit is the number of check equations, which refers to the bits occupied by the check digit in the output data number, that is, the code length minus the information bit length; the code rate is the ratio of the information bit length to the code length; the column weight refers to the number of 1s in each column of the parity check matrix H, wherein, if the number of 1s in each column If the number is the same, the LDPC code is a regular LDPC code (regular LDPC), otherwise, it is an irregular LDPC code (Irregular LDPC); row weight refers to the number of 1 in each row of the parity check matrix H.

If N represents the code length of the LDPC code, K represents the length of the information bit, M represents the length of the parity bit, γ represents the column weight, ρ represents the row weight, and v represents the code rate, the LDPC code can be expressed as (N, K) , the parity check matrix H of the LDPC code has the following characteristics:

1. H is a full-rank matrix of M×N;

2. γ is any integer, and γ≥3, γ<<M; among them, << means far less than;

3. ρ is any integer, and ρ≥3, ρ<<N;

4. Existence relationship: v=(N-M)/N=K/N;

5. The number of rows whose elements are both 1 in any two columns does not exceed 1, that is, there is no rectangle with four corners of 1 in the matrix, that is, there is no four-line loop.

An example of an LDPC encoder is used below to illustrate the LDPC encoding process. FIG. 1 is a schematic structural diagram of an existing LDPC encoder. Referring to Fig. 1, the encoder includes: a parity check matrix construction unit, a generator matrix construction unit and an encoding unit. The working principle of the LDPC encoder shown in Figure 1 is:

First, the parity check matrix construction unit constructs the parity check matrix H according to the preset LDPC code length, code rate and column weight; then, the generation matrix construction unit constructs the generation matrix G according to the parity check matrix H, here, Since the LDPC code is a linear error correction code, the generator matrix G and the corresponding parity check matrix H are dual matrices, but G does not have the low-density characteristics of H; finally, the encoding unit uses the generator matrix G to input data s Encoding is performed to obtain the codeword t of the output LDPC code, and satisfy Ht=0.

From a practical point of view, an important factor that restricts the wide application of LDPC codes is: the storage capacity of sparse parity check matrix and non-sparse generator matrix is too large, resulting in a very large storage space when using LDPC codes for encoding. big. In addition, the high coding complexity of the traditional LDPC code is also an important factor restricting its wide application. Due to the above disadvantages, LDPC codes have not been widely used in practical applications.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method for implementing a low-density parity-check code, so as to reduce the storage space required for storing the parity-check matrix.

Another object of the present invention is to provide a device for implementing a low-density parity-check code, so as to reduce the storage space required for storing the parity-check matrix.

In order to achieve the above object, the technical solution of the present invention is specifically realized in the following way:

A method for realizing a class of low-density parity-check codes, the method comprising the following steps:

A. According to the preset code length, code rate and line weight, set the digital sequence for generating the parity check matrix;

B, according to described digital sequence, adopt the mode of cyclic shift to construct the parity check matrix of low density parity check code LDPC code;

C. Transform the input data into LDPC codewords by using the parity check matrix.

Wherein, the step B may include:

B1, determine the number of rows and the number of columns of the parity check matrix according to the code length and code rate, construct a plurality of sub-matrices, the number of rows of the sub-matrix is the number of sub-matrices of the number of rows of the parity-check matrix One-half of the number, the number of columns is equal to the number of columns of the parity check matrix;

B2. According to the digital sequence and the row weight, the parity check matrix is evenly divided into a plurality of sub-matrices according to the first row of elements in each sub-matrix;

B3. The sub-matrix is evenly divided into a plurality of sub-matrices by columns, and each sub-matrix is a square matrix;

B4. According to the elements in the first row of each sub-matrix, the elements in other rows in each sub-matrix are obtained by means of cyclic shift.

Wherein, the step B2 can be:

Divide the number sequence into a plurality of number groups containing multiple numbers in the row, and use the number in each number group in the number sequence as the column number of element 1 in the first row of the corresponding sub-matrix .

Wherein, the cyclic shift in step B4 may be: cyclic left shift and/or cyclic right shift.

Wherein, the parity check matrix may include permutation identity matrices of the length of the digital sequence.

Wherein, in the number sequence, any two numbers used to determine the number of columns where element 1 is located in the first row of each sub-matrix have different values obtained by moduloing the number of rows of the sub-matrix .

Wherein, when the LDPC code is a regular LDPC code, and the code length is 4608, the code rate is 1/2, and the row weight is 6,

The length of the number sequence is 192, and the number sequence can be:

9 212 384 2326 2803 3343 140 264 465 2405 2870 3445 192 305 560 2449 2925 3494 233 367 617 2587 2989 3571 295 460 703 2654 3055 3632 388 514 732 2709 3157 3730 442 610 832 2773 3206 3764 538 650 910 2839 3283 3886 578 770 957 2941 3344 3906 698 855 1067 2990 3442 4031 783 924 1085 3067 3476 4043 852 949 1156 3128 3598 4148 877 1065 1259 3226 3618 4242 993 1145 1335 3260 3743 4257 1073 1155 1393 3382 3755 4388 1083 1246 1456 3402 3860 4440 1174 1325 1565 3527 3954 4481 1253 1369 1648 3539 3969 4543 1297 1507 1664 2342 3644 4100 1435 1574 1734 2419 3738 4152 1502 1629 1849 2480 3753 4193 1557 1693 1924 2578 3884 4255 1621 1759 1980 2612 3936 4348 1687 1861 2088 2734 3977 4402 1789 1910 2115 2754 4039 4498 1838 1987 2183 2879 4132 4538

1915 2048 2301 2324 2891 4186 4 1976 2146 2446 2996 4282 107 2074 2180 2466 3090 4322 183 2108 2302 2591 3105 4442 3 241 2230 2603 3236 4527 94 304 2250 2708 3288 4596

The number of the sub-matrix can be 32, the number of rows can be 72, and the number of columns can be 4608;

The number of sub-matrixes in each sub-matrix can be 64;

The sub-matrix can be a square matrix with 72 rows×72 columns;

The parity check matrix may include 192 permutation identity matrices.

Wherein, when the LDPC code is an irregular LDPC code, and the code length is 4608, the code rate is 1/2, and the row weight is 7,

The length of the number sequence is 224, and the number sequence can be:

923 970 2044 2100 2976 3359 4191 136 288 1972 2422 2904 4243 4266 597 704 779 1048 2805 4274 4380 454 632 918 976 3233 4365 4425 846 904 1007 1321 2688 4429 4484 653 832 1019 1119 3089 4495 4577 538 581 702 863 3017 3511 4597 429 1596 1745 1842 2945 3458 3576 558 616 755 803 2658 3571 3604 486 544 683 1277 3197 3668 3682 659 800 889 1380 3125 3694 3765 587 687 2505 2567 3255 3800 3875 467 656 745 1482 3183 3850 3893 443 543 1672 1942 3338 3942 4000

335 425 601 2295 3039 4031 4067 210 529 729 964 2765 4043 4143 628 773 824 1194 1558 3421 4112 129 191 556 876 2238 2441 3273 513 908 953 2007 2085 2370 2875 978 1240 1510 1548 1683 1742 3343 65 134 147 764 1751 2395 2834 464 692 834 985 1366 1404 2985 3 913 2145 2207 2463 2587 3127 444 727 928 952 1222 1260 3137 303 476 618 769 1150 2652 3242 546 1116 1190 2251 2362 2637 2697 29 1590 1669 1857 2179 2355 2921 439 766 972 1046 1359 1518 3026 481 862 1650 1934 1947 2211 2869 276 393 520 1862 1875 2139 3405 648 830 891 1381 1506 2551 2725 249 325 684 2045 2479 2738 3443

The number of the sub-matrix can be 32, the number of rows can be 72, and the number of columns can be 4608;

The number of sub-matrices in each sub-matrix can be 64;

The sub-matrix can be a square matrix with 72 rows×72 columns;

The parity check matrix may include 224 permutation identity matrices.

Wherein, when the LDPC code is an irregular LDPC code, and the code length is 4608, the code rate is 43/64, and the row weight is 12 or 13,

The length of the number sequence is 256, and the number sequence can be:

536 1098 1156 1259 1889 2012 3529 3656 3739 3749 3907 3998 100 322 977 1026 1672 1940 2994 3073 3457 3677 4207 4382 743 1868 3512 3595 3605 3697 3763 3854 3900 4072 4230 4310

1199 1227 1429 3351 3523 3691 3782 3828 3895 4064 4150 4272 1079 2022 2173 2260 3194 3710 3823 3928 3992 4162 4389 4393 419 1362 1384 2475 2553 3547 3638 3856 4006 4090 4448 4531 144 146 1580 1648 2212 3449 3612 3784 4018 4089 4124 4469 4561 502 1508 2140 2508 2757 2819 2909 2978 3494 3540 4127 4555 2 683 791 1313 2376 2991 3118 3183 3305 3468 3980 4055 611 719 767 795 997 3254 3568 3632 3802 3873 3983 4102 4145 171 436 1169 1954 2052 2409 2693 2762 3496 3801 3836 4030 59 99 258 930 1053 1097 2531 2621 2690 2863 2902 3658 265 2090 2223 2282 2418 3271 3366 3502 3586 3657 3978 4036 4139 309 371 709 1374 1483 2331 3408 3514 3585 3695 3906 4067 389 1666 1834 2079 2138 2337 2873 2894 3548 3892 4103 4151 809 932 1468 1564 1594 3670 3713 3762 3820 3923 4079 4107 493 570 1267 1309 2607 2729 3078 3158 3381 3598 3851 3959 4007 30 242 327 856 2470 2535 3526 3618 3676 3779 3935 4165 549 593 1123 1791 2606 2787 3048 3237 3451 3497 3546 3863 170 1584 1719 1778 1899 2415 3165 3743 3791 3819 3932 4120 640 870 979 1647 1787 1827 2004 2253 3671 3719 3747 4026

The number of the sub-matrix can be 21, the number of rows can be 72, and the number of columns can be 4608;

The number of sub-matrices in each sub-matrix can be 64;

The sub-matrix can be a square matrix with 72 rows×72 columns;

The parity check matrix may include 256 permutation identity matrices.

Further, after the step B, it may include: rotating the obtained parity check matrix at various angles and/or performing row replacement and/or performing column replacement and/or changing the position of the sub-matrix.

A device for implementing a low-density parity-check code, the device comprising: a storage module, a check matrix generation module, and a codeword generation module;

The storage module is used to store a digital sequence and provide the digital sequence to the check matrix generation module;

The parity check matrix generation module is used to construct the parity check matrix of the LDPC code by means of cyclic shift according to the digital sequence provided by the storage module, and send the parity check matrix to the code word generation module;

The codeword generating module is configured to receive the parity check matrix from the parity check matrix generating module, and use the parity check matrix to transform input data into an LDPC codeword.

Further, the check matrix generation module may include: a digital sequence analysis unit and a cyclic shift unit;

The storage module is further configured to provide the digital sequence to the digital sequence analysis unit;

The digital sequence analysis unit is used to divide the digital sequence evenly according to the digital sequence provided by the storage module and the line weight of the LDPC code to obtain a plurality of digital groups containing the number of the line weight , and according to each digit group obtained by dividing, the first row elements of each sub-matrix after the parity check matrix is evenly divided into a plurality of sub-matrices by rows are obtained, and the obtained first row elements are determined Each sub-matrix of is sent to the cyclic shift unit;

The cyclic shift unit is used to evenly divide each sub-matrix from the digital sequence analysis unit into a square matrix by column, so as to obtain the sub-matrix of the determined first row element of the parity check matrix , and according to the elements in the first row of each sub-matrix, each sub-matrix is obtained by cyclic shifting, each sub-matrix constitutes the parity check matrix, and the parity check matrix Send to the codeword generation module.

Further, the implementation device may include: a parity check matrix conversion unit;

The cyclic shift unit is further configured to send the parity check matrix to the check matrix transformation unit;

The check matrix conversion unit is used to rotate the parity check matrix at various angles and/or perform row replacement and/or perform column replacement and/or change the position of the sub-matrix, and pass through the The parity check matrix obtained by the transformation is sent to the code word generation module.

It can be seen from the above technical scheme that the implementation method and device of a class of LDPC codes of the present invention adopt the method of expressing the parity check matrix with a digital sequence, and cyclically shifting the digital sequence to obtain the parity check matrix, so that the parity check matrix can be stored The required storage space is minimized.

In addition, since the parity check matrix of the present invention has quasi-cyclic structural characteristics, in practical applications, the characteristics of cyclic shift can be used to realize fast addressing, save processing resources, simplify encoding and decoding operations, and make encoding and decoding The complexity of code operations is reduced.

Description of drawings

FIG. 1 is a schematic structural diagram of an existing LDPC encoder.

Fig. 2 is an exemplary flow chart of a method for implementing a class of LDPC codes in the present invention.

FIG. 3 is a schematic diagram of a performance curve of (4608, 2304) regular QC-LDPC codes using BPSK modulation in an AWGN channel in Embodiment 1 of the present invention.

FIG. 4 is a schematic diagram of the BER performance curve of the (4608, 2304) regular QC-LDPC code in the AWGN channel of the T-MMB system using 8DPSK modulation in Embodiment 1 of the present invention.

FIG. 5 is a schematic diagram of performance curves of (4608, 2304) irregular QC-LDPC codes using BPSK modulation in an AWGN channel in Embodiment 2 of the present invention.

FIG. 6 is a schematic diagram of performance curves of (4608, 3096) irregular QC-LDPC codes using BPSK modulation in an AWGN channel in Embodiment 3 of the present invention.

FIG. 7 is a schematic structural diagram of an apparatus for implementing a QC-LDPC code in Embodiment 4 of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

The main idea of the present invention is to set the digital sequence used to generate the parity check matrix according to the preset code length, code rate and line weight, and then construct a quasi-cyclic (QC: The parity check matrix of the LDPC code of the Quasi Cyclic) structure, and then transform the input data with the obtained parity check matrix to obtain the LDPC code word containing the parity check information. In this way, only a very small amount of storage space is needed to store the digital sequence, and the problem of excessive storage of the parity check matrix can be solved.

Fig. 2 is an exemplary flow chart of a method for implementing a class of LDPC codes in the present invention. Referring to Figure 2, the method comprises the following steps:

Step 201: Set a digital sequence for generating a parity check matrix according to preset code length, code rate and row weight.

In this example, according to the preset code length, code rate and row weight, determine the number of rows and columns of the parity check matrix to be constructed in this example, where the number of rows is the code length of the LDPC code, expressed as N; The column number is the check bit length, expressed as M, and the parity check matrix H of the constructed QC-LDPC code of the present invention is assumed to be as shown in (1):

In (1), A _{i, j} is a circular matrix of t rows × t columns, which is called a sub-matrix of the parity check matrix H. Since A _{i, j} is a circular matrix, it can also be called a parity check matrix H Circular sub-matrix, so the parity check matrix H of the present invention has a quasi-cyclic structure, so the LDPC code constructed by the present invention is called QC-LDPC code.

According to the number of rows and the number of columns of the parity check matrix H determined above, multiple sub-matrixes are constructed, so that the number of rows of the constructed sub-matrix is one-half of the number of sub-matrixes of the number of rows of matrix H, and the number of columns is the same as that of matrix H The number of columns is equal, and each sub-matrix constructed corresponds to each row of the cyclic sub-matrix in the above matrix H, that is, each sub-matrix can be expressed as:

A _i = [A _{i, 1} , A _{i, 2 .} . . , A _{i, c} ] (i=1, 2, . . . , u) (2)

Wherein, the number of sub-matrices u=N/t, and the number of sub-matrices in the sub-matrix c=M/t. The number sequence set in this step is used to determine the number of columns where element 1 is located in the first row of each sub-matrix, that is, the first row in each sub-matrix is obtained. Therefore, the number sequence can be called Generate rules for the rows of the parity check matrix. Here, in order to ensure that the check matrix constructed is sparse, the values obtained by taking the modulus of t from the number of columns where any two elements 1 are located in each row should be different from each other. Therefore, in the set number sequence, use Any two numbers that determine the column number of element 1 in the first row of each sub-matrix have different values modulo t.

For regular LDPC codes and irregular LDPC codes with the same row weight, if ρ represents the row weight and u represents the number of sub-matrixes in the parity check matrix, since each ρ number in the digital sequence represents the first part of a sub-matrix The number of columns where element 1 is located in the row. Therefore, the number sequence consists of ρ×u numbers. Compared with M×N, the required storage space is greatly reduced; for irregular LDPCs with different row weights code, although its line weight is uncertain, but the number of numbers contained in the sequence of numbers is at most the product of the maximum value of the line weight and u, therefore, compared to M×N, the required storage space will also be be greatly reduced.

Step 202: Construct a parity check matrix of the LDPC code in a cyclic shift manner according to the set digital sequence.

In this step, first determine the first row element in each sub-matrix according to the sequence of numbers; then divide each sub-matrix into c sub-matrices evenly by column, so that each sub-matrix is a square matrix, here, c and step 201 The physical meaning of the c is the same; finally, according to the elements of the first row of each sub-matrix, the elements of other rows in the whole sub-matrix are obtained by cyclic shifting, which is the cyclic sub-matrix of the present invention, so, obtained by The parity check matrix of the QC-LDPC code in this example constituted by each cyclic sub-matrix. Assuming that the set number sequence used to generate the parity check matrix contains y numbers, because in the number sequence, any two pairs of numbers used to determine the number of columns where element 1 is located in the first row of each sub-matrix The values obtained by taking the modulus of t are different from each other, therefore, there is at most one element 1 in each row of each circulant sub-matrix, so the obtained parity check matrix contains y circulant sub-matrices containing element 1, by the It can be seen from the properties that these cyclic sub-matrices containing element 1 are permutation identity matrices.

In this step, after the parity check matrix is obtained, it can be rotated at various angles, replaced by rows, replaced by columns, or any transformation that changes the position of the cyclic sub-matrix.

Step 203: Using the obtained parity check matrix, transform the input data into LDPC codewords.

In this step, after the parity check matrix is obtained, the input data may be encoded in the same manner as in the prior art to obtain output data including parity check information.

So far, the exemplary flow of the implementation method of a class of quasi-cyclic LDPC codes in the present invention is ended.

In practical applications, the data encoded by the QC-LDPC implementation method of the present invention can be transmitted outside after being interleaved and modulated. Here, the modulation method may include: quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude phase shift keying (APSK), differential phase shift keying (DPSK), absolute phase shift keying (BPSK), Differential Amplitude Phase Shift Keying (DAPSK) and Orthogonal Frequency Division Multiplexing (OFDM), etc. The modulated signal can be transmitted through various communication systems, including terrestrial links supporting mobile multimedia broadcasting, etc. For example, it can be transmitted through a terrestrial mobile multimedia broadcasting system (T-MMB: Terrestrial Mobile Multimedia Broadcasting).

The present invention can be applied to regular LDPC codes and irregular LDPC codes. The technical solution of the present invention will be described in detail through four embodiments below.

Embodiment one:

In this embodiment, the rule (4608, 2304) LDPC code is taken as an example for illustration. The code length N of the regular LDPC code to be realized in this embodiment is 4608, the row weight ρ=6, and the code rate v=1/2. It can be seen from the corresponding relationship between the code rate, the code length and the number of check equations that the number of check equations in the check matrix in this embodiment is M=4608-2304=2304. In addition, in this embodiment, the implementation process of the above-mentioned quasi-cyclic LDPC code will be described by taking a cyclic sub-matrix with 72 rows×72 columns as the minimum cyclic unit as an example.

The flow chart of the method of this embodiment is similar to the flow chart of the exemplary method of the present invention shown in Figure 2. Referring to Figure 2, the implementation method of the QC-LDPC code in this embodiment includes the following steps:

In step 201, according to the preset code length, code rate and line weight in this embodiment, a digital sequence is set, as follows:

9 212 384 2326 2803 3343 140 264 465 2405 2870 3445 192 305 560 2449 2925 3494 233 367 617 2587 2989 3571 295 460 703 2654 3055 3632 388 514 732 2709 3157 3730 442 610 832 2773 3206 3764 538 650 910 2839 3283 3886 578 770 957 2941 3344 3906 698 855 1067 2990 3442 4031

783 924 1085 3067 3476 4043 852 949 1156 3128 3598 4148 877 1065 1259 3226 3618 4242 993 1145 1335 3260 3743 4257 1073 1155 1393 3382 3755 4388 1083 1246 1456 3402 3860 4440 1174 1325 1565 3527 3954 4481 1253 1369 1648 3539 3969 4543 1297 1507 1664 2342 3644 4100 1435 1574 1734 2419 3738 4152 1502 1629 1849 2480 3753 4193 1557 1693 1924 2578 3884 4255 1621 1759 1980 2612 3936 4348 1687 1861 2088 2734 3977 4402 1789 1910 2115 2754 4039 4498 1838 1987 2183 2879 4132 4538 1915 2048 2301 2324 2891 4186 4 1976 2146 2446 2996 4282 107 2074 2180 2466 3090 4322 183 2108 2302 2591 3105 4442 3 241 2230 2603 3236 4527 94 304 2250 2708 3288 4596

For convenience of description, the number sequence in this embodiment is referred to as number sequence one. Referring to number sequence one, each row in the sequence represents the column number of element 1 in the first row of a sub-matrix.

Since the row weight of the LDPC code in the present embodiment is 6, there are 6 elements 1 in the first row of each sub-matrix, that is, there are 6 columns with a value of 1; in addition, since the parity check in the present embodiment The cyclic sub-matrix of the check matrix is a matrix of 72×72, and the number of check equations is 2304. Therefore, the number of sub-matrices u=2304/72=32 in the parity check matrix, so, in the present embodiment The number sequence one is a sequence composed of 32 rows×6 columns=192 numbers. Among them, each group of 6 numbers represents the column number of element 1 in the first row of a sub-matrix; any two numbers in each group of 6 numbers have different values obtained by modulo 72 , to ensure that there is at most one 1 in the same row of each cyclic sub-matrix, that is, to ensure that the parity check matrix is sparse.

In step 202, according to the set number sequence one, a parity check matrix of the LDPC code is constructed by means of cyclic shift.

In this step, the parity check matrix of the LDPC code is constructed according to the following steps:

In the first step, the number sequence 1 is evenly divided into a plurality of number groups containing numbers in rows, and the number in each number group in number sequence 1 is used as the position of element 1 in the first row of the corresponding sub-matrix number of columns. That is, the number in the first number group in number sequence one is used as the column number of element 1 in the first row of the first sub-matrix, and the number in the second number group in number sequence one is used as The column number of the element 1 in the first row of the second sub-matrix, and so on, until the number in the last digit group in the number sequence one is used as the element 1 in the first row of the last sub-matrix the number of columns.

Specifically, the number sequence 1 is evenly divided into multiple number groups containing 6 numbers, and the parity check is obtained according to the numbers in each number group obtained, that is, the numbers in each row shown in number sequence 1. Elements in the first row of each submatrix of the test matrix:

For example, as shown in the number sequence one, its first number group is 9, 212, 384, 2326, 2803, and 3343, indicating the first row of the first sub-matrix in the parity check matrix, that is, the first row of the parity check matrix The values of column 9, column 212, column 384, column 2326, column 2803 and column 3343 in the first row are 1, and the remaining columns in the first row of the first sub-matrix are 0;

Its second number group is 140, 264, 465, 2405, 2870 and 3445, indicating the first row of the second sub-matrix of the parity check matrix, that is, the 140th column in the 73rd row of the parity check matrix, Columns 264, 465, 2405, 2870, and 3445 are 1, and the rest of the columns in the first row of the second submatrix are 0. For other submatrixes in the first row The value can be obtained by analogy with reference to an example, and will not be repeated here.

In the second step, each sub-matrix that has determined the value of the first row is evenly divided into c sub-matrixes by column; The length is 4608, therefore, the number of cyclic sub-matrices c=4608/72=64 in each sub-matrix; after division, the parity-check matrix of this embodiment will be divided into 32 rows×64 columns=2048 The cyclic sub-matrix, and the values of the elements in the first row of each cyclic sub-matrix have been determined.

Step 3: For each cyclic sub-matrix, the value of other row elements in the cyclic sub-matrix is obtained by cyclically shifting the elements in the first row of the cyclic sub-matrix. For example, you can move the elements in row 1 to the left by x bits to get the elements in row 2; you can shift the elements in row 2 to the left by x bits to get the elements in row 3, and so on, you can get the elements from row 2 to row 2 Values of all elements in line 72. Here, of course, cyclic right shifting or other cyclic shifting methods can also be used for shifting.

After the above steps 1 to 3, the parity check matrix of the regular QC-LDPC code in this embodiment can be obtained. Since there are 32 rows×6 columns=192 numbers in the number sequence of this embodiment, and the values obtained by taking the modulus of 72 in any two numbers in each number group are different from each other, the identity of each cyclic sub-matrix is guaranteed. There is at most one 1 in a row, therefore, there will be 192 permutation identity matrices in the parity check matrix obtained in this embodiment.

In this step, after the parity check matrix is obtained, it can be rotated at various angles, replaced by rows, replaced by columns, or any transformation that changes the position of the cyclic sub-matrix.

In step 203, the obtained parity check matrix is used in the same manner as in the prior art to transform the input data into LDPC codewords.

So far, the exemplary flow of the implementation method of the QC-LDPC code in Embodiment 1 of the present invention is ended.

It can be seen from the above embodiments that the present invention adopts a method of expressing the parity check matrix with a digital sequence, and cyclically shifting the digital sequence to obtain the parity check matrix, so that the storage space required for storing the parity check matrix is minimized.

In addition, since the parity check matrix in this embodiment has quasi-cyclic structural characteristics, in practical applications, the characteristics of cyclic shift can be used to realize fast addressing, save processing resources, simplify encoding and decoding operations, and make encoding and The complexity of the decoding operation is reduced.

The following describes the performance of the (4608, 2304) regular QC-LDPC code provided in Embodiment 1 of the present invention by comparing it with the simulation of the prior art. FIG. 3 is a schematic diagram of a performance curve of (4608, 2304) regular QC-LDPC codes using BPSK modulation in an AWGN channel in Embodiment 1 of the present invention. In this simulation, the decoding uses the sum-product algorithm, and the maximum number of iterations is 50.

Referring to Fig. 3, wherein, straight line 301 represents Shannon limit;

Curve 302 represents adopting (4608,2304) rule QC-LDPC code of the present invention to encode, BPSK way to modulate, then transmit in additive white Gaussian noise (AWGN) channel, and adopt sum product decoding algorithm (SPA: Sum- Product Arithmetic) the bit error rate (BER) curve of the signal decoded;

Curve 303 represents the frame error rate (BLER) curve of the signal that adopts (4608, 2304) rule QC-LDPC code of the present invention to encode, BPSK mode to modulate, then transmit in AWGN channel, and adopt SPA algorithm to decode;

Curve 304 represents the BER performance curve of a signal that is directly modulated by BPSK without encoding, and then transmitted through an AWGN channel;

It can be seen from Fig. 3 that the (4608, 2304) regular QC-LDPC code of the present invention has a very low error floor, and its performance curve is only 1.9 dB away from the Shannon limit at BER=10 ⁻⁹ .

Apply the (4608, 2304) rule QC-LDPC code provided by this embodiment to the AWGN channel of the T-MMB system, and use 8DPSK mode for modulation and SPA algorithm for decoding, the BER performance as shown in Figure 4 will be obtained curve. Referring to Fig. 4, the curve shown in the figure is in the AWGN channel of T-MMB system, after adopting (4608,2304) rule QC-LDPC code of the present invention to encode, 8DPSK mode to modulate, and adopt SPA algorithm to decode after Signal BER performance curve.

In the first embodiment above, the specific implementation method of the (4608, 2304) regular QC-LDPC code of the present invention is described in detail. In the following two embodiments, the realization of the irregular QC-LDPC code of the present invention will be described The specific implementation of the method will be described in detail.

Embodiment two:

In this embodiment, an irregular LDPC code with the same row weight (4608, 2304) is taken as an example for illustration. The code length N of the regular LDPC code to be realized in this embodiment is 4608, the row weight ρ=7, and the code rate v=1/2. From the correspondence between the code rate, the code length and the number of check equations, it can be known that this The number of check equations in the check matrix of the embodiment is M=4608-2304=2304. In addition, in this embodiment, the same as the first embodiment, a 72×72 cyclic sub-matrix is taken as an example to illustrate the implementation process of the above-mentioned quasi-cyclic LDPC code.

The flow chart of the method of this embodiment is similar to the flow chart of the exemplary method of the present invention shown in Figure 2. Referring to Figure 2, the implementation method of the QC-LDPC code in this embodiment includes the following steps:

In step 201, according to the preset code length, code rate and line weight in this embodiment, a digital sequence is set, as follows:

923 970 2044 2100 2976 3359 4191 136 288 1972 2422 2904 4243 4266 597 704 779 1048 2805 4274 4380 454 632 918 976 3233 4365 4425 846 904 1007 1321 2688 4429 4484 653 832 1019 1119 3089 4495 4577 538 581 702 863 3017 3511 4597 429 1596 1745 1842 2945 3458 3576 558 616 755 803 2658 3571 3604 486 544 683 1277 3197 3668 3682 659 800 889 1380 3125 3694 3765 587 687 2505 2567 3255 3800 3875 467 656 745 1482 3183 3850 3893 443 543 1672 1942 3338 3942 4000 335 425 601 2295 3039 4031 4067 210 529 729 964 2765 4043 4143 628 773 824 1194 1558 3421 4112 129 191 556 876 2238 2441 3273 513 908 953 2007 2085 2370 2875 978 1240 1510 1548 1683 1742 3343 65 134 147 764 1751 2395 2834 464 692 834 985 1366 1404 2985

3 913 2145 2207 2463 2587 3127 444 727 928 952 1222 1260 3137 303 476 618 769 1150 2652 3242 546 1116 1190 2251 2362 2637 2697 29 1590 1669 1857 2179 2355 2921 439 766 972 1046 1359 1518 3026 481 862 1650 1934 1947 2211 2869 276 393 520 1862 1875 2139 3405 648 830 891 1381 1506 2551 2725 249 325 684 2045 2479 2738 3443

For convenience of description, the number sequence in this embodiment is referred to as number sequence two. Referring to number sequence 2, each row in this sequence represents the column number of element 1 in the first row of a sub-matrix.

Since the row weight of the LDPC code in the present embodiment is 7, there are 7 elements 1 in the first row of each sub-matrix, that is, there are 7 columns with a value of 1; in addition, since the parity check in the present embodiment The cyclic sub-matrix of the check matrix is a matrix of 72×72, and the number of check equations is 2304. Therefore, the number of sub-matrices u=2304/72=32 in the parity check matrix, so, in the present embodiment The number sequence two is a sequence consisting of 32 rows×7 columns=244 numbers. Among them, each group of 7 numbers represents the column number of element 1 in the first row of a sub-matrix; any two numbers in each group of 7 numbers have different values obtained by modulo 72 , to ensure that there is at most one 1 in the same row of each cyclic sub-matrix, that is, to ensure that the parity check matrix is sparse.

In step 202, according to the set number sequence two, a parity check matrix of the LDPC code is constructed by means of cyclic shift.

In this step, the parity check matrix of the LDPC code is constructed according to the following steps:

In the first step, the number sequence 2 is evenly divided into multiple number groups containing 7 numbers, and the parity check is obtained according to the obtained numbers in each number group, that is, the numbers in each row shown in number sequence 2 Elements in the first row of each submatrix of the test matrix:

For example, as shown in the number sequence two, its first number group is 923, 970, 2044, 2100, 2976, 3359, and 4191, indicating the first row of the first sub-matrix in the parity check matrix, that is, the parity check matrix The values of the 923rd, 970th, 2044th, 2100th, 2976th, 3359th and 4191th columns in the first row of the matrix are 1, and in the first row of the first sub-matrix The rest of the columns are 0;

Its second number group is 136, 288, 1972, 2422, 2904, 4243 and 4266, indicating the first row of the second sub-matrix of the parity check matrix, that is, the 136th row in the 73rd row of the parity check matrix column, the 288th column, the 1972th column, the 2422nd column, the 2904th column, the 4243rd column and the 4266th column take the value of 1, the rest of the columns in the first row of the second sub-matrix are 0, for the other sub-matrix The value of the first row of the matrix can be obtained by analogy with reference to an example, and will not be repeated here.

In the second step, each sub-matrix that has determined the value of the first row is evenly divided into c sub-matrixes by column; The length is 4608, therefore, the number of cyclic sub-matrices c=4608/72=64 in each sub-matrix; after division, the parity-check matrix of this embodiment will be divided into 32 rows×64 columns=2048 The cyclic sub-matrix, and the values of the elements in the first row of each cyclic sub-matrix have been determined.

Step 3: For each cyclic sub-matrix, the value of other row elements in the cyclic sub-matrix is obtained by cyclically shifting the elements in the first row of the cyclic sub-matrix. For example, you can move the elements in row 1 to the left by x bits to get the elements in row 2; you can shift the elements in row 2 to the left by x bits to get the elements in row 3, and so on, you can get the elements from row 2 to row 2 Values of all elements in line 72. Here, of course, cyclic right shifting or other cyclic shifting methods can also be used for shifting.

After the above steps 1 to 3, the parity check matrix of the irregular QC-LDPC code in this embodiment can be obtained. Since there are 32 rows×7 columns=224 numbers in the number sequence of the present embodiment, and the values obtained by modulo 72 of any two numbers in each number group are different from each other, the identity of each cyclic sub-matrix is guaranteed. There is at most one 1 in a row, therefore, there will be 224 permutation identity matrices in the parity check matrix obtained in this embodiment.

In this step, after the parity check matrix is obtained, it can be rotated at various angles, replaced by rows, replaced by columns, or any transformation that changes the position of the cyclic sub-matrix.

In step 203, the obtained parity check matrix is used in the same manner as in the prior art to transform the input data into LDPC codewords.

So far, the exemplary flow of the implementation method of the QC-LDPC code in the second embodiment of the present invention is ended.

It can be seen from the above embodiments that the present invention adopts a method of expressing the parity check matrix with a digital sequence, and cyclically shifting the digital sequence to obtain the parity check matrix, so that the storage space required for storing the parity check matrix is minimized.

Moreover, since the parity check matrix in this embodiment has quasi-cyclic structural characteristics, in practical applications, the characteristics of cyclic shift can be used to realize fast addressing, which saves processing resources, simplifies encoding and decoding operations, and makes The complexity of encoding and decoding operations is reduced.

The performance of the (4608, 2304) irregular QC-LDPC code provided in Embodiment 2 of the present invention is described below by comparing it with the simulation of the prior art. FIG. 5 is a schematic diagram of performance curves of (4608, 2304) irregular QC-LDPC codes using BPSK modulation in an AWGN channel in Embodiment 2 of the present invention. In this simulation, the decoding uses the SPA algorithm, and the maximum number of iterations is 50.

Referring to Fig. 5, wherein, straight line 501 represents Shannon limit;

Curve 502 represents the BER curve of the signal that adopts (4608, 2304) irregular QC-LDPC code of the present invention to encode, BPSK mode to modulate, then transmit in AWGN channel, and adopt SPA algorithm to decode;

Curve 503 represents the BLER curve of the signal that adopts (4608, 2304) irregular QC-LDPC code of the present invention to encode, BPSK mode to modulate, then transmit in AWGN channel, and adopt SPA algorithm to decode;

Curve 504 represents the BER performance curve of a signal that is directly modulated by BPSK without encoding, and then transmitted through an AWGN channel;

As can be seen from Fig. 5, the error floor of the (4608, 2304) irregular QC-LDPC code of the present invention is very low, and, at BER= ^10-9 , its performance curve is only 1.6dB away from the Shannon limit, which is higher than that of Embodiment 1 of the present invention. The performance of the (4608, 2304) regular QC-LDPC code provided in is better.

In the above-mentioned embodiment two, taking the irregular QC-LDPC code with the same row weight as an example, the technical solution of the present invention is described in detail. Next, an example of an LDPC code with different row weights is used to describe the irregular QC-LDPC code of the present invention. The implementation method is introduced.

Embodiment three:

In this embodiment, an irregular LDPC code with (4608, 3096) row weights is taken as an example for illustration. The code length N of the regular LDPC code to be realized in this embodiment is 4608, the line weight ρ=12 or 13, and the code rate v=43/64, as can be known from the correspondence between the code rate, the code length and the number of check equations , the number of check equations in the check matrix in this embodiment is M=4608-3096=1512. In addition, in this embodiment, the same as the first embodiment, a 72×72 cyclic sub-matrix is taken as an example to illustrate the implementation process of the above-mentioned quasi-cyclic LDPC code.

The flow chart of the method of this embodiment is similar to the flow chart of the exemplary method of the present invention shown in Figure 2. Referring to Figure 2, the implementation method of the QC-LDPC code in this embodiment includes the following steps:

In step 201, according to the preset code length, code rate and line weight in this embodiment, a digital sequence is set, as follows:

536 1098 1156 1259 1889 2012 3529 3656 3739 3749 3907 3998 100 322 977 1026 1672 1940 2994 3073 3457 3677 4207 4382 743 1868 3512 3595 3605 3697 3763 3854 3900 4072 4230 4310 1199 1227 1429 3351 3523 3691 3782 3828 3895 4064 4150 4272 1079 2022 2173 2260 3194 3710 3823 3928 3992 4162 4389 4393 419 1362 1384 2475 2553 3547 3638 3856 4006 4090 4448 4531 144 146 1580 1648 2212 3449 3612 3784 4018 4089 4124 4469 4561 502 1508 2140 2508 2757 2819 2909 2978 3494 3540 4127 4555 2 683 791 1313 2376 2991 3118 3183 3305 3468 3980 4055 611 719 767 795 997 3254 3568 3632 3802 3873 3983 4102 4145 171 436 1169 1954 2052 2409 2693 2762 3496 3801 3836 4030 59 99 258 930 1053 1097 2531 2621 2690 2863 2902 3658 265 2090 2223 2282 2418 3271 3366 3502 3586 3657 3978 4036 4139 309 371 709 1374 1483 2331 3408 3514 3585 3695 3906 4067 389 1666 1834 2079 2138 2337 2873 2894 3548 3892 4103 4151 809 932 1468 1564 1594 3670 3713 3762 3820 3923 4079 4107 493 570 1267 1309 2607 2729 3078 3158 3381 3598 3851 3959 4007 30 242 327 856 2470 2535 3526 3618 3676 3779 3935 4165 549 593 1123 1791 2606 2787 3048 3237 3451 3497 3546 3863

170 1584 1719 1778 1899 2415 3165 3743 3791 3819 3932 4120 640 870 979 1647 1787 1827 2004 2253 3671 3719 3747 4026

For convenience of description, the number sequence in this embodiment is referred to as number sequence three. Referring to number sequence three, each row in the sequence represents the column number of element 1 in the first row of a sub-matrix.

Since the row weight of the LDPC code in this embodiment is 12 or 13, there are 12 or 13 element 1s in the first row of each sub-matrix, that is, there are 12 or 13 columns with a value of 1, according to Number sequence three, there are 17 sub-matrixes with a row weight of 12 and 4 sub-matrices with a row weight of 13 in this embodiment; in addition, since the cyclic sub-matrix of the parity check matrix in this embodiment is a matrix of 72×72 , and the number of check equations is 1512, therefore, the number u=1512/72=21 of sub-matrixes in the parity check matrix, so the number sequence three in the present embodiment is 17 rows×12 columns+4 Row × 13 columns = sequence of 256 numbers. Among them, each group of 12 or 13 numbers represents the column number of element 1 in the first row of a sub-matrix; the difference between any two numbers in each group of 12 or 13 numbers is The values obtained by taking the modulus of 72 are different from each other, so as to ensure that there is at most one 1 in the same row of each cyclic sub-matrix, that is, to ensure that the parity check matrix is sparse.

In step 202, according to the set number sequence three, the parity check matrix of the LDPC code is constructed by means of cyclic shift.

In this step, the parity check matrix of the LDPC code is constructed according to the following steps:

In the first step, the number sequence three is divided into a plurality of number groups containing numbers in rows, and according to the obtained numbers in each number group, that is, each row shown in number sequence three, the parity check matrix is obtained Elements in the first row of each submatrix:

For example, as shown in the number sequence three, the first number group is 536, 1098, 1156, 1259, 1889, 2012, 3529, 3656, 3739, 3749, 3907, and 3998, indicating that the first group in the parity check matrix The first row of the matrix, that is, the 536th column, the 1098th column, the 1156th column, the 1259th column, the 1889th column, the 2012th column, the 3529th column, the 3656th column, the 2012th column in the first row of the parity check matrix The value of the 3739th column, the 3749th column, the 3907th column and the 3998th column is 1, and the remaining columns in the first row of the first sub-matrix are 0; for the values of the first row of other sub-matrices, you can refer to It can be obtained by analogy with an example, and will not be repeated here.

In the second step, each sub-matrix that has determined the value of the first row is evenly divided into c sub-matrixes by column; The length is 4608, therefore, the number of cyclic sub-matrices c=4608/72=64 in each sub-matrix; after division, the parity-check matrix of this embodiment will be divided into 32 rows×64 columns=2048 The cyclic sub-matrix, and the values of the elements in the first row of each cyclic sub-matrix have been determined.

Step 3: For each cyclic sub-matrix, the value of other row elements in the cyclic sub-matrix is obtained by cyclically shifting the elements in the first row of the cyclic sub-matrix. For example, you can move the elements in row 1 to the left by x bits to get the elements in row 2; you can shift the elements in row 2 to the left by x bits to get the elements in row 3, and so on, you can get the elements from row 2 to row 2 Values of all elements in line 72. Here, of course, cyclic right shifting or other cyclic shifting methods can also be used for shifting.

After the above steps 1 to 3, the parity check matrix of the irregular QC-LDPC code in this embodiment can be obtained. Since there are 256 numbers in the number sequence of this embodiment, and the values obtained by modulo 72 of any two numbers in each number group are different from each other, it is guaranteed that there is at most one 1 in the same row of each cyclic sub-matrix , therefore, there will be 256 permutation identity matrices in the parity check matrix obtained in this embodiment.

In this step, after the parity check matrix is obtained, it can be rotated at various angles, replaced by rows, replaced by columns, or any transformation that changes the position of the cyclic sub-matrix.

In step 203, the obtained parity check matrix is used in the same manner as in the prior art to transform the input data into LDPC codewords.

So far, the exemplary flow of the implementation method of the QC-LDPC code in the third embodiment of the present invention is ended.

It can be seen from the above embodiments that the present invention adopts a method of expressing the parity check matrix with a digital sequence, and cyclically shifting the digital sequence to obtain the parity check matrix, so that the storage space required for storing the parity check matrix is minimized.

In addition, since the parity check matrix in this embodiment has quasi-cyclic structural characteristics, in practical applications, the characteristics of cyclic shift can be used to achieve fast addressing, which saves processing resources, simplifies encoding and decoding operations, and makes The complexity of encoding and decoding operations is reduced.

The performance of the (4608, 3096) irregular QC-LDPC code provided in Embodiment 3 of the present invention is described below by comparing it with the simulation of the prior art. FIG. 6 is a schematic diagram of performance curves of (4608, 3096) irregular QC-LDPC codes using BPSK modulation in an AWGN channel in Embodiment 3 of the present invention. In this simulation, the decoding uses the sum-product algorithm, and the maximum number of iterations is 50.

Referring to Fig. 6, wherein, straight line 601 represents Shannon limit;

Curve 602 represents the BER curve of the signal that adopts (4608, 3096) irregular QC-LDPC code of the present invention to encode, BPSK mode to modulate, then transmit in AWGN channel, and adopt SPA algorithm to decode;

Curve 603 represents the BLER curve of the signal that adopts (4608, 3096) irregular QC-LDPC code of the present invention to encode, BPSK mode to modulate, then transmit in AWGN channel, and adopt SPA algorithm to decode;

Curve 604 represents the BER performance curve of a signal that is directly modulated by BPSK without encoding, and then transmitted through an AWGN channel;

As can be seen from Fig. 6, the error floor of the (4608, 3096) irregular QC-LDPC code of the present invention is very low, and, at BER=10 ^-9 place, its performance curve distance Shannon limit is less than 1.5dB, compared with the second embodiment of the present invention The performance of the (4608, 2304) irregular QC-LDPC code implemented in is better.

The realization method of the QC-LDPC code of the present invention is described in detail in the above embodiment, and the specific implementation of the coder of the QC-LDPC code of the present invention will be described below through an example of an encoder.

Embodiment four:

FIG. 7 is a schematic structural diagram of an apparatus for implementing a QC-LDPC code in Embodiment 4 of the present invention. Referring to FIG. 7 , the implementation device includes: a storage module 710 , a check matrix generation module 720 and a codeword generation module 730 , wherein the check matrix generation module 720 further includes a digital sequence analysis unit 721 and a cyclic shift unit 722 .

In the implementation device shown in Figure 7, the storage module 710 is used to store the digital sequence, and provides the stored digital sequence to the digital sequence analysis unit 721 in the check matrix generation module 720;

The digital sequence analysis unit 721 in the check matrix generation module 720 is used to divide the digital sequence evenly according to the digital sequence provided by the storage module 710 and the row weight of the LDPC code to obtain a plurality of digital groups comprising the row heavy digits , and according to each number sequence obtained by division, the first row elements of each sub-matrix after the parity check matrix is evenly divided into multiple sub-matrices by row are obtained, and the obtained determined elements of the first row are obtained Each sub-matrix is sent to the cyclic shift unit 722 in the check matrix generation module 720;

The cyclic shift unit 722 in the check matrix generation module 720 is used to divide each sub-matrix from the digital sequence analysis unit 721 into a square matrix evenly by column, and obtain the determined first row element of the parity check matrix sub-matrix, and according to the first row element of each sub-matrix, each sub-matrix is obtained by cyclic shifting. Here, each sub-matrix constitutes the parity check matrix in this embodiment, and the parity The check matrix is sent to the codeword generation module 730;

The codeword generation module 730 is configured to receive the parity check matrix from the cyclic shift unit 722 in the check matrix generation module 720, and use the parity check matrix to transform the input data into an LDPC codeword.

In the implementation device shown in FIG. 7 , it may further include: a parity check matrix conversion unit, which can be used to perform various angle rotations and row replacements on the parity check matrix obtained by the cyclic shift unit 722 , column permutation or changing sub-matrix positions and other transformations, and then send the transformed parity check matrix to the code word generation module 730 .

The parity check matrix conversion unit may be set separately in the implementation device of this embodiment, or may be set in the parity check matrix generating module 720, or may be set in other modules.

It can be seen from the above embodiments that the present invention adopts a method of expressing the parity check matrix with a digital sequence, and cyclically shifting the digital sequence to obtain the parity check matrix, so that the storage space required for storing the parity check matrix is minimized.

In addition, since the parity check matrix in this embodiment has quasi-cyclic structural characteristics, in practical applications, the characteristics of cyclic shift can be used to realize fast addressing, save processing resources, simplify encoding and decoding operations, and make encoding and The complexity of the decoding operation is reduced.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (13)

1, the realization method of a kind of low-density parity-check code, it is characterized in that, the method comprises the following steps: A. According to the preset code length, code rate and line weight, set the digital sequence for generating the parity check matrix; B, according to described digital sequence, adopt the mode of cyclic shift to construct the parity check matrix of low density parity check code LDPC code; C. Transform the input data into LDPC codewords by using the parity check matrix. 2. The implementation method according to claim 1, characterized in that the step B comprises: B1, determine the number of rows and the number of columns of the parity check matrix according to the code length and code rate, construct a plurality of sub-matrices, the number of rows of the sub-matrix is the number of sub-matrices of the number of rows of the parity-check matrix One-half of the number, the number of columns is equal to the number of columns of the parity check matrix; B2. Determine the first row element in each sub-matrix in the plurality of sub-matrices according to the number sequence and the row weight; B3, divide each sub-matrix into a plurality of sub-matrices evenly by column, and make each sub-matrix a square matrix; B4. According to the elements in the first row of each sub-matrix, the elements in other rows in each sub-matrix are obtained by means of cyclic shift. 3. The method according to claim 2, characterized in that the step B2 is: Divide the number sequence into a plurality of number groups containing multiple numbers in the row, and use the number in each number group in the number sequence as the column number of element 1 in the first row of the corresponding sub-matrix . 4. The method according to claim 2, wherein the cyclic shift in step B4 is: cyclic left shift and/or cyclic right shift. 5. The method according to claim 2, wherein the parity-check matrix includes permutation identity matrices of the length of the digital sequence. 6. The method according to claim 2, characterized in that, in the sequence of numbers, any two numbers used to determine the number of columns where element 1 is located in the first row of each sub-matrix pair the The values obtained modulo the number of rows of the submatrix are different from each other. 7. The method according to claim 2, wherein when the LDPC code is a regular LDPC code, and the code length is 4608, the code rate is 1/2, and the row weight is 6, The length of the sequence of numbers is 192, and the sequence of numbers is: 9 212 384 2326 2803 3343 140 264 465 2405 2870 3445 192 305 560 2449 2925 3494 233 367 617 2587 2989 3571 295 460 703 2654 3055 3632 388 514 732 2709 3157 3730 442 610 832 2773 3206 3764 538 650 910 2839 3283 3886 578 770 957 2941 3344 3906 698 855 1067 2990 3442 4031 783 924 1085 3067 3476 4043 852 949 1156 3128 3598 4148 877 1065 1259 3226 3618 4242 993 1145 1335 3260 3743 4257 1073 1155 1393 3382 3755 4388 1083 1246 1456 3402 3860 4440 1174 1325 1565 3527 3954 4481 1253 1369 1648 3539 3969 4543 1297 1507 1664 2342 3644 4100 1435 1574 1734 2419 3738 4152 1502 1629 1849 2480 3753 4193 1557 1693 1924 2578 3884 4255 1621 1759 1980 2612 3936 4348 1687 1861 2088 2734 3977 4402 1789 1910 2115 2754 4039 4498 1838 1987 2183 2879 4132 4538 1915 2048 2301 2324 2891 4186 4 1976 2146 2446 2996 4282 107 2074 2180 2466 3090 4322 183 2108 2302 2591 3105 4442 3 241 2230 2603 3236 4527 94 304 2250 2708 3288 4596 The number of the sub-matrix is 32, the number of rows is 72, and the number of columns is 4608; The number of sub-matrixes in each sub-matrix is 64; The sub-matrix is a square matrix with 72 rows×72 columns; The parity check matrix includes 192 permutation identity matrices. 8. The method according to claim 2, wherein when the LDPC code is an irregular LDPC code, and the code length is 4608, the code rate is 1/2, and the row weight is 7 , The length of the sequence of numbers is 224, and the sequence of numbers is: 923 970 2044 2100 2976 3359 4191 136 288 1972 2422 2904 4243 4266 597 704 779 1048 2805 4274 4380 454 632 918 976 3233 4365 4425 846 904 1007 1321 2688 4429 4484 653 832 1019 1119 3089 4495 4577 538 581 702 863 3017 3511 4597 429 1596 1745 1842 2945 3458 3576 558 616 755 803 2658 3571 3604 486 544 683 1277 3197 3668 3682 659 800 889 1380 3125 3694 3765 587 687 2505 2567 3255 3800 3875 467 656 745 1482 3183 3850 3893 443 543 1672 1942 3338 3942 4000 335 425 601 2295 3039 4031 4067 210 529 729 964 2765 4043 4143 628 773 824 1194 1558 3421 4112 129 191 556 876 2238 2441 3273 513 908 953 2007 2085 2370 2875 978 1240 1510 1548 1683 1742 3343 65 134 147 764 1751 2395 2834 464 692 834 985 1366 1404 2985 3 913 2145 2207 2463 2587 3127 444 727 928 952 1222 1260 3137 303 476 618 769 1150 2652 3242 546 1116 1190 2251 2362 2637 2697 29 1590 1669 1857 2179 2355 2921 439 766 972 1046 1359 1518 3026 481 862 1650 1934 1947 2211 2869 276 393 520 1862 1875 2139 3405 648 830 891 1381 1506 2551 2725 249 325 684 2045 2479 2738 3443 The number of the sub-matrix is 32, the number of rows is 72, and the number of columns is 4608; The number of sub-matrixes in each sub-matrix is 64; The sub-matrix is a square matrix with 72 rows×72 columns; The parity check matrix includes 224 permutation identity matrices. 9. The method according to claim 2, wherein when the LDPC code is an irregular LDPC code, and the code length is 4608, the code rate is 43/64, and the row weight is 12 or 13:00, The length of the number sequence is 256, and the number sequence is: 536 1098 1156 1259 1889 2012 3529 3656 3739 3749 3907 3998 100 322 977 1026 1672 1940 2994 3073 3457 3677 4207 4382 743 1868 3512 3595 3605 3697 3763 3854 3900 4072 4230 4310 1199 1227 1429 3351 3523 3691 3782 3828 3895 4064 4150 4272 1079 2022 2173 2260 3194 3710 3823 3928 3992 4162 4389 4393 419 1362 1384 2475 2553 3547 3638 3856 4006 4090 4448 4531 144 146 1580 1648 2212 3449 3612 3784 4018 4089 4124 4469 4561 502 1508 2140 2508 2757 2819 2909 2978 3494 3540 4127 4555 2 683 791 1313 2376 2991 3118 3183 3305 3468 3980 4055 611 719 767 795 997 3254 3568 3632 3802 3873 3983 4102 4145 171 436 1169 1954 2052 2409 2693 2762 3496 3801 3836 4030 59 99 258 930 1053 1097 2531 2621 2690 2863 2902 3658 265 2090 2223 2282 2418 3271 3366 3502 3586 3657 3978 4036 4139 309 371 709 1374 1483 2331 3408 3514 3585 3695 3906 4067 389 1666 1834 2079 2138 2337 2873 2894 3548 3892 4103 4151 809 932 1468 1564 1594 3670 3713 3762 3820 3923 4079 4107 493 570 1267 1309 2607 2729 3078 3158 3381 3598 3851 3959 4007 30 242 327 856 2470 2535 3526 3618 3676 3779 3935 4165 549 593 1123 1791 2606 2787 3048 3237 3451 3497 3546 3863 170 1584 1719 1778 1899 2415 3165 3743 3791 3819 3932 4120 640 870 979 1647 1787 1827 2004 2253 3671 3719 3747 4026 The number of the sub-matrix is 21, the number of rows is 72, and the number of columns is 4608; The number of sub-matrixes in each sub-matrix is 64; The sub-matrix is a square matrix with 72 rows×72 columns; The parity check matrix includes 256 permutation identity matrices. 10. The method according to claim 7, 8 or 9, characterized in that, after the step B, further comprising: rotating the obtained parity check matrix at various angles and/or performing row replacement and /or perform column replacement and/or change the position of the sub-matrix. 11. A device for realizing a low-density parity-check code, characterized in that the device for realizing comprises: a storage module, a check matrix generation module and a codeword generation module; The storage module is used to store a digital sequence and provide the digital sequence to the check matrix generation module; The parity check matrix generation module is used to construct the parity check matrix of the LDPC code by means of cyclic shift according to the digital sequence provided by the storage module, and send the parity check matrix to the code word generation module; The codeword generating module is configured to receive the parity check matrix from the parity check matrix generating module, and use the parity check matrix to transform input data into an LDPC codeword. 12. The implementation device according to claim 11, wherein the parity check matrix generation module further comprises: a digital sequence analysis unit and a cyclic shift unit; The storage module is further configured to provide the digital sequence to the digital sequence analysis unit; The digital sequence analysis unit is used to divide the digital sequence evenly according to the digital sequence provided by the storage module and the line weight of the LDPC code to obtain a plurality of digital groups containing the number of the line weight , and according to each digit group obtained by dividing, the first row elements of each sub-matrix after the parity check matrix is evenly divided into a plurality of sub-matrices by rows are obtained, and the obtained first row elements are determined Each sub-matrix of is sent to the cyclic shift unit; The cyclic shift unit is used to evenly divide each sub-matrix from the digital sequence analysis unit into a square matrix by column, so as to obtain the sub-matrix of the determined first row element of the parity check matrix , and according to the elements in the first row of each sub-matrix, each sub-matrix is obtained by cyclic shifting, each sub-matrix constitutes the parity check matrix, and the parity check matrix Send to the codeword generation module. 13. The realization device according to claim 12, characterized in that, the realization device further comprises: a parity check matrix conversion unit; The cyclic shift unit is further configured to send the parity check matrix to the check matrix conversion unit; The check matrix conversion unit is used to rotate the parity check matrix at various angles and/or perform row replacement and/or perform column replacement and/or change the position of the sub-matrix, and pass through the The parity check matrix obtained by the transformation is sent to the code word generation module.

Images