CN1964199A

CN1964199A - A method and device to realize low density parity check code

Info

Publication number: CN1964199A
Application number: CN 200610145182
Authority: CN
Inventors: 鲍东山; 王加庆
Original assignee: BEIJING NUFRONT SOFTWARE TECHNOLOGY Co Ltd
Current assignee: BEIJING PUJIXIN TECHNOLOGY CO LTD; Beijing Nufront Mobile Multimedia Technology Co Ltd; Nufront Mobile Communications Tech Co Ltd
Priority date: 2006-06-14
Filing date: 2006-11-17
Publication date: 2007-05-16
Anticipated expiration: 2026-11-17
Also published as: CN100423454C

Abstract

The disclosed realization method for LDPC comprises: A. according to preset code length, code rate and row weight, setting digital sequence for parity check matrix; B. circular shifting to construct the matrix for LDPC; and C. converting input data into LDPC by the matrix. This invention can reduce storage room.

Description

The implementation method of low-density parity check code and device

Technical field

The present invention relates to the encoding and decoding technique of digital communication system, particularly the implementation method of low-density parity check code and device.

Background technology

Because the influence of the factors such as multipath fading in random noise, the wireless transmission, make the transfer of data in the communication system that various mistakes often take place, especially in digital multimedia broadcasting system, data volume is big, limited bandwidth and various bursty interference are very many, makes the reliability of data transmission problem become more outstanding.

Usually, adopt the method for chnnel coding to guarantee in noisy communication channel, to provide reliable communication.In the existing implementation method, low density parity check code (LDPC) is widely regarded as one of best error correction implementation method of performance.This be because, a kind of performance quality of coding can be weighed with the degree that approaches Shannon (Shannon) limit, and LDPC sign indicating number decoding complexity lower, have a performance that approaches shannon limit.Briefly introduce existing LDPC sign indicating number below.

The LDPC sign indicating number is a kind of linear error correction sign indicating number based on sparse parity check matrix H.The characteristics of H matrix are that the element 0 in the matrix accounts for the overwhelming majority, and the density of element 1 is very low, promptly so-called low-density.The notion that following comparison basis is arranged in the LDPC sign indicating number:

Code length, be meant the input data encoded after, the length of resulting dateout, the i.e. length of LDPC code word; Check digit length is the number of check equations, is meant the shared bit number of check digit in the dateout, and promptly code length subtracts information bit length; Code check is an information bit length and the ratio of code length; Column weight is meant 1 number in each row of parity check matrix H, and wherein, if 1 number is identical in every row, then this LDPC sign indicating number is regular LDPC sign indicating number (regular LDPC), otherwise, be irregular LDPC codes (Irregular LDPC); Row is heavy, is meant in each row of parity check matrix H 1 number.

If represent that with N code length, the K of LDPC sign indicating number represent that information bit length, M represent that check digit length, γ represent that column weight, ρ represent that row is heavy, v represents code check, this LDPC code table can be shown (N, K), the parity check matrix H of this LDPC sign indicating number has following characteristic:

1, H is the non-singular matrix of M * N;

2, γ is an arbitrary integer, and γ 〉=3, γ＜＜M; Wherein,＜＜expression much smaller than;

3, ρ is an arbitrary integer, and ρ 〉=3, ρ＜＜N;

4, there is relation: v=(N-M)/N=K/N;

5, element is all 1 line number and is no more than 1 in any two row, and promptly not having four angles in the matrix all is 1 rectangle, does not promptly have the circulation of four lines.

Below by a LDPC encoder instances, the LDPC cataloged procedure is described.Fig. 1 is the structural representation of existing LDPC encoder.Referring to Fig. 1, this encoder comprises: parity matrix structural unit, generator matrix structural unit and coding unit.The operation principle of LDPC encoder shown in Figure 1 is:

At first, the parity matrix structural unit is constructed parity check matrix H according to predefined LDPC code length, code check and column weight; Then, according to parity check matrix H structure generator matrix G, here, because the LDPC sign indicating number is a kind of linear error correction sign indicating number, therefore, generator matrix G and corresponding parity-check matrix H are the antithesis matrixes by the generator matrix structural unit, but G does not possess the low-density characteristics of H; At last, coding unit is encoded to input data s with generator matrix G, the code word t of the LDPC sign indicating number that obtains exporting, and satisfy Ht=0.

From point of view of practicability, a key factor of restriction LDPC sign indicating number extensive use is: the memory space of sparse parity matrix and non-sparse generator matrix is excessive, causes when using the LDPC sign indicating number to encode needed memory space very big.In addition, traditional LDPC sign indicating number encoder complexity is too high also is an important factor of its extensive use of restriction.Because the existence of above-mentioned shortcoming causes the LDPC sign indicating number not dropped in the practical application widely as yet.

Summary of the invention

In view of this, main purpose of the present invention is to provide the implementation method of low-density parity check code, to reduce the required memory space of storage parity matrix.

Another object of the present invention is to provide the implement device of low-density parity check code, to reduce the required memory space of storage parity matrix.

For achieving the above object, technical scheme of the present invention specifically is achieved in that

The implementation method of low-density parity check code, this method may further comprise the steps:

A, heavy according to predefined code length, code check and row is provided for generating the Serial No. of parity matrix;

B, according to described Serial No., adopt the parity matrix of the mode constructing low-density parity code LDPC sign indicating number of cyclic shift;

C, utilize described parity matrix, will import data conversion is the LDPC code word.

Wherein, described step B can comprise:

B1, determine the line number and the columns of described parity matrix according to described code length and code check, construct a plurality of sub matrixs, the line number of described sub matrix is that sub matrix number/one, the columns of described parity matrix line number equates with described parity matrix columns;

B2, heavily described parity matrix evenly is divided into first row element in each sub matrix behind a plurality of sub matrixs by row according to described Serial No. and described row;

B3, described sub matrix evenly is divided into a plurality of submatrixs by row, and to make described each submatrix be a square formation;

B4, according to first row element of described each submatrix, adopt the mode of cyclic shift to obtain elements of other row in each submatrix.

Wherein, described step B2 can for:

Described Serial No. is divided into a plurality of digit groups that comprise heavy numeral of described row, element 1 residing columns in going as first of corresponding sub matrix with the numeral in each digit groups in the described Serial No..

Wherein, step B4 described cyclic shift can be ring shift left and/or ring shift right.

A length displacement unit matrix that wherein, can comprise described Serial No. in the described parity matrix.

Wherein, in the described Serial No., be used for determining that any two numerals of the first row element, 1 residing columns of described each sub matrix are different to the value of the line number delivery gained of described submatrix.

Wherein, when described LDPC sign indicating number is regular LDPC sign indicating number, and described code length is 4608, described code check is 1/2, described row heavily is 6 o'clock,

The length of described Serial No. is 192, described Serial No. can for:

9	212	384	2326	2803	3343
9	212	384	2326	2803	3343	140	264	465	2405	2870	3445
192	305	560	2449	2925	3494	140	264	465	2405	2870	3445
192	305	560	2449	2925	3494	233	367	617	2587	2989	3571
295	460	703	2654	3055	3632	233	367	617	2587	2989	3571
295	460	703	2654	3055	3632	388	514	732	2709	3157	3730
442	610	832	2773	3206	3764	388	514	732	2709	3157	3730
442	610	832	2773	3206	3764	538	650	910	2839	3283	3886
578	770	957	2941	3344	3906	538	650	910	2839	3283	3886
578	770	957	2941	3344	3906	698	855	1067	2990	3442	4031
783	924	1085	3067	3476	4043	698	855	1067	2990	3442	4031
783	924	1085	3067	3476	4043	852	949	1156	3128	3598	4148
877	1065	1259	3226	3618	4242	852	949	1156	3128	3598	4148
877	1065	1259	3226	3618	4242	993	1145	1335	3260	3743	4257
1073	1155	1393	3382	3755	4388	993	1145	1335	3260	3743	4257
1073	1155	1393	3382	3755	4388	1083	1246	1456	3402	3860	4440
1174	1325	1565	3527	3954	4481	1083	1246	1456	3402	3860	4440
1174	1325	1565	3527	3954	4481	1253	1369	1648	3539	3969	4543
1297	1507	1664	2342	3644	4100	1253	1369	1648	3539	3969	4543
1297	1507	1664	2342	3644	4100	1435	1574	1734	2419	3738	4152
1502	1629	1849	2480	3753	4193	1435	1574	1734	2419	3738	4152
1502	1629	1849	2480	3753	4193	1557	1693	1924	2578	3884	4255
1621	1759	1980	2612	3936	4348	1557	1693	1924	2578	3884	4255
1621	1759	1980	2612	3936	4348	1687	1861	2088	2734	3977	4402
1789	1910	2115	2754	4039	4498	1687	1861	2088	2734	3977	4402
1789	1910	2115	2754	4039	4498	1838	1987	2183	2879	4132	4538

1915	2048	2301	2324	2891	4186
1915	2048	2301	2324	2891	4186	4	1976	2146	2446	2996	4282
107	2074	2180	2466	3090	4322	4	1976	2146	2446	2996	4282
107	2074	2180	2466	3090	4322	183	2108	2302	2591	3105	4442
3	241	2230	2603	3236	4527	183	2108	2302	2591	3105	4442
3	241	2230	2603	3236	4527	94	304	2250	2708	3288	4596

The number of described sub matrix can be for 32, line number can be for 72, columns can be 4608;

The number of submatrix can be 64 in described each sub matrix;

Described submatrix can be the square formation of 72 row * 72 row;

Can comprise 192 displacement unit matrixs in the described parity matrix.

Wherein, when described LDPC sign indicating number is an irregular LDPC codes, and described code length is 4608, described code check is 1/2, described row heavily is 7 o'clock,

The length of described Serial No. is 224, described Serial No. can for:

923	970	2044	2100	2976	3359	4191
923	970	2044	2100	2976	3359	4191	136	288	1972	2422	2904	4243	4266
597	704	779	1048	2805	4274	4380	136	288	1972	2422	2904	4243	4266
597	704	779	1048	2805	4274	4380	454	632	918	976	3233	4365	4425
846	904	1007	1321	2688	4429	4484	454	632	918	976	3233	4365	4425
846	904	1007	1321	2688	4429	4484	653	832	1019	1119	3089	4495	4577
538	581	702	863	3017	3511	4597	653	832	1019	1119	3089	4495	4577
538	581	702	863	3017	3511	4597	429	1596	1745	1842	2945	3458	3576
558	616	755	803	2658	3571	3604	429	1596	1745	1842	2945	3458	3576
558	616	755	803	2658	3571	3604	486	544	683	1277	3197	3668	3682
659	800	889	1380	3125	3694	3765	486	544	683	1277	3197	3668	3682
659	800	889	1380	3125	3694	3765	587	687	2505	2567	3255	3800	3875
467	656	745	1482	3183	3850	3893	587	687	2505	2567	3255	3800	3875
467	656	745	1482	3183	3850	3893	443	543	1672	1942	3338	3942	4000

335	425	601	2295	3039	4031	4067
335	425	601	2295	3039	4031	4067	210	529	729	964	2765	4043	4143
628	773	824	1194	1558	3421	4112	210	529	729	964	2765	4043	4143
628	773	824	1194	1558	3421	4112	129	191	556	876	2238	2441	3273
513	908	953	2007	2085	2370	2875	129	191	556	876	2238	2441	3273
513	908	953	2007	2085	2370	2875	978	1240	1510	1548	1683	1742	3343
65	134	147	764	1751	2395	2834	978	1240	1510	1548	1683	1742	3343
65	134	147	764	1751	2395	2834	464	692	834	985	1366	1404	2985
3	913	2145	2207	2463	2587	3127	464	692	834	985	1366	1404	2985
3	913	2145	2207	2463	2587	3127	444	727	928	952	1222	1260	3137
303	476	618	769	1150	2652	3242	444	727	928	952	1222	1260	3137
303	476	618	769	1150	2652	3242	546	1116	1190	2251	2362	2637	2697
29	1590	1669	1857	2179	2355	2921	546	1116	1190	2251	2362	2637	2697
29	1590	1669	1857	2179	2355	2921	439	766	972	1046	1359	1518	3026
481	862	1650	1934	1947	2211	2869	439	766	972	1046	1359	1518	3026
481	862	1650	1934	1947	2211	2869	276	393	520	1862	1875	2139	3405
648	830	891	1381	1506	2551	2725	276	393	520	1862	1875	2139	3405
648	830	891	1381	1506	2551	2725	249	325	684	2045	2479	2738	3443

The number of submatrix can be 64 in described each sub matrix;

Described submatrix can be the square formation of 72 row * 72 row;

Can comprise 224 displacement unit matrix in the described parity matrix.

Wherein, when described LDPC sign indicating number is an irregular LDPC codes, and described code length is 4608, described code check is 43/64, described row heavily is 12 or 13 o'clock,

The length of described Serial No. is 256, described Serial No. can for:

536	1098	1156	1259	1889	2012	3529	3656	3739	3749	3907	3998
536	1098	1156	1259	1889	2012	3529	3656	3739	3749	3907	3998	100	322	977	1026	1672	1940	2994	3073	3457	3677	4207	4382
743	1868	3512	3595	3605	3697	3763	3854	3900	4072	4230	4310	100	322	977	1026	1672	1940	2994	3073	3457	3677	4207	4382

1199	1227	1429	3351	3523	3691	3782	3828	3895	4064	4150	4272
1199	1227	1429	3351	3523	3691	3782	3828	3895	4064	4150	4272		1079	2022	2173	2260	3194	3710	3823	3928	3992	4162	4389	4393
419	1362	1384	2475	2553	3547	3638	3856	4006	4090	4448	4531		1079	2022	2173	2260	3194	3710	3823	3928	3992	4162	4389	4393
419	1362	1384	2475	2553	3547	3638	3856	4006	4090	4448	4531		144	146	1580	1648	2212	3449	3612	3784	4018	4089	4124	4469	4561
502	1508	2140	2508	2757	2819	2909	2978	3494	3540	4127	4555		144	146	1580	1648	2212	3449	3612	3784	4018	4089	4124	4469	4561
502	1508	2140	2508	2757	2819	2909	2978	3494	3540	4127	4555		2	683	791	1313	2376	2991	3118	3183	3305	3468	3980	4055
611	719	767	795	997	3254	3568	3632	3802	3873	3983	4102	4145	2	683	791	1313	2376	2991	3118	3183	3305	3468	3980	4055
611	719	767	795	997	3254	3568	3632	3802	3873	3983	4102	4145	171	436	1169	1954	2052	2409	2693	2762	3496	3801	3836	4030
59	99	258	930	1053	1097	2531	2621	2690	2863	2902	3658		171	436	1169	1954	2052	2409	2693	2762	3496	3801	3836	4030
59	99	258	930	1053	1097	2531	2621	2690	2863	2902	3658		265	2090	2223	2282	2418	3271	3366	3502	3586	3657	3978	4036	4139
309	371	709	1374	1483	2331	3408	3514	3585	3695	3906	4067		265	2090	2223	2282	2418	3271	3366	3502	3586	3657	3978	4036	4139
309	371	709	1374	1483	2331	3408	3514	3585	3695	3906	4067		389	1666	1834	2079	2138	2337	2873	2894	3548	3892	4103	4151
809	932	1468	1564	1594	3670	3713	3762	3820	3923	4079	4107		389	1666	1834	2079	2138	2337	2873	2894	3548	3892	4103	4151
809	932	1468	1564	1594	3670	3713	3762	3820	3923	4079	4107		493	570	1267	1309	2607	2729	3078	3158	3381	3598	3851	3959	4007
30	242	327	856	2470	2535	3526	3618	3676	3779	3935	4165		493	570	1267	1309	2607	2729	3078	3158	3381	3598	3851	3959	4007
30	242	327	856	2470	2535	3526	3618	3676	3779	3935	4165		549	593	1123	1791	2606	2787	3048	3237	3451	3497	3546	3863
170	1584	1719	1778	1899	2415	3165	3743	3791	3819	3932	4120		549	593	1123	1791	2606	2787	3048	3237	3451	3497	3546	3863
170	1584	1719	1778	1899	2415	3165	3743	3791	3819	3932	4120		640	870	979	1647	1787	1827	2004	2253	3671	3719	3747	4026

The number of described sub matrix can be for 21, line number can be for 72, columns can be 4608;

The number of submatrix can be 64 in described each sub matrix;

Described submatrix can be the square formation of 72 row * 72 row;

Can comprise 256 displacement unit matrix in the described parity matrix.

Further, after described step B, can comprise: resulting parity matrix is carried out the rotation of various angles and/or carries out line replacement and/or carry out column permutation and/or change the position of described submatrix.

The implement device of low-density parity check code, this implement device comprises: memory module, check matrix generation module and code word generation module;

Described memory module is used to store Serial No., and provides described Serial No. to described check matrix generation module;

The described Serial No. that provides according to described memory module is provided described check matrix generation module, adopts the mode of cyclic shift to construct the parity matrix of LDPC sign indicating number, and described parity matrix is sent to described code word generation module;

Described code word generation module is used to receive the described parity matrix that comes from described check matrix generation module, and utilizes described parity matrix, and will import data conversion is the LDPC code word.

Further, described check matrix generation module can comprise: Serial No. analytic unit and cycle shift unit;

Described memory module is further used for providing described Serial No. to described Serial No. analytic unit;

Described Serial No. analytic unit, the described Serial No. that provides according to described memory module is provided, and the row of described LDPC sign indicating number is heavy, evenly divide described Serial No. and obtain a plurality of digit groups that comprise heavy numeral of described row, and, determine that with resulting each sub matrix of first row element sends to described cycle shift unit according to dividing resulting each digit groups, obtaining described parity matrix evenly is divided into first row element of each sub matrix behind a plurality of sub matrixs by row;

Described cycle shift unit, described each sub matrix that is used for coming from described Serial No. analytic unit evenly is divided into square formation by row, obtain the submatrix of determining first row element of described parity matrix, and according to first row element of described each submatrix, adopt the mode of cyclic shift to obtain described each submatrix, described each submatrix constitutes described parity matrix, and described parity matrix is sent to described code word generation module.

Further, can comprise in the described implement device: the check matrix converter unit;

Described cycle shift unit is further used for described parity matrix is sent to described check matrix converter unit;

Described check matrix converter unit, be used for described parity matrix is carried out the rotation of various angles and/or carries out line replacement and/or carry out column permutation and/or change the position of described submatrix, and will send to described code word generation module through the resulting parity matrix of described conversion.

As seen from the above technical solution, the implementation method of a class LDPC sign indicating number of the present invention and device have adopted with Serial No. to be represented parity matrix and digital sequence cyclic shift is obtained the mode of parity matrix, makes the required memory space of storage parity matrix reach and minimizes.

In addition, because parity matrix of the present invention has quasi-cyclic architectural characteristic, make in actual applications, can utilize the characteristic of cyclic shift to realize immediate addressing, save and handle resource, simplify coding and decoded operation, the complexity of coding and decoded operation is minimized.

Description of drawings

Fig. 1 is the structural representation of existing LDPC encoder.

Fig. 2 is the exemplary process diagram of the implementation method of the present invention's one class LDPC sign indicating number.

Fig. 3 is the performance curve schematic diagram that (4608,2304) regular QC-LDPC sign indicating number adopts the BPSK modulation in the embodiment of the invention one in awgn channel.

Fig. 4 is the BER performance curve schematic diagram that (4608,2304) regular QC-LDPC sign indicating number is modulated at employing 8DPSK in the awgn channel of T-MMB system in the embodiment of the invention one.

Fig. 5 is the performance curve schematic diagram that (4608,2304) non-regular QC-LDPC sign indicating number adopts the BPSK modulation in the embodiment of the invention two in awgn channel.

Fig. 6 is the performance curve schematic diagram that (4608,3096) non-regular QC-LDPC sign indicating number adopts the BPSK modulation in the embodiment of the invention three in awgn channel.

Fig. 7 is the structural representation of the implement device of QC-LDPC sign indicating number in the embodiment of the invention four.

Embodiment

For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.

Main thought of the present invention is heavy according to predefined code length, code check and row, be provided for generating the Serial No. of parity matrix, construct the parity matrix of LDPC sign indicating number then with accurate circulation (QC:Quasi Cyclic) structure according to the mode of Serial No., employing cyclic shift, with resulting parity matrix the input data are carried out conversion again, obtain comprising the LDPC code word of parity information.So, only need to solve the excessive problem of parity matrix memory space with very small amount of memory space storage Serial No..

Fig. 2 is the exemplary process diagram of the implementation method of the present invention's one class LDPC sign indicating number.Referring to Fig. 2, this method may further comprise the steps:

Step 201: weigh according to predefined code length, code check and row, be provided for generating the Serial No. of parity matrix.

In this example, weigh according to predefined code length, code check and row, determine the line number and the columns of the parity matrix that this example will be constructed, wherein, line number is the code length of LDPC sign indicating number, is expressed as N; Columns is a check digit length, is expressed as M, and the parity check matrix H of the hypothesis QC-LDPC sign indicating number of the present invention of being constructed is shown in (1):

(1) in, A _{I, j}Be t capable * circular matrix of t row, be called the submatrix of parity check matrix H, because A _{I, j}Be circular matrix, also can be referred to as the circulation submatrix of parity check matrix H, so parity check matrix H of the present invention has accurate loop structure, so the LDPC sign indicating number that the present invention constructed is called the QC-LDPC sign indicating number.

Line number and columns according to above-mentioned definite parity check matrix H are constructed a plurality of sub matrixs, the line number of feasible sub matrix of being constructed is that sub matrix number/one, the columns of the line number of matrix H equates with the columns of matrix H, and each sub matrix that order is constructed is corresponding with each the row circulation submatrix in the above-mentioned matrix H, promptly each sub matrix can be expressed as:

A _i＝[A _i，1，A _i，2…，A _i，c] (i＝1，2，…，u) (2)

Wherein, the number u=N/t of sub matrix, the number c=M/t of submatrix in the sub matrix.Set Serial No. is used for determining the first row element, the 1 residing columns of each sub matrix in this step, has also promptly obtained the row of first in each sub matrix, therefore, this Serial No. can be called the capable create-rule of parity matrix.Here, the check matrix of constructing in order to guarantee is sparse, any two elements, 1 residing columns should be different to the value of t delivery gained in each row, therefore, in set Serial No., be used for determining that any two numerals of the first row element, 1 residing columns of each sub matrix are different to the value of t delivery gained.

For regular LDPC sign indicating number and row heavy phase irregular LDPC codes together, if represent the number that row is heavy, u represents sub matrix in the check matrix with ρ, because element 1 residing columns in first row of the sub matrix of every ρ digitized representation in this Serial No., therefore, this Serial No. is made up of ρ * u numeral, with respect to M * N, required memory space is greatly reduced; For the heavy irregular LDPC codes inequality of row, though its row is heavy uncertain,, the digital number that is comprised in this Serial No. mostly is the heavy maximum of row most and amasss with u is, and therefore, with respect to M * N, its required memory space also will greatly be reduced.

Step 202: according to set Serial No., the mode of employing cyclic shift is constructed the parity matrix of LDPC sign indicating number.

In this step, at first determine first row element in each sub matrix according to Serial No.; Then each sub matrix evenly is divided into c submatrix by row, makes that each submatrix is a square formation, here, c is identical with the physical meaning of the described c of step 201; At last, according to first row element of each submatrix, adopt the mode of cyclic shift to obtain other elements of going in the whole submatrix, be circulation submatrix of the present invention, so, the parity matrix of QC-LDPC sign indicating number in this example that obtains constituting by each circulation submatrix.Suppose that the Serial No. that set being used to generates parity matrix comprises y numeral, because in this Serial No., any two numerals of the first row element, 1 residing columns that are used for determining each sub matrix are different to the value of t delivery gained, therefore, has only an element 1 at the most in each row of each circulation submatrix, so, comprise y circulation submatrix that contains element 1 in the resulting check matrix, by the character of matrix as can be known, these circulation submatrixs that contain element 1 are displacement unit matrix.

In this step, obtain after the parity matrix, can be to its any conversion of carrying out rotation, line replacement, the column permutation of various angles or changing circulation submatrix position.

Step 203: utilize resulting parity matrix, will import data conversion is the LDPC code word.

In this step, obtain after the parity matrix, can encode to the input data, obtain comprising the dateout of parity information according to mode same as the prior art.

So far, finish the exemplary flow of the implementation method of the quasi-cyclic LDPC sign indicating number of the present invention's one class.

In actual applications, after will interweaving, modulate through QC-LDPC implementation method encoded data of the present invention, can outwards launch.Here, modulation system can comprise: quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude phase shift keying (APSK), differential phase keying (DPSK) (DPSK), absolute phase shift keying (BPSK), differential amplitude phase shift keying (DAPSK) and OFDM (OFDM) etc.Modulation signal can transmit by various communication systems, comprise terrestrial links of supporting Mobile Multimedia Broadcasting etc., for example: can transmit by ground mobile multimedia broadcasting system (T-MMB:Terrestrial Mobile Multimedia Broadcasting).

The present invention goes for regular LDPC sign indicating number and irregular LDPC codes, below by four embodiment, technical solution of the present invention is elaborated.

Embodiment one:

Present embodiment is that example describes with rule (4608,2304) LDPC sign indicating number.The code length N of the regular LDPC sign indicating number that present embodiment will be realized is 4608, the heavy ρ of row=6, code check v=1/2.By the corresponding relation between code check, code length and the check equations number as can be known, check equations number M=4608-2304=2304 in the present embodiment check matrix.In addition, in the present embodiment, will be that minimal circulation unit is the implementation procedure that example illustrates above-mentioned quasi-cyclic LDPC code with the circulation submatrix of 72 row * 72 row.

Present embodiment method flow diagram and exemplary method flowchart of the present invention shown in Figure 2 are similar, and referring to Fig. 2, the implementation method of QC-LDPC sign indicating number may further comprise the steps in the present embodiment:

In step 201, heavy according to the code length that sets in advance in the present embodiment, code check and row, Serial No. is set, as follows:

9	212	384	2326	2803	3343
9	212	384	2326	2803	3343	140	264	465	2405	2870	3445
192	305	560	2449	2925	3494	140	264	465	2405	2870	3445
192	305	560	2449	2925	3494	233	367	617	2587	2989	3571
295	460	703	2654	3055	3632	233	367	617	2587	2989	3571
295	460	703	2654	3055	3632	388	514	732	2709	3157	3730
442	610	832	2773	3206	3764	388	514	732	2709	3157	3730
442	610	832	2773	3206	3764	538	650	910	2839	3283	3886
578	770	957	2941	3344	3906	538	650	910	2839	3283	3886
578	770	957	2941	3344	3906	698	855	1067	2990	3442	4031

783	924	1085	3067	3476	4043
783	924	1085	3067	3476	4043	852	949	1156	3128	3598	4148
877	1065	1259	3226	3618	4242	852	949	1156	3128	3598	4148
877	1065	1259	3226	3618	4242	993	1145	1335	3260	3743	4257
1073	1155	1393	3382	3755	4388	993	1145	1335	3260	3743	4257
1073	1155	1393	3382	3755	4388	1083	1246	1456	3402	3860	4440
1174	1325	1565	3527	3954	4481	1083	1246	1456	3402	3860	4440
1174	1325	1565	3527	3954	4481	1253	1369	1648	3539	3969	4543
1297	1507	1664	2342	3644	4100	1253	1369	1648	3539	3969	4543
1297	1507	1664	2342	3644	4100	1435	1574	1734	2419	3738	4152
1502	1629	1849	2480	3753	4193	1435	1574	1734	2419	3738	4152
1502	1629	1849	2480	3753	4193	1557	1693	1924	2578	3884	4255
1621	1759	1980	2612	3936	4348	1557	1693	1924	2578	3884	4255
1621	1759	1980	2612	3936	4348	1687	1861	2088	2734	3977	4402
1789	1910	2115	2754	4039	4498	1687	1861	2088	2734	3977	4402
1789	1910	2115	2754	4039	4498	1838	1987	2183	2879	4132	4538
1915	2048	2301	2324	2891	4186	1838	1987	2183	2879	4132	4538
1915	2048	2301	2324	2891	4186	4	1976	2146	2446	2996	4282
107	2074	2180	2466	3090	4322	4	1976	2146	2446	2996	4282
107	2074	2180	2466	3090	4322	183	2108	2302	2591	3105	4442
3	241	2230	2603	3236	4527	183	2108	2302	2591	3105	4442
3	241	2230	2603	3236	4527	94	304	2250	2708	3288	4596

Be convenient and describe, the Serial No. of above-mentioned present embodiment is called Serial No. one.Referring to Serial No. one, each row in this sequence represent a sub matrix first capable in element 1 residing columns.

Because the row of LDPC sign indicating number heavily is 6 in the present embodiment, therefore, there are 6 elements 1 in first row of each sub matrix, promptly having 6 values is 1 row; In addition, because the circulation submatrix of parity matrix is 72 * 72 matrix in the present embodiment, and the number of check equations is 2304, therefore, the number u=2304/72=32 of sub matrix is individual in the parity matrix, so the Serial No. one in the present embodiment is the sequence that=192 numerals of 32 row * 6 row are formed.Wherein, per 6 numerals are one group, represented a sub matrix first the row in element 1 residing columns; Each any two numeral of organizing in 6 digit groups is different to the value of 72 delivery gained, to have only one 1 at most in the same delegation that guarantees each circulation submatrix, guarantees that promptly parity matrix is sparse.

In step 202, according to set Serial No. one, the mode of employing cyclic shift is constructed the parity matrix of LDPC sign indicating number.

In this step, construct the parity matrix of LDPC sign indicating number according to following step:

The 1st step evenly was divided into a plurality of digit groups that comprise heavy numeral of row with Serial No. one, and with the numeral in each digit groups in the Serial No. one as element 1 residing columns in first row of corresponding sub matrix.Promptly, with the numeral in the first digit group in the Serial No. one as first sub matrix first the row in element 1 residing columns, with the numeral in the second digit group in the Serial No. one as second sub matrix first the row in element 1 residing columns, the rest may be inferred, element 1 residing columns in going as first of last sub matrix with the numeral in last digit groups in the Serial No. one.

Particularly, Serial No. one evenly is divided into a plurality of digit groups that comprise 6 numerals, according to the numeral in resulting each digit groups, i.e. numeral in each shown in digital sequence one row obtains first row element of each sub matrix of parity matrix:

For example, shown in digital sequence one, its first digit group is 9,212,384,2326,2803 and 3343, first row of first sub matrix in the expression parity matrix, be that the 9th during first of parity matrix is gone is listed as, the 212nd row, the 384th are listed as, the 2326th row, the 2803rd are listed as and the 3343rd value that is listed as is 1, all the other in first row of first sub matrix classify 0 as;

Its second digit group is 140,264,465,2405,2870 and 3445, first row of second sub matrix of expression parity matrix, be that the 140th during the 73rd of parity matrix is gone is listed as, the 264th row, the 465th are listed as, the 2405th row, the 2870th are listed as and the 3445th value that is listed as is 1, in first row of second sub matrix all the other classify 0 as, first value of going for other sub matrixs, can obtain with reference to analogizing for example, not repeat them here.

In the 2nd step, each sub matrix of determining the first row value evenly is divided into c submatrix by row; Here, because the circulation submatrix of parity matrix is 72 * 72 matrix in the present embodiment, and code length is 4608, therefore, and in each sub matrix the number c=4608/72=64 of circulation submatrix; After dividing, the parity matrix of present embodiment will be divided into=2048 circulation submatrixs of 32 row * 64 row, and the value of first row element of each circulation submatrix is determined.

In the 3rd step,, adopt the value that the mode of its first row element cyclic shift is obtained other row elements in this circulation submatrix at each circulation submatrix.For example, can obtain the 2nd row element to the 1st row element ring shift left x position; To the 2nd row element ring shift left x position, obtain the 3rd row element, the rest may be inferred, can obtain the value from the 2nd row to all elements of the 72nd row.Here, can certainly take ring shift right or other cyclic shift modes to be shifted.

Above-mentioned the 1st step of process can obtain the parity matrix of regular QC-LDPC sign indicating number in the present embodiment to the operation in the 3rd step.Owing to there are=192 numerals of 32 row * 6 row in the present embodiment Serial No., and, any two numerals in each digit groups are different to the value of 72 delivery gained, guaranteed to have only one 1 at most in the same delegation of each circulation submatrix, therefore, will there be 192 displacement unit matrixs in the resulting parity matrix of present embodiment.

In step 203, utilize resulting parity matrix according to mode same as the prior art, will import data conversion is the LDPC code word.

So far, finish the exemplary flow of the implementation method of QC-LDPC sign indicating number in the embodiment of the invention one.

As seen from the above-described embodiment, the present invention has adopted with Serial No. and has represented parity matrix and digital sequence cyclic shift is obtained the mode of parity matrix, makes the required memory space of storage parity matrix reach and minimizes.

In addition, because the parity matrix of present embodiment has quasi-cyclic architectural characteristic, make in actual applications, can utilize the characteristic of cyclic shift to realize immediate addressing, save and handle resource, simplify coding and decoded operation, the complexity of coding and decoded operation is minimized.

Contrast below by emulation, the performance of (4608,2304) the regular QC-LDPC sign indicating number that is provided in the embodiment of the invention one is described with prior art.Fig. 3 is the performance curve schematic diagram that (4608,2304) regular QC-LDPC sign indicating number adopts the BPSK modulation in the embodiment of the invention one in awgn channel.In this emulation, the sum-product algorithm is adopted in decoding, and maximum iteration time is 50.

Referring to Fig. 3, wherein, straight line 301 expression shannon limits;

Curve 302 expression adopts that the regular QC-LDPC sign indicating number of the present invention (4608,2304) is encoded, the BPSK mode is modulated, transmission in additive white Gaussian noise (AWGN) channel then, and adopt and bit error rate (BER) curve of the signal that long-pending decoding algorithm (SPA:Sum-Product Arithmetic) is deciphered;

Curve 303 expression adopts that the regular QC-LDPC sign indicating number of the present invention (4608,2304) is encoded, the BPSK mode is modulated, transmission and adopt frame error rate (BLER) curve of the signal that the SPA algorithm deciphers in awgn channel then;

Curve 304 expression un-encoded directly adopt the BPSK modulation, again the signal BER performance curve that transmits through awgn channel;

As seen from Figure 3, (error floor) is very low at the bottom of the basin of the regular QC-LDPC sign indicating number of the present invention (4608,2304), and, at BER=10 ^-9The place, its performance curve is apart from shannon limit 1.9dB only.

(4608,2304) that present embodiment provided regular QC-LDPC sign indicating number is applied to the awgn channel of T-MMB system, and adopts that the 8DPSK mode is modulated, the SPA algorithm is deciphered, with the BER performance curve that obtains as shown in Figure 4.Referring to Fig. 4, curve shown in the figure is in the awgn channel of T-MMB system, and the regular QC-LDPC sign indicating number of employing the present invention (4608,2304) is encoded, the 8DPSK mode is modulated and adopt the SPA algorithm to decipher signal BER performance curve afterwards.

In the foregoing description one, to the present invention (4608,2304) embodiment of the implementation method of regular QC-LDPC sign indicating number has been described in detail, and among two following embodiment, will the embodiment of the implementation method of the non-regular QC-LDPC sign indicating number of the present invention be elaborated.

Embodiment two:

Present embodiment is that example describes with (4608,2304) row heavy phase irregular LDPC codes together.The code length N of the regular LDPC sign indicating number that present embodiment will be realized is 4608, the heavy ρ of row=7, code check v=1/2, by the corresponding relation between code check, code length and the check equations number as can be known, check equations number M=4608-2304=2304 in the present embodiment check matrix.In addition, identical with embodiment one in the present embodiment, the circulation submatrix with 72 * 72 is that minimal circulation unit is the implementation procedure that example illustrates above-mentioned quasi-cyclic LDPC code.

923	970	2044	2100	2976	3359	4191
923	970	2044	2100	2976	3359	4191	136	288	1972	2422	2904	4243	4266
597	704	779	1048	2805	4274	4380	136	288	1972	2422	2904	4243	4266
597	704	779	1048	2805	4274	4380	454	632	918	976	3233	4365	4425
846	904	1007	1321	2688	4429	4484	454	632	918	976	3233	4365	4425
846	904	1007	1321	2688	4429	4484	653	832	1019	1119	3089	4495	4577
538	581	702	863	3017	3511	4597	653	832	1019	1119	3089	4495	4577
538	581	702	863	3017	3511	4597	429	1596	1745	1842	2945	3458	3576
558	616	755	803	2658	3571	3604	429	1596	1745	1842	2945	3458	3576
558	616	755	803	2658	3571	3604	486	544	683	1277	3197	3668	3682
659	800	889	1380	3125	3694	3765	486	544	683	1277	3197	3668	3682
659	800	889	1380	3125	3694	3765	587	687	2505	2567	3255	3800	3875
467	656	745	1482	3183	3850	3893	587	687	2505	2567	3255	3800	3875
467	656	745	1482	3183	3850	3893	443	543	1672	1942	3338	3942	4000
335	425	601	2295	3039	4031	4067	443	543	1672	1942	3338	3942	4000
335	425	601	2295	3039	4031	4067	210	529	729	964	2765	4043	4143
628	773	824	1194	1558	3421	4112	210	529	729	964	2765	4043	4143
628	773	824	1194	1558	3421	4112	129	191	556	876	2238	2441	3273
513	908	953	2007	2085	2370	2875	129	191	556	876	2238	2441	3273
513	908	953	2007	2085	2370	2875	978	1240	1510	1548	1683	1742	3343
65	134	147	764	1751	2395	2834	978	1240	1510	1548	1683	1742	3343
65	134	147	764	1751	2395	2834	464	692	834	985	1366	1404	2985

3	913	2145	2207	2463	2587	3127
3	913	2145	2207	2463	2587	3127	444	727	928	952	1222	1260	3137
303	476	618	769	1150	2652	3242	444	727	928	952	1222	1260	3137
303	476	618	769	1150	2652	3242	546	1116	1190	2251	2362	2637	2697
29	1590	1669	1857	2179	2355	2921	546	1116	1190	2251	2362	2637	2697
29	1590	1669	1857	2179	2355	2921	439	766	972	1046	1359	1518	3026
481	862	1650	1934	1947	2211	2869	439	766	972	1046	1359	1518	3026
481	862	1650	1934	1947	2211	2869	276	393	520	1862	1875	2139	3405
648	830	891	1381	1506	2551	2725	276	393	520	1862	1875	2139	3405
648	830	891	1381	1506	2551	2725	249	325	684	2045	2479	2738	3443

Be convenient and describe, the Serial No. of above-mentioned present embodiment is called Serial No. two.Referring to Serial No. two, each row in this sequence represent a sub matrix first capable in element 1 residing columns.

Because the row of LDPC sign indicating number heavily is 7 in the present embodiment, therefore, there are 7 elements 1 in first row of each sub matrix, promptly having 7 values is 1 row; In addition, because the circulation submatrix of parity matrix is 72 * 72 matrix in the present embodiment, and the number of check equations is 2304, therefore, the number u=2304/72=32 of sub matrix is individual in the parity matrix, so the Serial No. two in the present embodiment is the sequence that=244 numerals of 32 row * 7 row are formed.Wherein, per 7 numerals are one group, represented a sub matrix first the row in element 1 residing columns; Each any two numeral of organizing in 7 digit groups is different to the value of 72 delivery gained, to have only one 1 at most in the same delegation that guarantees each circulation submatrix, guarantees that promptly parity matrix is sparse.

In step 202, according to set Serial No. two, the mode of employing cyclic shift is constructed the parity matrix of LDPC sign indicating number.

The 1st step, Serial No. two evenly is divided into a plurality of digit groups that comprise 7 numerals, according to the numeral in resulting each digit groups, i.e. numeral in each shown in digital sequence two row obtains first row element of each sub matrix of parity matrix:

For example, shown in digital sequence two, its first digit group is 923,970,2044,2100,2976,3359 and 4191, first row of first sub matrix in the expression parity matrix, be parity matrix first the row in the 923rd row, the 970th row, the 2044th row, the 2100th row, the 2976th row, the 3359th row and the 4191st row value be 1, first sub matrix first the row in all the other classify 0 as;

Its second digit group is 136,288,1972,2422,2904,4243 and 4266, first row of second sub matrix of expression parity matrix, be parity matrix the 73rd the row in the 136th row, the 288th row, the 1972nd row, the 2422nd row, the 2904th row, the 4243rd row and the 4266th row value be 1, in first row of second sub matrix all the other classify 0 as, first value of going for other sub matrixs, can obtain with reference to analogizing for example, not repeat them here.

Above-mentioned the 1st step of process can obtain the parity matrix of non-regular QC-LDPC sign indicating number in the present embodiment to the operation in the 3rd step.Owing to there are=224 numerals of 32 row * 7 row in the present embodiment Serial No., and, any two numerals in each digit groups are different to the value of 72 delivery gained, guaranteed to have only one 1 at most in the same delegation of each circulation submatrix, therefore, will there be 224 displacement unit matrixs in the resulting parity matrix of present embodiment.

So far, finish the exemplary flow of the implementation method of QC-LDPC sign indicating number in the embodiment of the invention two.

And,, make in actual applications because the parity matrix of present embodiment has quasi-cyclic architectural characteristic, can utilize the characteristic of cyclic shift to realize immediate addressing, saved the processing resource, simplified coding and decoded operation, the complexity of coding and decoded operation is minimized.

Contrast below by emulation, the performance of (4608,2304) the non-regular QC-LDPC sign indicating number that is provided in the embodiment of the invention two is described with prior art.Fig. 5 is the performance curve schematic diagram that (4608,2304) non-regular QC-LDPC sign indicating number adopts the BPSK modulation in the embodiment of the invention two in awgn channel.In this emulation, the SPA algorithm is adopted in decoding, and maximum iteration time is 50.

Referring to Fig. 5, wherein, straight line 501 expression shannon limits;

The signal BER curve that the non-regular QC-LDPC sign indicating number of the present invention (4608,2304) is encoded, the BPSK mode is modulated, transmit and adopt the SPA algorithm to decipher is then adopted in curve 502 expressions in awgn channel;

Curve 503 expression adopts that the non-regular QC-LDPC sign indicating number of the present invention (4608,2304) is encoded, the BPSK mode is modulated, then in awgn channel transmission and adopt that the SPA algorithm deciphers the BLER curve of signal;

Curve 504 expression un-encoded directly adopt the BPSK modulation, again the signal BER performance curve that transmits through awgn channel;

As seen from Figure 5, the error floor of the non-regular QC-LDPC sign indicating number of the present invention (4608,2304) is very low, and, at BER=10 ^-9The place, its performance curve is apart from shannon limit 1.6dB only, and is more excellent than the performance of (4608,2304) the regular QC-LDPC sign indicating number that is provided in the embodiment of the invention one.

In the foregoing description two, with go heavy phase with non-regular QC-LDPC sign indicating number be example, describe technical solution of the present invention in detail, below again by a heavy LDPC sign indicating number example inequality of row, the implementation method of the non-regular QC-LDPC sign indicating number of the present invention is introduced.

Embodiment three:

Present embodiment is that example describes with the heavy irregular LDPC codes inequality of (4608,3096) row.The code length N of the regular LDPC sign indicating number that present embodiment will be realized is 4608, the heavy ρ of row=12 or 13, code check v=43/64, by the corresponding relation between code check, code length and the check equations number as can be known, check equations number M=4608-3096=1512 in the present embodiment check matrix.In addition, identical with embodiment one in the present embodiment, the circulation submatrix with 72 * 72 is that minimal circulation unit is the implementation procedure that example illustrates above-mentioned quasi-cyclic LDPC code.

536	1098	1156	1259	1889	2012	3529	3656	3739	3749	3907	3998
536	1098	1156	1259	1889	2012	3529	3656	3739	3749	3907	3998		100	322	977	1026	1672	1940	2994	3073	3457	3677	4207	4382
743	1868	3512	3595	3605	3697	3763	3854	3900	4072	4230	4310		100	322	977	1026	1672	1940	2994	3073	3457	3677	4207	4382
743	1868	3512	3595	3605	3697	3763	3854	3900	4072	4230	4310		1199	1227	1429	3351	3523	3691	3782	3828	3895	4064	4150	4272
1079	2022	2173	2260	3194	3710	3823	3928	3992	4162	4389	4393		1199	1227	1429	3351	3523	3691	3782	3828	3895	4064	4150	4272
1079	2022	2173	2260	3194	3710	3823	3928	3992	4162	4389	4393		419	1362	1384	2475	2553	3547	3638	3856	4006	4090	4448	4531
144	146	1580	1648	2212	3449	3612	3784	4018	4089	4124	4469	4561	419	1362	1384	2475	2553	3547	3638	3856	4006	4090	4448	4531
144	146	1580	1648	2212	3449	3612	3784	4018	4089	4124	4469	4561	502	1508	2140	2508	2757	2819	2909	2978	3494	3540	4127	4555
2	683	791	1313	2376	2991	3118	3183	3305	3468	3980	4055		502	1508	2140	2508	2757	2819	2909	2978	3494	3540	4127	4555
2	683	791	1313	2376	2991	3118	3183	3305	3468	3980	4055		611	719	767	795	997	3254	3568	3632	3802	3873	3983	4102	4145
171	436	1169	1954	2052	2409	2693	2762	3496	3801	3836	4030		611	719	767	795	997	3254	3568	3632	3802	3873	3983	4102	4145
171	436	1169	1954	2052	2409	2693	2762	3496	3801	3836	4030		59	99	258	930	1053	1097	2531	2621	2690	2863	2902	3658
265	2090	2223	2282	2418	3271	3366	3502	3586	3657	3978	4036	4139	59	99	258	930	1053	1097	2531	2621	2690	2863	2902	3658
265	2090	2223	2282	2418	3271	3366	3502	3586	3657	3978	4036	4139	309	371	709	1374	1483	2331	3408	3514	3585	3695	3906	4067
389	1666	1834	2079	2138	2337	2873	2894	3548	3892	4103	4151		309	371	709	1374	1483	2331	3408	3514	3585	3695	3906	4067
389	1666	1834	2079	2138	2337	2873	2894	3548	3892	4103	4151		809	932	1468	1564	1594	3670	3713	3762	3820	3923	4079	4107
493	570	1267	1309	2607	2729	3078	3158	3381	3598	3851	3959	4007	809	932	1468	1564	1594	3670	3713	3762	3820	3923	4079	4107
493	570	1267	1309	2607	2729	3078	3158	3381	3598	3851	3959	4007	30	242	327	856	2470	2535	3526	3618	3676	3779	3935	4165
549	593	1123	1791	2606	2787	3048	3237	3451	3497	3546	3863		30	242	327	856	2470	2535	3526	3618	3676	3779	3935	4165

170	1584	1719	1778	1899	2415	3165	3743	3791	3819	3932	4120
170	1584	1719	1778	1899	2415	3165	3743	3791	3819	3932	4120		640	870	979	1647	1787	1827	2004	2253	3671	3719	3747	4026

Be convenient and describe, the Serial No. of above-mentioned present embodiment is called Serial No. three.Referring to Serial No. three, each row in this sequence represent a sub matrix first capable in element 1 residing columns.

Because the row of LDPC sign indicating number heavily is 12 or 13 in the present embodiment, therefore, there are 12 or 13 elements 1 in first row of each sub matrix, promptly having 12 or 13 values is 1 row, according to Serial No. three, having 17 row in the present embodiment heavily is that 12 sub matrix, 4 row heavily are 13 sub matrix; In addition, because the circulation submatrix of parity matrix is 72 * 72 matrix in the present embodiment, and the number of check equations is 1512, therefore, the number u=1512/72=21 of sub matrix is individual in the parity matrix, so the Serial No. three in the present embodiment is the sequence that=256 numerals of 17 row * 12 row+4 row * 13 row are formed.Wherein, per 12 or 13 numerals are one group, have represented element 1 residing columns in first row of a sub matrix; The difference of any two numerals in 12 or 13 digit groups of each group is different to the value of 72 delivery gained, to have only one 1 at most in the same delegation that guarantees each circulation submatrix, guarantees that promptly parity matrix is sparse.

In step 202, according to set Serial No. three, the mode of employing cyclic shift is constructed the parity matrix of LDPC sign indicating number.

The 1st goes on foot, and Serial No. three is divided into a plurality of digit groups that comprise heavy numeral of row, and according to the numeral in resulting each digit groups, promptly each shown in digital sequence three is gone, and obtains first row element of each sub matrix of parity matrix:

For example, shown in digital sequence three, its first digit group is 536,1098,1156,1259,1889,2012,3529,3656,3739,3749,3907 and 3998, first row of first sub matrix in the expression parity matrix, be parity matrix first the row in the 536th row, the 1098th row, the 1156th row, the 1259th row, the 1889th row, the 2012nd row, the 3529th row, the 3656th row, the 3739th row, the 3749th row, the 3907th row and the 3998th row value be 1, first sub matrix first the row in all the other classify 0 as; First value of going for other sub matrixs can obtain with reference to analogizing for example, does not repeat them here.

Above-mentioned the 1st step of process can obtain the parity matrix of non-regular QC-LDPC sign indicating number in the present embodiment to the operation in the 3rd step.Owing to there are 256 numerals in the present embodiment Serial No., and, any two numerals in each digit groups are different to the value of 72 delivery gained, guaranteed to have only one 1 at most in the same delegation of each circulation submatrix, therefore, will there be 256 displacement unit matrixs in the resulting parity matrix of present embodiment.

So far, finish the exemplary flow of the implementation method of QC-LDPC sign indicating number in the embodiment of the invention three.

In addition, because the parity matrix of present embodiment has quasi-cyclic architectural characteristic, make in actual applications, can utilize the characteristic of cyclic shift to realize immediate addressing, saved the processing resource, simplified coding and decoded operation, the complexity of coding and decoded operation is minimized.

Contrast below by emulation, the performance of (4608,3096) the non-regular QC-LDPC sign indicating number that is provided in the embodiment of the invention three is described with prior art.Fig. 6 is the performance curve schematic diagram that (4608,3096) non-regular QC-LDPC sign indicating number adopts the BPSK modulation in the embodiment of the invention three in awgn channel.In this emulation, the sum-product algorithm is adopted in decoding, and maximum iteration time is 50.

Referring to Fig. 6, wherein, straight line 601 expression shannon limits;

The signal BER curve that the non-regular QC-LDPC sign indicating number of the present invention (4608,3096) is encoded, the BPSK mode is modulated, transmit and adopt the SPA algorithm to decipher is then adopted in curve 602 expressions in awgn channel;

Curve 603 expression adopts that the non-regular QC-LDPC sign indicating number of the present invention (4608,3096) is encoded, the BPSK mode is modulated, transmission and adopt the BLER curve of the signal that the SPA algorithm deciphers in awgn channel then;

Curve 604 expression un-encoded directly adopt the BPSK modulation, again the signal BER performance curve that transmits through awgn channel;

As seen from Figure 6, the error floor of the non-regular QC-LDPC sign indicating number of the present invention (4608,3096) is very low, and, at BER=10 ^-9The place, its performance curve apart from shannon limit less than 1.5dB, more excellent than the performance of (4608,2304) non-regular QC-LDPC sign indicating number of being realized in the embodiment of the invention two.

Implementation method to QC-LDPC sign indicating number of the present invention has been described in detail in the above embodiments, and the embodiment of the encoder of QC-LDPC sign indicating number of the present invention is described below by an encoder instances.

Embodiment four:

Fig. 7 is the structural representation of the implement device of QC-LDPC sign indicating number in the embodiment of the invention four.Referring to Fig. 7, this implement device comprises: memory module 710, check matrix generation module 720 and code word generation module 730 wherein, further comprise in the check matrix generation module 720: Serial No. analytic unit 721 and cycle shift unit 722.

In the implement device shown in Figure 7, memory module 710 is used to store Serial No., and the Serial No. that provides it to store of the Serial No. analytic unit 721 in check matrix generation module 720;

Serial No. analytic unit 721 in the check matrix generation module 720, the Serial No. that provided according to memory module 710 is provided, and the row of LDPC sign indicating number is heavy, evenly divide Serial No. and obtain a plurality of digit groups that comprise heavy numeral of described row, and according to dividing resulting each Serial No., obtain parity matrix evenly is divided into first row element of each sub matrix behind a plurality of sub matrixs by row, and each sub matrix that will resulting definite first row element sends to the cycle shift unit 722 in the check matrix generation module 720;

Cycle shift unit 722 in the check matrix generation module 720, each sub matrix that is used for coming from Serial No. analytic unit 721 evenly is divided into square formation by row, obtain the submatrix of determining first row element of this parity matrix, and according to first row element of each submatrix, adopt the mode of cyclic shift to obtain each submatrix, here, each submatrix has promptly constituted the parity matrix in the present embodiment, and this parity matrix is sent to code word generation module 730;

Code word generation module 730 is used for receiving the parity matrix of the cycle shift unit 722 that comes from check matrix generation module 720, and utilizes this parity matrix, and will import data conversion is the LDPC code word.

In implement device shown in Figure 7, may further include: the check matrix converter unit, this check matrix converter unit, the parity matrix that can be used for that cycle shift unit 722 is obtained carries out the various conversion such as rotation, line replacement, column permutation or change submatrix position of various angles, will send to code word generation module 730 through the resulting parity matrix of conversion then.

This check matrix converter unit can be separately set in the implement device of present embodiment, also can be arranged in the check matrix generation module 720, perhaps also can be arranged among other modules.

The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.All any modifications of being done within the spirit and principles in the present invention, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1, the implementation method of low-density parity check code is characterized in that, this method may further comprise the steps:

2, implementation method according to claim 1 is characterized in that, described step B comprises:

B2, heavily determine first row element in each sub matrix in described a plurality of sub matrixs according to described Serial No. and described row;

B3, described each sub matrix evenly is divided into a plurality of submatrixs by row, and to make described each submatrix be a square formation;

3, method according to claim 2 is characterized in that, described step B2 is:

4, method according to claim 2 is characterized in that, the described cyclic shift of step B4 is: ring shift left and/or ring shift right.

5, method according to claim 2 is characterized in that, comprises a length displacement unit matrix of described Serial No. in the described parity matrix.

6, method according to claim 2 is characterized in that, in the described Serial No., is used for determining that any two numerals of the first row element, 1 residing columns of described each sub matrix are different to the value of the line number delivery gained of described submatrix.

7, method according to claim 2 is characterized in that, when described LDPC sign indicating number is regular LDPC sign indicating number, and described code length is 4608, described code check is 1/2, described row heavily is 6 o'clock,

The length of described Serial No. is 192, and described Serial No. is:

9 212 384 2326 2803 3343 140 264 465 2405 2870 3445 192 305 560 2449 2925 3494 233 367 617 2587 2989 3571 295 460 703 2654 3055 3632 388 514 732 2709 3157 3730 442 610 832 2773 3206 3764 538 650 910 2839 3283 3886 578 770 957 2941 3344 3906 698 855 1067 2990 3442 4031 783 924 1085 3067 3476 4043 852 949 1156 3128 3598 4148 877 1065 1259 3226 3618 4242 993 1145 1335 3260 3743 4257 1073 1155 1393 3382 3755 4388 1083 1246 1456 3402 3860 4440 1174 1325 1565 3527 3954 4481 1253 1369 1648 3539 3969 4543 1297 1507 1664 2342 3644 4100 1435 1574 1734 2419 3738 4152 1502 1629 1849 2480 3753 4193 1557 1693 1924 2578 3884 4255 1621 1759 1980 2612 3936 4348 1687 1861 2088 2734 3977 4402

1789 1910 2115 2754 4039 4498 1838 1987 2183 2879 4132 4538 1915 2048 2301 2324 2891 4186 4 1976 2146 2446 2996 4282 107 2074 2180 2466 3090 4322 183 2108 2302 2591 3105 4442 3 241 2230 2603 3236 4527 94 304 2250 2708 3288 4596

The number of described sub matrix is 32, line number is 72, columns is 4608;

The number of submatrix is 64 in described each sub matrix;

Described submatrix is the square formation of 72 row * 72 row;

Comprise 192 displacement unit matrixs in the described parity matrix.

8, method according to claim 2 is characterized in that, when described LDPC sign indicating number is an irregular LDPC codes, and described code length is 4608, described code check is 1/2, described row heavily is 7 o'clock,

The length of described Serial No. is 224, and described Serial No. is:

923 970 2044 2100 2976 3359 4191 136 288 1972 2422 2904 4243 4266 597 704 779 1048 2805 4274 4380 454 632 918 976 3233 4365 4425 846 904 1007 1321 2688 4429 4484 653 832 1019 1119 3089 4495 4577 538 581 702 863 3017 3511 4597 429 1596 1745 1842 2945 3458 3576 558 616 755 803 2658 3571 3604 486 544 683 1277 3197 3668 3682 659 800 889 1380 3125 3694 3765 587 687 2505 2567 3255 3800 3875

467 656 745 1482 3183 3850 3893 443 543 1672 1942 3338 3942 4000 335 425 601 2295 3039 4031 4067 210 529 729 964 2765 4043 4143 628 773 824 1194 1558 3421 4112 129 191 556 876 2238 2441 3273 513 908 953 2007 2085 2370 2875 978 1240 1510 1548 1683 1742 3343 65 134 147 764 1751 2395 2834 464 692 834 985 1366 1404 2985 3 913 2145 2207 2463 2587 3127 444 727 928 952 1222 1260 3137 303 476 618 769 1150 2652 3242 546 1116 1190 2251 2362 2637 2697 29 1590 1669 1857 2179 2355 2921 439 766 972 1046 1359 1518 3026 481 862 1650 1934 1947 2211 2869 276 393 520 1862 1875 2139 3405 648 830 891 1381 1506 2551 2725 249 325 684 2045 2479 2738 3443

The number of described sub matrix is 32, line number is 72, columns is 4608;

The number of submatrix is 64 in described each sub matrix;

Described submatrix is the square formation of 72 row * 72 row;

Comprise 224 displacement unit matrix in the described parity matrix.

9, method according to claim 2 is characterized in that, when described LDPC sign indicating number is an irregular LDPC codes, and described code length is 4608, described code check is 43/64, described row heavily is 12 or 13 o'clock,

The length of described Serial No. is 256, and described Serial No. is:

536 1098 1156 1259 1889 2012 3529 3656 3739 3749 3907 3998 100 322 977 1026 1672 1940 2994 3073 3457 3677 4207 4382 743 1868 3512 3595 3605 3697 3763 3854 3900 4072 4230 4310 1199 1227 1429 3351 3523 3691 3782 3828 3895 4064 4150 4272 1079 2022 2173 2260 3194 3710 3823 3928 3992 4162 4389 4393 419 1362 1384 2475 2553 3547 3638 3856 4006 4090 4448 4531 144 146 1580 1648 2212 3449 3612 3784 4018 4089 4124 4469 4561 502 1508 2140 2508 2757 2819 2909 2978 3494 3540 4127 4555 2 683 791 1313 2376 2991 3118 3183 3305 3468 3980 4055 611 719 767 795 997 3254 3568 3632 3802 3873 3983 4102 4145 171 436 1169 1954 2052 2409 2693 2762 3496 3801 3836 4030 59 99 258 930 1053 1097 2531 2621 2690 2863 2902 3658 265 2090 2223 2282 2418 3271 3366 3502 3586 3657 3978 4036 4139 309 371 709 1374 1483 2331 3408 3514 3585 3695 3906 4067 389 1666 1834 2079 2138 2337 2873 2894 3548 3892 4103 4151 809 932 1468 1564 1594 3670 3713 3762 3820 3923 4079 4107 493 570 1267 1309 2607 2729 3078 3158 3381 3598 3851 3959 4007 30 242 327 856 2470 2535 3526 3618 3676 3779 3935 4165 549 593 1123 1791 2606 2787 3048 3237 3451 3497 3546 3863 170 1584 1719 1778 1899 2415 3165 3743 3791 3819 3932 4120 640 870 979 1647 1787 1827 2004 2253 3671 3719 3747 4026

The number of described sub matrix is 21, line number is 72, columns is 4608;

The number of submatrix is 64 in described each sub matrix;

Described submatrix is the square formation of 72 row * 72 row;

Comprise 256 displacement unit matrix in the described parity matrix.

10, according to claim 7,8 or 9 described methods, it is characterized in that, after described step B, further comprise: resulting parity matrix is carried out the rotation of various angles and/or carries out line replacement and/or carry out column permutation and/or change the position of described submatrix.

11, the implement device of low-density parity check code is characterized in that, this implement device comprises: memory module, check matrix generation module and code word generation module;

12, implement device according to claim 11 is characterized in that, described check matrix generation module further comprises: Serial No. analytic unit and cycle shift unit;

13, implement device according to claim 12 is characterized in that, further comprises in the described implement device: the check matrix converter unit;