CN1963541A - Electric energy computation circuit removing DC and circuit removing DC - Google Patents
Electric energy computation circuit removing DC and circuit removing DC Download PDFInfo
- Publication number
- CN1963541A CN1963541A CN 200610161043 CN200610161043A CN1963541A CN 1963541 A CN1963541 A CN 1963541A CN 200610161043 CN200610161043 CN 200610161043 CN 200610161043 A CN200610161043 A CN 200610161043A CN 1963541 A CN1963541 A CN 1963541A
- Authority
- CN
- China
- Prior art keywords
- direct current
- signal
- digital
- detection
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 75
- 238000001514 detection method Methods 0.000 claims description 111
- 238000004364 calculation method Methods 0.000 claims description 36
- 238000005070 sampling Methods 0.000 claims description 34
- 238000009825 accumulation Methods 0.000 claims description 18
- 238000001914 filtration Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 13
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
This invention discloses one direct current energy meter circuit, which comprises two A/D conversion unit, multiplier, low band filter and A/D unit and direct computation unit and abstract unit, wherein, the direct current computation unit is to compute one A/D conversion unit volume and to output direct current to abstract device; the abstract device is to receive digital signals from A/D conversion unit and direct current meter unit. This invention also discloses one direct current removal circuit.
Description
Technical Field
The invention relates to an electric energy metering technology, in particular to a direct current removing electric energy metering circuit and a direct current removing circuit.
Background
The electric energy metering means that: and measuring the energy generated by active power. Fig. 1 is a schematic structural diagram of an electric energy metering circuit in the prior art. As shown in fig. 1, in general, the electric energy metering circuit includes: the device comprises two analog-to-digital conversion units, a multiplier, a low-pass filter, a digital-to-frequency conversion unit and a metering unit. The two analog-to-digital conversion units respectively convert the current analog signals and the voltage analog signals into parallel current digital signals and parallel voltage digital signals with a plurality of bits, the parallel current digital signals and the parallel voltage digital signals are multiplied in a multiplier to obtain instantaneous power, the instantaneous power is subjected to low-pass filtering in a low-pass filter, and after being subjected to digital-to-frequency conversion by the digital-to-frequency conversion unit, the instantaneous power is output to the metering unit in a pulse form, and the metering unit counts the received pulses to realize electric energy metering. The metering unit may also be a functional unit other than the electric energy metering circuit, such as a metering device in an electric meter.
Assuming that the input voltage analog signal is v (t) ═ Vcos (ω · t) and the input current analog signal is i (t) ═ Icos (ω · t + α), the instantaneous power obtained by multiplying the input voltage analog signal by the multiplier is:
P(t)＝V(t)·I(t)＝Vcos(ω·t)×Icos(ω·t+α)
namely: <math> <mrow> <mi>P</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>cos</mi> <mi>α</mi> <mo>+</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>cos</mi> <mrow> <mo>(</mo> <mn>2</mn> <mi>ωt</mi> <mo>)</mo> </mrow> <mi>cos</mi> <mi>α</mi> <mo>-</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>sin</mi> <mrow> <mo>(</mo> <mn>2</mn> <mi>ωt</mi> <mo>)</mo> </mrow> <mi>sin</mi> <mi>α</mi> </mrow> </math>
component therein <math> <mrow> <msub> <mi>P</mi> <mn>0</mn> </msub> <mo>=</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>cos</mi> <mi>α</mi> </mrow> </math> I.e. the active power component to be measured, is usually obtained by a low-pass filter as shown in fig. 1.
However, in practical applications, considering peripheral circuits, the design and manufacture of the analog-to-digital conversion unit inevitably have dc offset, as shown in fig. 2, the instantaneous current flowing through the analog-to-digital conversion unit is a sine wave plus a dc component, where the dc component is the introduced dc offset IdcWhen DC bias is applied to IdcWhen the voltage analog signal and the current analog signal exist, the instantaneous power actually obtained after multiplication by the multiplier is as follows: <math> <mrow> <mi>P</mi> <mrow> <mo>(</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>=</mo> <mrow> <mo>(</mo> <mi>V</mi> <mi>cos</mi> <mrow> <mo>(</mo> <mi>ω</mi> <mo>·</mo> <mi>t</mi> <mo>)</mo> </mrow> <mo>+</mo> <msub> <mi>V</mi> <mi>dc</mi> </msub> <mo>)</mo> </mrow> <mo>×</mo> <mrow> <mo>(</mo> <mi>I</mi> <mi>cos</mi> <mrow> <mo>(</mo> <mrow> <mi>ω</mi> <mo>·</mo> <mi>t</mi> </mrow> <mo>+</mo> <mi>α</mi> <mo>)</mo> </mrow> <mo>+</mo> <msub> <mi>I</mi> <mi>dc</mi> </msub> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>cos</mi> <mi>α</mi> <mo>+</mo> <msub> <mi>V</mi> <mi>dc</mi> </msub> <msub> <mi>I</mi> <mi>dc</mi> </msub> <mo>+</mo> <msub> <mi>P</mi> <mi>ac</mi> </msub> </mrow> </math>
wherein, <math> <mrow> <msub> <mi>P</mi> <mi>ac</mi> </msub> <mo>=</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>cos</mi> <mrow> <mo>(</mo> <mn>2</mn> <mi>ωt</mi> <mo>)</mo> </mrow> <mi>cos</mi> <mi>α</mi> <mo>-</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>sin</mi> <mrow> <mo>(</mo> <mn>2</mn> <mi>ωt</mi> <mo>)</mo> </mrow> <mi>sin</mi> <mi>α</mi> <mo>+</mo> <msub> <mi>V</mi> <mi>dc</mi> </msub> <mi>I</mi> <mi>cos</mi> <mrow> <mo>(</mo> <mi>ω</mi> <mo>·</mo> <mi>t</mi> <mo>+</mo> <mi>α</mi> <mo>)</mo> </mrow> <mo>+</mo> <msub> <mi>I</mi> <mi>dc</mi> </msub> <mi>V</mi> <mi>cos</mi> <mrow> <mo>(</mo> <mi>ω</mi> <mo>·</mo> <mi>t</mi> <mo>)</mo> </mrow> </mrow> </math>
the active power component to be metered becomes <math> <mrow> <msub> <mi>P</mi> <mn>0</mn> </msub> <mo>=</mo> <mfrac> <mrow> <mi>V</mi> <mo>×</mo> <mi>I</mi> </mrow> <mn>2</mn> </mfrac> <mi>cos</mi> <mi>α</mi> <mo>+</mo> <msub> <mi>V</mi> <mi>dc</mi> </msub> <msub> <mi>I</mi> <mi>dc</mi> </msub> <mo>,</mo> </mrow> </math> Wherein V isdcIdcThe error term is introduced, so that the active power measurement is not accurate enough.
To eliminate VdcIdcItem, can remove IdcOr VdcAny of (1), even if IdcOr VdcIs 0, then the error term VdcIdc0, there is therefore a solution: adding a high-pass filter in the current path of the electric energy metering circuit to remove the DC bias I in the current pathdcThereby removing the error term. However, a phase difference is generated between the current signal and the voltage signal, and therefore, a phase compensation unit must be added for phase compensation, as shown in fig. 3, fig. 3 is a schematic diagram of a prior art electric energy metering circuit that uses a high-pass filter and a phase compensation unit to remove direct current. However, since the accuracy requirement for the phase compensation is very high, the requirement for the phase compensation unit is also very high, and the implementation is difficult.
Disclosure of Invention
In view of the above, an aspect of the present invention provides a dc-free power metering circuit, which is capable of removing a dc component without generating a phase difference.
Another aspect of the present invention provides a dc removal circuit capable of removing a dc component.
The invention provides a direct current removing electric energy metering circuit, which comprises: two analog-to-digital conversion units, a multiplier, a low-pass filter and a digital-to-frequency conversion unit, in addition, the circuit also comprises: a direct current calculation unit and a subtracter, wherein,
the direct current calculating unit is used for calculating a direct current component in the digital signal output by the analog-to-digital conversion unit and outputting the calculated direct current component to the subtracter;
and the subtracter is used for receiving the digital signal from the analog-to-digital conversion unit and the direct current component from the direct current calculation unit, performing subtraction operation and outputting the digital signal with the direct current component subtracted to the multiplier.
Wherein the direct current calculation unit includes: a sample point counter, a data accumulator, a period detection module, and a divider, wherein,
the sampling point counter is used for counting the discrete number of the digital signals output by the analog-to-digital conversion unit and outputting the counting result to the divider; receiving a zero clearing signal from the period detection module, and clearing the count according to the zero clearing signal;
the data accumulator is used for receiving the digital signals from the analog-to-digital conversion unit, accumulating the received digital signals and outputting the accumulated result to the divider; receiving a zero clearing signal from the period detection module, and clearing the accumulation result according to the zero clearing signal;
the period detection module is used for carrying out period detection on the digital signals output by the analog-to-digital conversion unit, sending a control signal to the divider when the number of the whole periods of the output digital signals reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator, and clearing the count of the sampling point counter and the data accumulator;
and the divider is used for receiving the control signal from the period detection module, receiving the accumulation result from the data accumulator and the counting result from the sampling point counter according to the control signal, performing division operation, dividing the accumulation result by the counting result to obtain a direct current component and outputting the direct current component to the subtracter.
Wherein the period detection module comprises: a detection sub-module and a cycle counter, wherein,
the detection submodule is used for detecting the digital signal output by the analog-to-digital conversion unit, and sending a notification signal to the cycle counter when a preset detection point is detected;
and the period counter is used for accumulating the number of the detection points according to the received notification signal, sending a control signal to the divider when the number of the periods represented by the number of the detection points reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator at the same time, and clearing the count of the sampling point counter and the data accumulator.
Wherein the detection submodule is: the zero-crossing detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is a zero point;
or the detection submodule is: the maximum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the maximum peak;
or the detection submodule is: and the minimum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the minimum peak.
Wherein the cycle counter is further to: a number of cycles value preset to at least one cycle number is stored.
Preferably, the circuit further comprises: and the low-pass filter is positioned between the analog-to-digital conversion unit and the direct current calculation unit and is used for receiving the digital signal from the analog-to-digital conversion unit, performing low-pass filtering on the digital signal and outputting the digital signal to the direct current calculation unit.
The direct current computing unit is a current direct current computing unit, the one-path analog-to-digital conversion unit is a current analog-to-digital conversion unit, the digital signal is a current digital signal, and the direct current component is a current direct current component;
or the direct current computing unit is a voltage direct current computing unit, the one-path analog-to-digital conversion unit is a voltage analog-to-digital conversion unit, the digital signal is a voltage digital signal, and the direct current component is a voltage direct current component.
The invention provides a DC removing circuit, which comprises: a direct current calculation unit and a subtracter, wherein,
a direct current calculation unit for calculating a direct current component in the digital signal containing the direct current component and outputting the calculated direct current component to the subtractor;
and the subtracter is used for receiving the digital signal containing the direct current component and the direct current component from the direct current calculation unit, performing subtraction operation and outputting the digital signal with the direct current component subtracted.
Wherein the direct current calculation unit includes: a sample point counter, a data accumulator, a period detection module, and a divider, wherein,
the sampling point counter is used for counting the discrete number of the digital signals containing the direct current components and outputting the counting result to the divider; receiving a zero clearing signal from the period detection module, and clearing the count according to the zero clearing signal;
the data accumulator is used for receiving the digital signal containing the direct-current component, accumulating the received digital signal and outputting an accumulation result to the divider; receiving a zero clearing signal from the period detection module, and clearing the accumulation result according to the zero clearing signal;
the period detection module is used for carrying out period detection on the digital signal containing the direct-current component, sending a control signal to the divider when the number of the whole periods of the output digital signal reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator at the same time, and clearing the count of the sampling point counter and the data accumulator;
and the divider is used for receiving the control signal from the period detection module, receiving the accumulation result from the data accumulator and the counting result from the sampling point counter according to the control signal, performing division operation, dividing the accumulation result by the counting result to obtain a direct current component and outputting the direct current component to the subtracter.
Wherein the period detection module comprises: a detection sub-module and a cycle counter, wherein,
the detection submodule is used for detecting the digital signal containing the direct current component and sending a notification signal to the cycle counter when a preset detection point is detected;
and the period counter is used for accumulating the number of the detection points according to the received notification signal, sending a control signal to the divider when the number of the periods represented by the number of the detection points reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator at the same time, and clearing the count of the sampling point counter and the data accumulator.
Wherein the detection submodule is: the zero-crossing detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is a zero point;
or the detection submodule is: the maximum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the maximum peak;
or the detection submodule is: and the minimum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the minimum peak.
Wherein the cycle counter is further to: a number of cycles value preset to at least one cycle number is stored.
Preferably, the circuit further comprises: and the low-pass filter is positioned in front of the direct current computing unit and used for receiving the digital signal containing the direct current component, performing low-pass filtering on the digital signal and outputting the digital signal to the direct current computing unit.
As can be seen from the above solution, the present invention provides a dc calculating unit and a subtractor in a current path or a voltage path, calculates a dc component in a received digital signal by the dc calculating unit, and outputs the calculated dc component to the subtractor; the subtracter subtracts the direct current component calculated by the direct current calculating unit from the received digital signal containing the direct current component, and outputs the digital signal with the direct current component subtracted, thereby removing one path of direct current component and achieving the purpose of eliminating VdcIdcThe purpose of the item is to accurately calculate the active power, and because the main channel of the digital signal is not influenced by the direct current calculating unit, the phase difference can not be generated.
Drawings
Fig. 1 is a schematic structural diagram of an electric energy metering circuit in the prior art.
Fig. 2 is a schematic diagram of a current signal in the presence of a dc bias.
Fig. 3 is a schematic structural diagram of a dc power removal metering circuit in the prior art.
Fig. 4 is a schematic structural diagram of a dc power removal metering circuit according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of an internal structure of a dc calculating unit in the circuit shown in fig. 4.
Fig. 6 is a schematic structural diagram of a dc removing circuit with a low-pass filter added in the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following embodiments and the accompanying drawings.
The basic idea of the invention is: setting a direct current calculating unit and a subtracter, calculating a direct current component in the received digital signal by the direct current calculating unit, and outputting the calculated direct current component to the subtracter; the subtracter subtracts the direct current component calculated by the direct current calculation unit from the received digital signal containing the direct current component, and outputs the digital signal subtracted with the direct current component.
In practical application, the direct current calculating unit and the subtracter can be arranged in a current path and a voltage path.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a dc-free power metering circuit applying the above idea in the embodiment of the present invention. As shown in fig. 4, the circuit includes: analog-to-digital conversion unit 401, direct current calculation unit 402, subtractor 403, analog-to-digital conversion unit 404, multiplier 405, low-pass filter 406, and digital-to-frequency conversion unit 407.
The dc calculating unit 402 is configured to calculate a dc component in the digital signal output by the analog-to-digital converting unit 401, and output the calculated dc component to the subtractor 403.
The analog-to-digital conversion unit 401 may be an analog-to-digital conversion unit in a current path or an analog-to-digital conversion unit in a voltage path.
If the analog-to-digital conversion unit 401 is an analog-to-digital conversion unit in the current path, the corresponding direct current calculation unit is a current direct current calculation unit, the digital signal is a current digital signal, the direct current component is a current direct current component, and the analog-to-digital conversion unit 404 is an analog-to-digital conversion unit in the voltage path; if the analog-to-digital conversion unit 401 is an analog-to-digital conversion unit in the voltage path, the corresponding dc calculation unit is a voltage dc calculation unit, the digital signal is a voltage digital signal, the dc component is a voltage dc component, and the analog-to-digital conversion unit 404 is an analog-to-digital conversion unit in the current path.
In the following, taking a case where the dc calculating unit 402 and the subtractor 403 are disposed in a current path as an example, that is, the analog-to-digital converting unit 401 is an analog-to-digital converting unit in a current path, and the analog-to-digital converting unit 404 is an analog-to-digital converting unit in a voltage path, for example, for convenience of distinction, the analog-to-digital converting unit 401 may be referred to as a current analog-to-digital converting unit 401, and the analog-to-digital converting unit 404 may be referred to as a voltage analog-.
The current analog-to-digital conversion unit 401 is configured to convert the current analog signal into a current digital signal, and output the current digital signal to the direct current calculation unit 402 and the subtractor 403. The current digital signal is a current digital signal containing a direct current component.
The dc calculating unit 402 is configured to receive the current digital signal from the current analog-to-digital converting unit 401, calculate a dc component in the received current digital signal, and output the calculated dc component to the subtractor 403.
The voltage analog-to-digital conversion unit 404 is configured to convert the voltage analog signal into a voltage digital signal and output the voltage digital signal to the multiplier 405.
The multiplier 405 is configured to receive the current digital signal from the subtractor 403 and the voltage digital signal from the voltage analog-to-digital conversion unit 404, multiply the current digital signal and the voltage digital signal to obtain an instantaneous power, and output the instantaneous power to the low-pass filter 406.
The low-pass filter 406 is configured to receive the instantaneous power from the multiplier 405, filter the received instantaneous power, and output the filtered instantaneous power to the digital-to-frequency conversion unit 407.
The digital frequency conversion unit 407 is used to convert the instantaneous power from the low pass filter 406 into a pulse form output.
The function and principle are the same when the above process is implemented in the voltage path.
The specific implementation manner of the dc calculating unit 402 can be many, and the dc calculating unit 402 in the embodiment of the present invention is described in detail below by taking only one specific implementation manner as an example.
Referring to fig. 5, fig. 5 is a schematic diagram of an internal structure of the dc calculating unit 402 in the circuit shown in fig. 4. As shown in fig. 5, the dc calculating unit 402 specifically includes: a sample point counter 501, a data accumulator 502, a period detection module 503, and a divider 504.
The principle of implementation of the dc calculating unit 402 shown in fig. 5 is as follows: as can be seen from the current signal diagram shown in fig. 2, when the current signals in a period T are added up, the ac part will be cancelled out, so that the dc component part in the period T, as shown by ABCD in the figure, is retained, and the area is divided by the side length AB to obtain the value I of the dc componentdc. Based on this principle, the current values in one cycle may be accumulated, or the current values in a plurality of cycles may be accumulated, and as long as the accumulated current values are an integer number of cycles, the ac part may be cancelled out positively and negatively. The same applies to the voltage signal.
In practical applications, since digital signals of current or voltage are usually processed, for example, the current signals passing through the current analog-to-digital conversion unit 401 are current digital signals, and the current digital signals are generally discrete values, which are also called as sampling points, it is necessary to perform numerical accumulation on each discrete value in a whole number of cycles, record the number of discrete values, and finally divide the accumulated value in an integer number of cycles by the number of numerical values corresponding to the accumulated value to obtain a dc component.
Each block in the dc calculation unit 402 is described in detail below.
In specific implementation, the sampling point counter 501 is configured to count the discrete number of the digital signals output by the analog-to-digital conversion unit 401, and output a count result to the divider 504; a clear signal from the cycle detection module 503 is received and the count is cleared based on the clear signal.
The data accumulator 502 is configured to receive the digital signal from the analog-to-digital conversion unit 401, accumulate the received digital signal, and output an accumulation result to the divider 504; the clear signal from the period detection module 503 is received and the accumulation result is cleared according to the clear signal.
The period detection module 503 is configured to perform period detection on the digital signal output by the analog-to-digital conversion unit 401, and when the number of the whole periods of the output digital signal reaches a preset period number value, send a control signal to the divider 504, and send a clear signal to the sampling point counter 501 and the data accumulator 502, and clear the count of the sampling point counter and the count of the data accumulator.
The divider 504 is configured to receive the control signal from the period detection module 503, receive the accumulated result from the data accumulator 502 and the counting result from the sampling point counter 501 according to the control signal, perform division operation, divide the accumulated result by the counting result, obtain a dc component, and output the dc component to the subtractor 403.
The sampling point counter 501 and the data accumulator 502 output the respective calculation results to the divider 504 in real time, but the divider 504 does not receive the calculation results every time, and the switch is turned on only when the divider 504 receives the control signal from the period detection module 503 to receive the calculation results from the sampling point counter 501 and the data accumulator 502. The divider 504 outputs the dc component to the subtractor 403, and outputs the dc component value calculated last time until the update.
In the above detailed description of each module in the dc calculating unit 402 shown in fig. 5, if the analog-to-digital converting unit 401 is a current analog-to-digital converting unit, the corresponding digital signal is a current digital signal; if the analog-to-digital conversion unit 401 is a voltage analog-to-digital conversion unit, the corresponding digital signal is a voltage digital signal. And the digital signal is a digital signal containing a direct current component.
The period detection module 503 may also be implemented in various ways, for example, zero points may be detected to determine whether the period is a whole period, for example, when the period is just started, counting is started from a first zero point, for example, data accumulation and sampling point counting are performed, until two zero points appear again, the period is a whole period, if the dc calculation is performed by using data of a plurality of whole periods, the zero points may be continuously accumulated, and each two zero points appear as a period, so as to obtain the number of periods. In addition, the maximum peak value can be detected, the detection method is similar to that in zero point detection, and when the maximum peak values are added subsequently, each two maximum peak values are in one period, so that the number of the periods can be obtained. Similarly, the minimum peak may be detected.
In a specific implementation, detection points may be preset, and the detection points may be points having characteristics such as a zero point, a maximum peak value, or a minimum peak value, and the number of cycles may be obtained by detecting and counting the preset detection points.
Also taking the dc calculating unit 402 in the current path as an example, the cycle detecting module 503 in the dc calculating unit 402 will be described in detail.
In a specific implementation, the period detection module 503 may specifically include: a detection submodule and a period counter.
The detection submodule is configured to detect a digital signal output by the analog-to-digital conversion unit 401, and send a notification signal to the cycle counter when a preset detection point is detected.
The period counter is used for accumulating the number of the detection points according to the received notification signal, sending a control signal to the divider when the number of the periods represented by the number of the detection points reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator at the same time, and clearing the count of the period counter.
The detection submodule may be a zero-crossing detection submodule, configured to perform zero-crossing detection on the digital signal output by the analog-to-digital conversion unit 401, and send a notification signal to the cycle counter when a zero point is detected. The zero point is not the absolute zero point, but the point closest to zero, because the number of actually sampled points is not all the points sampled at the absolute zero point.
In addition, the detection sub-module may also be a maximum peak detection sub-module, or a minimum peak detection sub-module, etc.
Similarly, if the analog-to-digital conversion unit 401 is a current analog-to-digital conversion unit, the corresponding digital signal is a current digital signal; if the analog-to-digital conversion unit 401 is a voltage analog-to-digital conversion unit, the corresponding digital signal is a voltage digital signal.
In order to make the dc component calculated by the dc calculating unit 402 more accurate, a low pass filter 408 may be added to the embodiment shown in fig. 4 for filtering out high frequency noise. As shown in fig. 6, fig. 6 is a schematic structural diagram of a dc removing circuit with a low pass filter added in the embodiment of the present invention. The low-pass filter 408 is disposed between the analog-to-digital conversion unit 401 and the dc calculation unit 402, and is configured to receive the digital signal from the analog-to-digital conversion unit 401, perform low-pass filtering on the digital signal, and output the digital signal to the dc calculation unit 402, and perform an operation of calculating a dc component on the digital signal after being filtered by the low-pass filter by the dc calculation unit 402. In a specific implementation, the sampling point counter 501, the data accumulator 502 and the period detection module 503 inside the dc calculating unit 402 may respectively perform the counting, accumulating and period detection operations on the digital signal after being filtered by the low pass filter.
Similarly, if the analog-to-digital conversion unit 401 is a current analog-to-digital conversion unit, the corresponding digital signal is a current digital signal; if the analog-to-digital conversion unit 401 is a voltage analog-to-digital conversion unit, the corresponding digital signal is a voltage digital signal.
The circuit structure diagram shown in fig. 6 can also be used as a dc removal circuit alone. Also when used alone as a dc removing circuit, the circuit configuration shown in fig. 6 is preferably configured with the low-pass filter 408, and if it is necessary to calculate the digital signal containing the dc component as a digital signal after the high-frequency noise has been removed, the low-pass filter 408 may not be provided.
The circuit configuration of the dc calculating unit 402 shown in fig. 5 may be a dc calculating circuit alone. And further, a low pass filter 408 may be provided in the dc calculation circuit, and the connection relationship thereof may be the same as that in the dc removing circuit shown in fig. 6.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (13)
1. A de-dc power metering circuit comprising: two analog-to-digital conversion units, a multiplier, a low-pass filter and a digital-to-frequency conversion unit, and the circuit is characterized by further comprising: a direct current calculation unit and a subtracter, wherein,
the direct current calculating unit is used for calculating a direct current component in the digital signal output by the analog-to-digital conversion unit and outputting the calculated direct current component to the subtracter;
and the subtracter is used for receiving the digital signal from the analog-to-digital conversion unit and the direct current component from the direct current calculation unit, performing subtraction operation and outputting the digital signal with the direct current component subtracted to the multiplier.
2. The circuit of claim 1, wherein the dc calculation unit comprises: a sample point counter, a data accumulator, a period detection module, and a divider, wherein,
the sampling point counter is used for counting the discrete number of the digital signals output by the analog-to-digital conversion unit and outputting the counting result to the divider; receiving a zero clearing signal from the period detection module, and clearing the count according to the zero clearing signal;
the data accumulator is used for receiving the digital signals from the analog-to-digital conversion unit, accumulating the received digital signals and outputting the accumulated result to the divider; receiving a zero clearing signal from the period detection module, and clearing the accumulation result according to the zero clearing signal;
the period detection module is used for carrying out period detection on the digital signals output by the analog-to-digital conversion unit, sending a control signal to the divider when the number of the whole periods of the output digital signals reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator, and clearing the count of the sampling point counter and the data accumulator;
and the divider is used for receiving the control signal from the period detection module, receiving the accumulation result from the data accumulator and the counting result from the sampling point counter according to the control signal, performing division operation, dividing the accumulation result by the counting result to obtain a direct current component and outputting the direct current component to the subtracter.
3. The circuit of claim 2, wherein the cycle detection module comprises: a detection sub-module and a cycle counter, wherein,
the detection submodule is used for detecting the digital signal output by the analog-to-digital conversion unit, and sending a notification signal to the cycle counter when a preset detection point is detected;
and the period counter is used for accumulating the number of the detection points according to the received notification signal, sending a control signal to the divider when the number of the periods represented by the number of the detection points reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator at the same time, and clearing the count of the sampling point counter and the data accumulator.
4. The circuit of claim 3, wherein the detection submodule is: the zero-crossing detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is a zero point;
or the detection submodule is: the maximum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the maximum peak;
or the detection submodule is: and the minimum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the minimum peak.
5. The circuit of claim 3, wherein the cycle counter is further to: a number of cycles value preset to at least one cycle number is stored.
6. The circuit of claim 1, further comprising: and the low-pass filter is positioned between the analog-to-digital conversion unit and the direct current calculation unit and is used for receiving the digital signal from the analog-to-digital conversion unit, performing low-pass filtering on the digital signal and outputting the digital signal to the direct current calculation unit.
7. The circuit according to any one of claims 1 to 6, wherein the DC calculating unit is a current DC calculating unit, the one-way analog-to-digital converting unit is a current analog-to-digital converting unit, the digital signal is a current digital signal, and the DC component is a current DC component;
or the direct current computing unit is a voltage direct current computing unit, the one-path analog-to-digital conversion unit is a voltage analog-to-digital conversion unit, the digital signal is a voltage digital signal, and the direct current component is a voltage direct current component.
8. A de-dc circuit, comprising: a direct current calculation unit and a subtracter, wherein,
a direct current calculation unit for calculating a direct current component in the digital signal containing the direct current component and outputting the calculated direct current component to the subtractor;
and the subtracter is used for receiving the digital signal containing the direct current component and the direct current component from the direct current calculation unit, performing subtraction operation and outputting the digital signal with the direct current component subtracted.
9. The circuit of claim 8, wherein the dc calculation unit comprises: a sample point counter, a data accumulator, a period detection module, and a divider, wherein,
the sampling point counter is used for counting the discrete number of the digital signals containing the direct current components and outputting the counting result to the divider; receiving a zero clearing signal from the period detection module, and clearing the count according to the zero clearing signal;
the data accumulator is used for receiving the digital signal containing the direct-current component, accumulating the received digital signal and outputting an accumulation result to the divider; receiving a zero clearing signal from the period detection module, and clearing the accumulation result according to the zero clearing signal;
the period detection module is used for carrying out period detection on the digital signal containing the direct-current component, sending a control signal to the divider when the number of the whole periods of the output digital signal reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator at the same time, and clearing the count of the sampling point counter and the data accumulator;
and the divider is used for receiving the control signal from the period detection module, receiving the accumulation result from the data accumulator and the counting result from the sampling point counter according to the control signal, performing division operation, dividing the accumulation result by the counting result to obtain a direct current component and outputting the direct current component to the subtracter.
10. The circuit of claim 9, wherein the cycle detection module comprises: a detection sub-module and a cycle counter, wherein,
the detection submodule is used for detecting the digital signal containing the direct current component and sending a notification signal to the cycle counter when a preset detection point is detected;
and the period counter is used for accumulating the number of the detection points according to the received notification signal, sending a control signal to the divider when the number of the periods represented by the number of the detection points reaches a preset period number value, sending a zero clearing signal to the sampling point counter and the data accumulator at the same time, and clearing the count of the sampling point counter and the data accumulator.
11. The circuit of claim 10, wherein the detection submodule is: the zero-crossing detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is a zero point;
or the detection submodule is: the maximum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the maximum peak;
or the detection submodule is: and the minimum peak detection submodule is used for sending a notification signal to the cycle counter when the preset detection point is the minimum peak.
12. The circuit of claim 10, wherein the cycle counter is further to: a number of cycles value preset to at least one cycle number is stored.
13. A circuit as claimed in any one of claims 8 to 12, further comprising: and the low-pass filter is positioned in front of the direct current computing unit and used for receiving the digital signal containing the direct current component, performing low-pass filtering on the digital signal and outputting the digital signal to the direct current computing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101610433A CN100492026C (en) | 2006-12-04 | 2006-12-04 | Electric energy computation circuit removing DC and circuit removing DC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101610433A CN100492026C (en) | 2006-12-04 | 2006-12-04 | Electric energy computation circuit removing DC and circuit removing DC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1963541A true CN1963541A (en) | 2007-05-16 |
| CN100492026C CN100492026C (en) | 2009-05-27 |
Family
ID=38082679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101610433A Expired - Fee Related CN100492026C (en) | 2006-12-04 | 2006-12-04 | Electric energy computation circuit removing DC and circuit removing DC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100492026C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937017A (en) * | 2010-08-10 | 2011-01-05 | 珠海中慧微电子有限公司 | Dynamic direct-current removing method for intelligent electric meter during alternating-current sampling |
| CN101777365B (en) * | 2009-12-22 | 2012-02-01 | 凌阳科技股份有限公司 | filter and filtering method thereof |
| CN105738686A (en) * | 2016-04-12 | 2016-07-06 | 辽宁大学 | Current detection method |
| CN107515327A (en) * | 2016-06-16 | 2017-12-26 | 上海华虹集成电路有限责任公司 | The blob detection circuit received for magnetizing mediums signal in ISO7811 agreements |
| CN108900453A (en) * | 2018-06-13 | 2018-11-27 | 上海晟矽微电子股份有限公司 | DC component acquisition device and method |
| CN110830075A (en) * | 2019-11-07 | 2020-02-21 | 成都九洲迪飞科技有限责任公司 | Zero-intermediate-frequency transceiving component analog-to-digital converter DC-removing method |
| CN111310522A (en) * | 2018-12-12 | 2020-06-19 | 航天信息股份有限公司 | Method and equipment for removing direct current |
| CN113746310A (en) * | 2021-11-05 | 2021-12-03 | 艾乐德电子（南京）有限公司 | Device and method for eliminating direct current component in alternating current power supply output periodic symmetrical waveform |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2355900B (en) * | 1999-10-29 | 2004-03-17 | Ericsson Telefon Ab L M | Radio receiver |
| CN1195231C (en) * | 2002-02-20 | 2005-03-30 | 北京中星微电子有限公司 | Automatic eliminating method for self d.c. component in power metering system |
| CN1570653A (en) * | 2004-05-14 | 2005-01-26 | 杭州利尔达单片机技术有限公司 | MSP430FE42x single phase multifunctional electric energy meter and metering method |
| CN2704849Y (en) * | 2004-06-11 | 2005-06-15 | 石家庄长通电器有限公司 | Effective induction style electric energy meter |
-
2006
- 2006-12-04 CN CNB2006101610433A patent/CN100492026C/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777365B (en) * | 2009-12-22 | 2012-02-01 | 凌阳科技股份有限公司 | filter and filtering method thereof |
| CN101937017A (en) * | 2010-08-10 | 2011-01-05 | 珠海中慧微电子有限公司 | Dynamic direct-current removing method for intelligent electric meter during alternating-current sampling |
| CN105738686A (en) * | 2016-04-12 | 2016-07-06 | 辽宁大学 | Current detection method |
| CN107515327A (en) * | 2016-06-16 | 2017-12-26 | 上海华虹集成电路有限责任公司 | The blob detection circuit received for magnetizing mediums signal in ISO7811 agreements |
| CN107515327B (en) * | 2016-06-16 | 2020-10-30 | 上海华虹集成电路有限责任公司 | Peak detection circuit for magnetic medium signal reception in ISO7811 protocol |
| CN108900453A (en) * | 2018-06-13 | 2018-11-27 | 上海晟矽微电子股份有限公司 | DC component acquisition device and method |
| CN108900453B (en) * | 2018-06-13 | 2021-02-09 | 上海晟矽微电子股份有限公司 | Direct current component acquisition device and method |
| CN111310522A (en) * | 2018-12-12 | 2020-06-19 | 航天信息股份有限公司 | Method and equipment for removing direct current |
| CN110830075A (en) * | 2019-11-07 | 2020-02-21 | 成都九洲迪飞科技有限责任公司 | Zero-intermediate-frequency transceiving component analog-to-digital converter DC-removing method |
| CN113746310A (en) * | 2021-11-05 | 2021-12-03 | 艾乐德电子（南京）有限公司 | Device and method for eliminating direct current component in alternating current power supply output periodic symmetrical waveform |
| CN113746310B (en) * | 2021-11-05 | 2022-02-08 | 艾乐德电子（南京）有限公司 | Device and method for eliminating direct current component in alternating current power supply output periodic symmetrical waveform |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100492026C (en) | 2009-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100492026C (en) | Electric energy computation circuit removing DC and circuit removing DC | |
| KR102309359B1 (en) | Time-to-digital converter with increased range and sensitivity | |
| US7474087B2 (en) | Energy meter system and method for calibration | |
| US8508213B2 (en) | Frequency measurement device | |
| KR102041677B1 (en) | Apparatus for assuring accuracy of harmonic frequency power, Method thereof, and Computer readable storage medium having the same | |
| CN1082667C (en) | Apparatus for measuring a pulse duration | |
| US4291377A (en) | Apparatus for measuring electrical power | |
| CN101937017A (en) | Dynamic direct-current removing method for intelligent electric meter during alternating-current sampling | |
| CN107430159B (en) | System and method for ripple-free AC power determination | |
| CN101562431A (en) | Phase-locking amplifier | |
| EP0793106B1 (en) | Arithmetic unit | |
| TW201237429A (en) | Measuring sum of squared current | |
| US6794857B2 (en) | Apparatus and method for measuring a phase delay characteristic | |
| US9513319B1 (en) | Systems, methods, and devices for energy and power metering | |
| JP2587970B2 (en) | Impedance measuring device | |
| CN100442665C (en) | Clock phase detecting device and method | |
| CN100378463C (en) | Wave detection device, method, program, and recording medium | |
| RU2225012C2 (en) | Phase-meter | |
| EP1378756B1 (en) | Digital circuit for measuring of power | |
| RU2117954C1 (en) | Signal-to-noise ratio meter | |
| RU2751020C1 (en) | Digital phase shift meter for harmonic signals | |
| CN117054737B (en) | Method and device for calculating power supply frequency through autocorrelation filtering | |
| JP4329916B2 (en) | Train detector | |
| RU2368910C1 (en) | Device for measurement of commercial frequency alternating current parametres | |
| RU2025738C1 (en) | Device for measuring frequency and frequency difference of signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090527 Termination date: 20121204 |