CN1961353A - Inhibition of power supply variations for gain error cancellation in pulse-width-modulated motor controllers - Google Patents

Abstract

A positioning driver (32) for a voice coil motor (22) in a disk drive system is disclosed. Pulse-width-modulated prestage drivers (46) are coupled to power transistors (50PH, 50NH, 50PL, 50NL) arranged in an 'H' bridge for driving the voice coil motor (22), biased with a power supply voltage (VM). The pulse-width-modulated prestage drivers (46) drive the power transistors (50PH, 50NH, 50PL, 50NL) according to a comparison between an error signal from an error amplifier (36) and a ramp clock signal (RMP) generated by a ramp clock generator (48). The ramp clock generator (48) includes a control circuit that modulates the high and low limits of the ramp clock signal (RMP) in response to variations in the power supply voltage (VM). This modulation of the high and low limits compensates for variations in the gain of the power transistors (50) resulting from variations in the power supply voltage (VM). The control circuit may also modulate the slope of the ramp clock signal (RMP) according to variations in the power supply voltage (VM), for example to maintain a constant frequency.

Description

Suppress power source change to eliminate the gain error of pulse-length modulation electric machine controller

Technical field

[0001] the present invention relates to Motor Control Field, and more particularly, at the control of the voice coil motor that is used for the computer disk driving governor.

Background technology

It is evident that in the industry cycle that [0002] in the modern computer that comprises desktop workstations and portable " on knee " computing machine, disk drive or driver still are the major techniques of high capacity read/write store.Now, disc driver is very popular in the portable system on a small scale such as portable voice frequency system and player equally.

[0003] modern disk drives generally comprises " main shaft " motor and " voice coil loudspeaker voice coil " motor.In operational process, the spindle motor spinning disk, the sector that makes the disk certain radius is by data transducer, or read/write " head "." voice coil loudspeaker voice coil " motor is in the radial position locator data sensor of magnetic disk surface, the track location that this radial position is read thus or write corresponding to data.Data transducer generally is positioned at the far-end of registration arm, and registration arm is from the surface that the fulcrum or the pivoting point of disk periphery rotates through spinning disk, and registration arm changes the radial position of the data transducer on magnetic disk surface around the rotation of pivot like this.Voice coil motor control registration arm is around the rotation of pivot, thus the track location of control data sensor.

[0004] the voice coil motor controller circuitry provides drive signal by a pair of output driver to voice coil motor usually, output driver generally comprises high side or high bit driver (high sidedriver) and downside or low bit driver (low side driver), and they are connected on the voice coil motor opposite side.In service, provide electric current to flow through voice coil motor by high side driver, flow to low side driver, and registration arm is rotated around pivot along a direction, and provide electric current to flow through voice coil motor by low side driver, flow to high side driver, and registration arm is rotated around pivot along opposite direction.

[0005] as further background technology, the U.S. the 5th, 838, No. 515 patent has been described a kind of dual-mode voice coil motor driver, and it operates in pulse-length modulation (" D class ") pattern and linear model.As known in the art, " track following " operational mode of voice coil motor remains on the track location of expectation with data transducer, and " magnetic track searching " operational mode moves to another track location with registration arm from a track location.This list of references has been described during magnetic track is sought, and voice coil motor runs on pulse-width-modulated mode, but when entering the deceleration period of tracking, just is transformed into operation under the linear model, all remains on linear model then during track following.

[0006] with reference now to Fig. 1, Fig. 1 illustrates the voice coil motor driver of conventional pulse-length modulation.In this example, the last reception of online ERRP, ERRM differential error signal.Incoming line ERRP is applied to the noninverting or in-phase input end of comparer 3H, and incoming line ERRM is applied to the non-inverting input of comparer 3L.Differential error signal on line ERRP, the ERRM is produced by the error amplifier (not shown) usually, and this error amplifier compares the incoming level of feedback signal and expectation.Slope clock generator 2 produces the triangular signal of certain frequency, this frequency is corresponding to the output signal frequency of the pulse-length modulation (PWM) of expectation, and slope clock generator 2 is applied to this slope clock signal the inverting input of comparer 3H, 3L.The output of comparer 3H is applied to the input of difference PWM output amplifier 4H, and the output of comparer 3L is connected to the input of difference PWM output amplifier 4L.The output level that difference PWM output amplifier 4H produces is applied to the grid of power transistor 5PH, 5PL, and it defines differential voltage gP; Similarly, the output level that difference PWM output amplifier 4L produces is applied to the grid of power transistor 5NH, 5NL, and differential voltage is gM.

[0007] as known in the art, power transistor 5 is arranged to conventional " H " bridge to drive voice coil motor (VCM) 9.In this layout, source electrode-drain path of power transistor 5PH, 5PL is connected in series in supply voltage V _MAnd between the ground, source electrode-drain path of same transistor 5NH, 5NL also is connected in series in supply voltage V _MAnd between the ground.VCM 9 is connected between node VCMP and the node VCMN, node VCMP is arranged in drain electrode and transistor 5PH (this example of transistor 5PL, transistor 5PL, 5PH are the N channel device) source electrode between, node VCMN is between the source electrode of the drain electrode of transistor 5NL and transistor 5NH.Correspondingly, the relative voltage at node VCMP, VCMN place has determined conduction flow to cross the polarity and the size of the electric current of VCM9.

[0008] ruuning situation of the routine of Fig. 1 being arranged with reference now to Fig. 2 is described.From what Fig. 2 obviously found out be on the one hand, the relation between the signal on error originated from input line ERRP, the ERRM, what obviously find out on the other hand is to have determined to flow through the electric current of VCM 9 from the signal RMP of slope clock generator 2.As shown in Figure 2, when the voltage on the line ERRP was higher than the instantaneous voltage of slope clock RMP, the differential voltage gP that exports from PWM output amplifier 4H was positive, and when the voltage of the voltage ratio slope clock RMP on the line ERRP hanged down, this differential voltage was born.With reference to figure 1, in this example, positive differential voltage gP makes transistor 5PH with respect to transistor 5PL conducting again, and its voltage with node VCMP pulls to supply voltage V _MSimilarly, when the voltage on the line ERRM was lower than the instantaneous voltage of slope clock RMP, the differential voltage gM of PWM output amplifier 4L output was positive, and when the voltage of the voltage ratio slope clock RMP on the line ERRM was high, this differential voltage was born.Positive differential voltage gM makes transistor 5NL with respect to transistor 5NH conducting, and its voltage with node VCMN pulls to ground voltage.

[0009] in general, when the voltage of node VCMP and node VCMN differed from one another, electric current conducted between node VCMA, VCMB, and flow through VCM 9.In Fig. 2, the electric current of the current impulse explanation positive polarity from T0 to T3 flows through VCM 9, promptly all be those times of positive polarity, and the electric current of the current impulse of T4 and T5 explanation negative polarity flow through VCM 9, all is negative polarity corresponding to differential voltage gP, gM corresponding to differential voltage gP, gM.In this example, be that voltage at incoming line ERRP is higher than reference voltage V such as the such positive polarity current impulse of the pulse in from T0 to T3 _Ref, and the voltage of incoming line ERRM is lower than reference voltage V _RefSituation under produce.On the contrary, be lower than the voltage of waveform RMP at the voltage of incoming line ERRP, and the voltage of incoming line ERRM also is lower than the time durations of the voltage of waveform RMP, electric current conduction flow is in the opposite direction crossed VCM 9, as current impulse T4, T5, and shown in corresponding differential voltage gP, the gM.In example shown in Figure 2, this negative current drive is because the voltage of incoming line ERRP drops to reference voltage V _RefUnder, and the voltage of incoming line ERRM rises to reference voltage V _RefOn produce.At differential voltage gP, gM is the time durations of opposite polarity, and the voltage reality of node VCMP, VCMN is mutually the same, and the non-conducting electric current.

[0010] observe, related to the present invention, the variation of supply voltage can influence the transadmittance gain of conventional PWM VCM driving circuit shown in Figure 1, or open-loop gain, and therefore can influence the electric current that VCM 9 is flow through in driving.Find out clearly that from Fig. 1 the electric current that flows through the power transistor 5 of " H " bridge layout directly depends on supply voltage V _MObviously, for a given fixed duty cycle, higher supply voltage V _MCan cause higher drain current, the electric current that therefore flows through VCM 9 is higher.

[0011] with reference to figure 2, in order to consider the gain of driving circuit, can be with reference voltage V _RefBe considered as " pseudo-ground (pseudo-ground) ".If line ERRP, the error voltage at ERRM place are reference voltage V _Ref, then do not have electric current to be driven; At this moment voltage duty cycle is 0%.If the error voltage at line ERRP, ERRM place is a slope clock RMP crest voltage separately, electric current will be driven constantly flows through VCM 9.For example, if the error voltage of line ERRP is positive crest voltage, and the error voltage of line ERRM is the peak level of bearing, and positive current will be driven and flow through VCM 9, and dutycycle is 100%.On the contrary, if the error voltage of line ERRP is negative crest voltage, and the error voltage of line ERRM is positive peak level, and then negative current will be driven and flow through VCM 9, and dutycycle also is 100%.

[0012] can consider the influence of power source change by example, in this example, supply voltage V _MBe 12 volts, the open-loop gain of driving stage is rated for 12, reference voltage V _RefBe ground.Therefore, when obtaining 100% dutycycle, mid point-crest voltage V of slope clock RMP _PeakCan obtain by following formula:

Because VCM 9 is an either-rotation motor, the P-to-P voltage slope of slope clock RMP in this case is 2 volts.If but the specified power supply voltage tolerance is ± 10%, supply voltage V _MJust can between 10.8 volts to 13.2 volts, change.At supply voltage V _M± 10% variation range in, with mid point-crest voltage V _PeakMaintain 1 volt, the open-loop gain of driving circuit will correspondingly change between 10.8 to 13.2.Therefore, supply voltage V _MVariation cause the respective change of open-loop gain.

[0013] described as the 6th, 374, No. 043 patent of the U.S. of authorizing on April 16th, 2002, in dual-mode voice coil motor driver circuits, it is the most obvious that these of open-loop gain change the influence that is brought.Under linear model, the FEEDBACK CONTROL that VCM drives will be eliminated the variation in power transistor 5 drivings.In addition, many D classes or pulse-width-modulated voice coil motor drive systems or pattern also comprise FEEDBACK CONTROL, and it will compensate the variation of the open-loop gain during the steady-state operation under this pattern.But dual-mode voice coil motor driver circuits such as No. 6374043 described circuit of patent of the U.S., is transformed into the PWM pattern from linear model.When changing, the open-loop gain of driving circuit will be controlled the driving of voice coil motor, can the error that produce be responded up to feedback control loop.Therefore, in the conversion between two kinds of drive patterns, the variation of the open-loop gain of " H " bridge of power transistor 5 shown in Figure 1 is very tangible.

Therefore [0014] in addition, some conventional disk drive systems do not make electricity consumption feed back the position of control data sensor, and also not electricity consumption is fed back and controlled voice coil motor, on the contrary, but carries out this control with mechanical positioner.In these conventional systems, the variation meeting of the open-loop gain of voice coil motor drive circuit directly influences the location of data transducer.Can think that these change in gain magnetic track that can extend is determined the time (track settling times), and under serious situation, may cause the location mistake.

Summary of the invention

[0015] therefore, the purpose of this invention is to provide the D class driving circuit of pulse-length modulation, the variation in the supply voltage is compensated in this circuit.

[0016] further aim of the present invention provides a kind of driving circuit, in this circuit, because the variation in the open-loop gain that mains voltage variations causes is compensated.

[0017] further object of the present invention provides a kind of driving circuit, and in this circuit, the variation of supply voltage can't cause the variation of PWM output frequency.

[0018] further object of the present invention provides a kind of disk drive system, and this system comprises one drive circuit, and this driving circuit is used to control the driving to voice coil motor, and voice coil motor is positioned on the selected disk track data transducer.

[0019] by with reference to following detailed description and accompanying drawing, those of ordinary skill in the art will understand other purpose and advantage of the present invention.

[0020] the present invention can implement in driving circuit, as in disc driver, can be used for driving voice coil motor so that data transducer or read/write head are positioned.The slope clock generator produces the waveform that compares with error signal, and the purpose of carrying out this comparison is to produce the pulse-length modulation output drive signal.The slope clock generator comprises control circuit, the supply voltage of its response output driving circuit, so that the voltage limit of slope clock or waveform slope, or the two is all modulated according to the variation of supply voltage.

Description of drawings

[0021] Fig. 1 is the circuit diagram of the conventional pulse-length modulation driving circuit that is used for voice coil motor represented with synoptic diagram.

[0022] Fig. 2 is the sequential chart of the conventional pulse-length modulation driving circuit operation of key diagram 1.

[0023] Fig. 3 is the circuit diagram of the disk drive system that makes up according to the preferred embodiments of the present invention represented with block diagram form.

[0024] Fig. 4 is the circuit diagram of representing with piece figure and schematic form according to the voice coil motor drive circuit in Fig. 3 system of the preferred embodiments of the present invention structure.

[0025] Fig. 5 is the sequential chart of the operation logic of the explanation preferred embodiment of the present invention.

[0026] Fig. 6 is a circuit diagram, and its explanation is according to the structure of the slope clock generator in the voice coil motor drive circuit of Fig. 4 of preferred embodiment of the invention structure.

Embodiment

[0027] the present invention will be described in conjunction with its preferred embodiment, also be implemented in the driving circuit of the voice coil motor in the modern computer disk drive system with regard to it, and this is because estimate that advantage provided by the invention is useful especially to this application.Yet, estimate that also the present invention is used for other application and also has superiority, and with reference to this instructions, this application is apparent to one skilled in the art.

[0028] Fig. 3 general description the disk drive system 10 that makes up according to the preferred embodiments of the present invention.Disk drive system 10 comprises one or more magnetic media disks 12, and it is by spindle motor 14 rotations in response to spindle driver circuit 16.Data transducer 18 is read/write heads of disk drive system 10, and is placed on the end of registration arm 17.Under the situation that a plurality of disks are arranged shown in Figure 1, a plurality of registration arm 17 are provided, each registration arm has one or more data transducers 18.Voice coil motor (VCM) 22 operation makes registration arm 17 rotate around pivot, so that data transducer 18 is placed on the optional radial track of disk 12.These radial track of disk 12 include magnetic track recognition data, positional information and are used for the synchrodata of disk drive system 10 operations.Data transducer 18 is used for user data record (" writing ") on disk and read user data from disk, to detect the signal of energy recognition data from this magnetic track that writes and sector, with the detection servo bursts, described servo pulse can laterally align read/write head just with the magnetic track of disk.

[0029] make read/write head 18 produce analog electrical signals in response to being recorded in the magnetic signal on the disk 12, described analog electrical signal is sent to data channel 13, to communicate by letter with result that the mainframe computer system (not shown) comes and goes.Be recorded in servosignal on the disk 12 in advance with numeral or analog form, detected and demodulation by one or more servo demodulator circuit (not shown), and handle to come the position of control data sensor 18 by anchor drive circuit 32 through digital signal processor (DSP) 30.The spindle driver circuit 16 of anchor drive circuit 32 and control spindle motor 14 can be realized in common microcontroller.Anchor drive circuit 32 also can be as required be integrated in the disk drive system 10 with other circuit.

[0030] with reference now to Fig. 4, the structure of anchor drive circuit 32 according to the preferred embodiment of the invention will be described now, this combination of circuits voice coil motor (VCM) 22 itself.Can know obviously that from this description anchor drive circuit 32 is double mode, its reason is that it not only comprises linear drive mode but also comprise pulse-length modulation (or D class) drive pattern.

[0031] power transistor 50 is arranged to conventional " H " bridge, flows through VCM 22 with drive current." height " side drive is provided by transistor 50PH, 50PL, and in this embodiment of the present invention, they all are N channel power metal-oxide semiconductor (MOS) transistors; As known in the art, if desired, also can use complementary MOS (CMOS) technology to drive VCM 22, in this case, transistor 50PH is exactly the P channel MOS transistor.Source electrode-drain path of high-side transistor 50PH, 50PL is connected in series in supply voltage V _MAnd between the ground.Similarly, " low " side drive is provided by transistor 50NH, 50NL, and its source electrode-drain path also is connected in series in supply voltage V _MAnd between the ground.Voice coil motor 22 is connected between node VCMP and the node VCMN, and node VCMP is between the drain electrode of the source electrode of transistor 50PH and transistor 50PL, and node VCMN is between the drain electrode of the source electrode of transistor 50NH and transistor 50NL.The voltage at node VCMP, VCMN place typically refers to " phase " voltage in this area.Current sense resistor 51 and VCM 22 are connected in series, and its sensing node ISP is between resistor 51 and VCM 22.

[0032] generally speaking, as known in the art, the relative driving that is applied to the grid of transistor 50 has determined to flow through the polarity and the value of the electric current of VCM 22.For example, if give the grid biasing of high side drive transistors 50PH, 50PL, make the difficult conducting of the relative transistor 50PL of transistor 50PH, give the grid biasing of low side drive transistor 50NH, 50NL, make the difficult conducting of the relative transistor 50NH of transistor 50NL, the phase voltage of node VCMP is just than the phase voltage height of node VCMN.This can produce electric current, and it comes from transistor 50PH, and conduction flow is crossed VCM 22, and leads away by transistor 50NL, and this can cause VCM 22 that registration arm 17 is rotated around pivot along a direction.On the contrary, if the grid of high side drive transistors 50PH, 50PL is by biasing, make the difficult conducting of the relative transistor 50PL of transistor 50PL, the grid of low side drive transistor 50NH, 50NL is by biasing, make the difficult conducting of the relative transistor 50NL of transistor 50NH, the phase voltage of node VCMN is just than the phase voltage height of node VCMP.This can produce electric current, and it comes from transistor 50NH, and conduction flow is crossed VCM 22, and leads away by transistor 50PL, and this can cause VCM 22 that registration arm 17 is rotated around pivot along opposite direction.

[0033] therefore, be applied to polarity and the value that Control of Voltage conduction flow on transistor 50 grids is crossed the electric current of VCM22.What anchor drive circuit 32 was realized in the disk drive system 10 of Fig. 3 is exactly this function.

[0034] again with reference to figure 4, in the linear side of anchor drive circuit 32, the voltage of current sense amplifier 34 receiving node VCMP and node ISP is imported as it, and produces a signal, this signal is corresponding to the pressure drop at resistor 51 two ends, therefore corresponding to the electric current that flows through VCM 22.This signal and the input end addition of control voltage VDAC at error amplifier 36; Another input of error amplifier 36 receives reference voltage VREF.Error amplifier 36 comprises compensation feedback or the network 37 that is connected between its input and output, its objective is the stability in order to move, as known in the art.Error amplifier 36 is output as error signal, and it is corresponding to a difference, and this difference is expectation voltage VDAC and one corresponding to the voltage sum of the momentary current level by the VCM22 difference with respect to reference voltage VREF.This error signal and be applied to linear prestage drivers 38 together corresponding to the feedback signal of the phase voltage of node VCMP, VCMN.In response to this error signal and phase voltage, linear prestage drivers 38 flows through driven bridge transistor 50PH, 50PL, the 50NH of the electric current of VCM 22, the grid of 50NL with qualification, control the motion when the track location of seeking or following the tracks of expectation on the disk 12 of registration arm 17 and sensor 18 (Fig. 1) subsequently.

[0035] U.S. the 6th, 374, and No. 043 patent provides the structure of the linear prestage drivers 38 that can use in conjunction with the present invention and the additional detail of operation.The Linear actuator that expectation is used for other structure of voice coil motor 22 also can alternatively use in conjunction with the present invention.

[0036] in the PWM of anchor drive circuit 32 side, the error signal of error amplifier 36 outputs is sent to an input end of differential amplifier 40; Second input end of differential amplifier 40 receives reference voltage V _Ref Differential amplifier 40 produces differential output signal, and it is corresponding to the error signal and the reference voltage V of error amplifier 36 outputs _RefBetween difference.Export the input of device 42P as a comparison for one of differential amplifier 40, and another of differential amplifier 40 exported the input of device 42N as a comparison.Comparer 42P, 42N compare these inputs separately with the slope clock signal RAMP that is produced by slope clock generator 48.As below describing in detail, slope clock generator 48 is according to supply voltage V _MProduce slope clock signal RAMP.According to the fiducial value between its input that receives from differential amplifier 40 and the slope clock signal RAMP, comparer 42P, 42N respectively produce full swing (full-rail) output signal, and the logic level that produces is offered PWM pre-stage driver 46, and PWM pre-stage driver 46 produces the drive signal of the grid that is applied to transistor 50 again.The operation of the power transistor 50 in " H " bridge shown in Figure 4 and above description about Fig. 1 are corresponding.In this manner, the transistor 50 in " H " bridge produces and is applied to the pulse-width-modulated current of VCM 22, and controls its rotation and motion.

[0037], now operation logic of the present invention is described with reference now to Fig. 5.Slope clock signal RMP is specified slope clock signal, thereby is to have maximum level V _HWith minimum levels V _LTriangular waveform.Alternatively, slope clock signal RMP can be zig-zag, or the waveform that becomes when can be used for producing another of pulse-length modulation output signal; Yet this instructions refers to triangular waveform, is appreciated that the present invention also can be applied to other waveform shape similarly.In this example, pseudo-voltage V _RefBe actually ground connection, or 0 volt, slope clock signal RMP has the positive polarity skew and negative polarity is offset voltage V _H=-V _LError voltage ERRP, the ERRM of 100% dutycycle shown in Figure 5 are respectively voltage V _H, V _LIn this example, the cycle of slope clock signal RMP is a time T.

[0038] as mentioned above, the open-loop gain of main anchor drive 32 on " H " of power transistor 50 bridge can be along with supply voltage V _MVariation and change.Find, according to the present invention, can be by changing the peak amplitude V of slope clock signal _Peak, compensate this change in gain, the peak amplitude V of this slope clock signal _PeakBe supply voltage V _MFunction, shown in equation (1).This can cause the variation of the dutycycle of output pwm signal, and it compensates the variation of the open-loop gain that is caused by mains voltage variations.For example, if supply voltage V _MIncrease peak amplitude V from its ratings _PeakAlso can increase, this dutycycle that can cause output pwm signal reduces.On the contrary, supply voltage V _MReduce peak amplitude V by the slope clock signal _PeakReduce compensate, this can cause the increase of PWM dutycycle, it has compensated the open-loop gain that reduces.

Find further that [0039] when the amplitude of slope clock changes to slope clock signal RMP ', the frequency of slope clock signal RMP ' also can change, be corrected unless be used for producing the current source of resultant current at the slope clock circuit.In many application, this frequency preferably is corrected, because the slope clock frequency directly is controlled at total PWM frequency of output.Yet,, can select all or part of correction slope clock frequency according to the preferred embodiment of the invention.

[0040] in example shown in Figure 5, according to the preferred embodiment of the invention, slope clock signal RMP ' and offset supply voltage V _MThe slope clock signal of increase corresponding.In this example, the frequency of the slope clock signal RMP ' of compensation also is adjusted, and is complementary with the frequency with specified slope clock signal RMP, as below describing.The slope clock signal RMP ' of compensation is from maximum voltage V _H'=V _H+ Δ V _HBe displaced to minimum voltage V _L'=V _L+ Δ V _L, its frequency is identical with the frequency of slope clock signal RMP.Voltage Δ V _H, Δ V _LWith supply voltage V _MChanges delta V _MBetween relation can be expressed as:

$\frac{{\mathrm{\ΔV}}_H}{V_H}=\frac{{\mathrm{\ΔV}}_L}{V_L}=\frac{{\mathrm{\ΔV}}_M}{V_M}---\left(2\right)$

As ise apparent from FIG. 5, for the slope clock signal RMP ' that makes compensation keeps and the identical frequency of slope clock signal RMP, the slope of the slope clock signal RMP ' of compensation becomes new slope m ' from the slope of specified slope clock signal RMP:

$m^{\′}=\frac{{V_H}^{\′}}{T/4}=\frac{4(V_H+{\mathrm{\ΔV}}_H)}{T}---\left(3\right)$

It is a certain amount of that this compensation can make that the PWM dutycycle reduces, and the slope clock signal RMP ' of the corresponding compensation of this reduction is greater than error voltage ERRP or less than the time Δ t (the full dutycycle of the specified slope clock signal RMP generation of this example neutralization compares) of error voltage ERRM.The variation of dutycycle (being expressed as the mark of whole period T) is:

$\frac{\mathrm{\Δt}}{T}=\frac{{4\mathrm{\ΔV}}_H}{m^{\′}T}---\left(4\right)$

Can represent the variation of dutycycle with in equation (2) the substitution equation (3), obtain:

$\frac{\mathrm{\Δt}}{T}=\frac{{\mathrm{\ΔV}}_H}{V_H+{\mathrm{\ΔV}}_H}=\frac{1}{(1+\frac{V_H}{{\mathrm{\ΔV}}_H})}---\left(5\right)$

Wherein, consider equation (2), can use supply voltage V _MVariation following formula is expressed as:

$\frac{\mathrm{\Δt}}{T}=\frac{1}{(1+\frac{V_M}{{\mathrm{\ΔV}}_M})}---\left(6\right)$

This compensating for variations of dutycycle the variation of the open-loop gain that causes by mains voltage variations.

[0041] shown in the example of Fig. 5, constant for holding frequency, the slope m ' of slope clock signal RMP ' is changed to respect to the slope m's of specified slope clock signal RMP:

$\frac{m^{\&prime;}}{m}=\frac{{V_H}^{\&prime;}/\frac{T}{4}}{V_H/\frac{\mathrm{<figure-callout\; id="4"\; label="T"\; filenames="A20058001738400241.png"\; state="\{\{state\}\}">T</figure-callout>}}{4}}=\frac{{V_H}^{\&prime;}}{V_H}=1+\frac{V_H}{{\mathrm{\&Delta;V}}_H}---\left(7\right)$

Or:

$\frac{m^{\&prime;}}{m}=1+\frac{V_M}{{\mathrm{\&Delta;V}}_M}---\left(8\right)$

Slope m, m ' are corresponding to the charge rate and the discharge rate of conventional ramp generator.For example, charging and the discharge of a class ramp generator based on capacitor arranged, its certainly corresponding to:

$i=C\frac{\mathrm{dV}}{\mathrm{dt}}=C\&CenterDot;m---\left(9\right)$

As a result, for slope is changed to m ' from m, must change the charging current (and discharge current) that is applied to the capacitor in the ramp generator:

$\frac{i^{\&prime;}}{i}=\frac{m^{\&prime;}}{m}=\frac{1+{\mathrm{\&Delta;V}}_m}{V_M}---\left(10\right)$

So that the difference DELTA i=i ' of charging current and discharge current-i is corresponding to the difference of supply voltage:

$\frac{\mathrm{\&Delta;i}}{i}=\frac{{\mathrm{\&Delta;V}}_M}{V_M}---\left(11\right)$

As mentioned above, according to the variation of supply voltage, charging and discharge current in the modulation ramp generator, the frequency that can keep the slope clock signal is constant, and still compensates the variation of open-loop gain.

[0042] as known in the art, the ramp generator circuit of other type also is known in this area.For example, another kind of ramp generator circuit comprises integrator, and the output signal of its generation is corresponding to the integration of step function pulse.The speed of integration generally is to be determined by the feedback condenser of operation amplifier circuit.Therefore, those skilled in the art will be appreciated that slope from the output ramp signal of this ramp generator circuit can change capacitance and modulate according to the variation of supply voltage.Can estimate those skilled in the art with reference to behind this instructions, can be easily the slope of the ramp signal in these and other selectable ramp generator circuit be modulated, thereby it be constant to keep the PWM frequency.

[0043] as mentioned above, in some applications, the frequency that allows the slope clock signal is along with the variation of supply voltage is modulated, as long as dutycycle is modulated to compensate the respective change of open-loop gain, this is an acceptable.Also have further and select, can estimate, if desired, can partly proofread and correct the slope of slope clock signal, reduce the variation of frequency.Along with the variation of dutycycle, allow frequency modulation (PFM) to be determined as required to which kind of degree this depends on the application-specific of the preferred embodiment of the present invention by the deviser.

[0044] in each case, with respect to corresponding rated supply voltage V _MRatings, the compensation of the slope of the compensation of PWM dutycycle and slope clock signal can be used when disk drive system powers up.Preferred monitoring in real time or measurement supply voltage V _M, so that the slope of PWM dutycycle and slope clock signal RMP can be regulated at run duration.

[0045] therefore, according to the preferred embodiment of the invention, the variation of the open-loop gain that the dutycycle that reduces PWM operation is caused by the variation of the supply voltage on the power transistor 50 that is applied to " H " bridge output driving circuit with compensation.With reference now to Fig. 6,, describes the structure of ramp generator 48 according to the preferred embodiment of the invention in detail.This specific examples of ramp generator 48 is based on the charging and the discharge of time capacitor, and with described.In view of each ramp generator circuit all must comprise an element or other parameter, control the voltage limit value of slope clock signal, and thereby its slope of control is controlled its frequency, so estimate that those skilled in the art after with reference to this instructions, can easily apply to the present invention in the ramp generator circuit of other type in a similar fashion.

[0046] as shown in Figure 6, the plate that time capacitor 60 has is connected to charge node CN, another relative plate earthing.The variation of considering output slope clock signal RMP can also can be negative polarity for positive polarity, and current source 62H and current source 62L are connected in series between bias voltage V+ and the bias voltage V-.In this was connected in series, switch 64H was connected in series between current source 62H and the charge node CN, and switch 64L is connected in series between charge node CN and the current source 62L.Switch 64L, 64H are by level detector 66 controls, below with described.

[0047] input of impact damper 61 is connected to charge node CN, and its output is used as slope clock signal RMP, and also sends to level detector 66.Signal on level detector 66 acceptance line VH, the VL, they are upper voltage limit and the lower voltage limit of slope clock signal RMP.Level detector 66 compares with the instantaneous voltage of slope clock signal RMP with corresponding to the upper voltage limit and the lower voltage limit of the signal on line VH, the VL, and the state of corresponding gauge tap 64H, 64L.In service, switch 64H is closed, and switch 64L is that (shown in the example of Fig. 6) opened is to charge to capacitor 60.In case reach upper voltage limit corresponding to the signal on the line VH from the voltage in impact damper 61 output of charge node CN, level detector 66 is just opened switch 64H and Closing Switch 64L, with the discharge of beginning half period.Capacitor 60 discharges by current source 62L then, reach lower voltage limit up to voltage corresponding to the signal on the line VL from impact damper 61 output of charge node CN, in view of the above the recharge semiperiod, level detector 66 is opened switch 64L and Closing Switch 64H.In this mode, charging semiperiod and discharge semiperiod continue to carry out.

Can find out obviously from this description that [0048] frequency of charging semiperiod and discharge semiperiod depends on the electric current of current source 62H, 62L.In this embodiment of the present invention, the control signal that frequency control circuit 65 produces current source 62H, 62L is to control these chargings and discharge current.As known in the art, current source 62H, 62L can realize that in this case, frequency control circuit 65 applies suitable grid voltage these current levels are set with MOS transistor.Generally, the rated frequency of ramp generator 48 operations is controlled decision by design or by the user at least.

[0049] according to a preferred embodiment of the invention, upper voltage limit and the lower voltage limit that is sent to level detector 66 from line VH, VL is according to supply voltage V _MChange modulates, its modulation system is the above-mentioned mode of describing with reference to Fig. 5.In this example, ramp generator 48 comprises voltage comparator and slope clock controller circuit 68, and it receives supply voltage V _M, and reference voltage VREG, supply voltage compares or measures with respect to reference voltage VREG.Can be produced by bandgap reference circuit, voltage regulator or another custom circuit with reference to electric VREG, the reference voltage that this custom circuit produces does not rely on supply voltage V basically _MAccording to the preferred embodiment of the invention, voltage comparator and slope clock controller circuit 68 comprise a suitable circuit, and it is with supply voltage V _MVREG compares with reference voltage, and according to suitable upper voltage limit signal and the lower voltage limit signal of the last generation of the online VH of this comparative result, VL, delivers to level detector 66.Estimate that those skilled in the art with reference to behind this instructions, can easily derive the suitable detailed circuit that is used for voltage comparator and slope clock controller circuit 68.

[0050] therefore, be in operation, by to send appropriate signals, supply voltage V on the above-mentioned online VH of mode, the VL that describes with reference to Fig. 5 _MIncrease can make voltage comparator and slope clock controller circuit 68 improve upper voltage limit and lower voltage limit that level detectors 66 use.On the contrary, by online VH, send appropriate signal on the VL, supply voltage V _MReduce can make voltage comparator and slope clock comparator circuit 68 reduce upper voltage limit and lower voltage limit that level detector 66 uses.Under each situation, the crest voltage V of slope clock signal RMP _PeakAccording to supply voltage V _MLevel modulate, this dutycycle that can cause aforesaid output pwm signal changes.The variation of dutycycle can compensate because supply voltage V _MThe variation of the open-loop gain that causes of variation.

[0051] according to a preferred embodiment of the invention, the frequency of slope clock signal RMP can be according to supply voltage V _MVariation control.As shown in Figure 6, voltage comparator and slope clock controller circuit 68 also have the output that is connected to frequency control circuit 65.Voltage comparator and slope clock controller circuit 68 therefore can be according to supply voltage V _MWith the comparative result of reference voltage VREG, send control signal to frequency control circuit 65.Therefore, the signal that sends according to voltage comparator and slope clock controller circuit 68 of frequency control circuit 65 is adjusted its bias voltage or is applied to the control signal of current source 62H, 62L.As mentioned above, if supply voltage V _MIncrease, to such an extent as to voltage comparator and slope clock controller circuit 68 increase crest voltage V _PeakThereby reduce the PWM dutycycle, voltage comparator and slope clock controller circuit 68 also can send control signal to frequency control circuit 65, also increase so that come from charging current and the discharge current of current source 62H, 62L, thereby the frequency of keeping slope clock signal RMP are constant.On the contrary, lower supply voltage V _MCan cause that voltage comparator and slope clock controller circuit 68 send signal to frequency control circuit 65, flow through the electric current of current source 62H, 62L, keep the constant frequency of slope clock signal RMP and lower voltage peak V with minimizing _PeakConsistent.Yet, as mentioned above, be optional to this control of slope clock signal RMP frequency.In addition, part control if desired, this frequency can be conditioned, with the only variation of part compensated peak voltage.

[0052] therefore, according to the preferred embodiment of the invention, the variation of the open-loop gain of the pulse width modulating signal that is caused by the variation of supply voltage is changed by the limit value of slope clock signal and compensates.In addition, the frequency that can keep the slope clock signal is constant, or can partly adjust if desired.Be used for aspect the voice coil motor of disk drive, this compensation of open-loop gain variations has improved the positional accuracy of data transducer or read/write head.In the dual-mode voice coil motor controller, be especially tangible in the conversion of the raising of accuracy between drive pattern, in the disk drive system that the mechanical positioning of those use data transducers and registration arm is controlled, also be clearly.

[0053] invention has been described according to the preferred embodiment of the invention, think that certainly those skilled in the art is after with reference to this instructions and accompanying drawing, meeting is obviously understood the modification that the embodiments of the invention are made and is substituted, and reaches advantage or benefit that this modification and alternative energy obtain from the present invention.

Claims (17)

1. pulse width modulation drivers circuit, it comprises:

First driver is right, and it comprises first and second transistors, and their conductive channel is connected in series between supply voltage and the ground voltage, and described first and second transistors respectively have a control end;

Pulse width modulation circuit, the comparative result that it is used for according to error signal and slope clock signal produces first pulse width modulating signal;

First pulse width modulation drivers, it has an input of connection, receiving described first pulse width modulating signal, and a plurality of outputs that are connected to the described first and second transistorized described control ends; With

The slope clock generator, it is used to be created in periodically variable slope clock signal between the upper and lower bound, and described slope clock generator comprises a circuit, and this circuit is used for the variation according to supply voltage, changes described upper and lower bound.

2. circuit according to claim 1, wherein said pulse width modulation circuit also are used for the result that compares according to described error signal and described slope clock signal, produce second pulse width modulating signal; Further comprise:

Second driver is right, and it comprises third and fourth transistor, and their conductive channel is connected in series between described supply voltage and the ground voltage, and described third and fourth transistor respectively has a control end; With

Second pulse width modulation drivers, it has an input of connection, to receive described second pulse width modulating signal and to be connected to a plurality of outputs of the described third and fourth transistorized described control end.

3. circuit according to claim 1, further comprise the load that is connected between first node and the Section Point, the junction of described first node between the described first and second transistorized described conductive channels, the junction of described Section Point between the described third and fourth transistorized described conductive channel.

4. circuit according to claim 1, wherein said slope clock generator further comprises: a circuit, the variation that it is used for according to described supply voltage changes the slope of described slope clock signal.

5. circuit according to claim 1, wherein said slope clock generator comprises:

Time capacitor;

Charging circuit, it is used for periodically described time capacitor being charged;

Discharge circuit, it is used for periodically described time capacitor being discharged;

Level detector, it is used to detect the voltage at described time capacitor place, be used to control described charging circuit, when reaching described, described detected voltage prescribes a time limit down, described time capacitor is charged, also be used to control described discharge circuit, go up in limited time, described time capacitor is discharged when described detected voltage reaches described; With

Control circuit, it is used to measure described supply voltage and according to the supply voltage of described measurement, sends the described upper limit and described lower limit to described level detector.

6. circuit according to claim 5, wherein said charging circuit comprises first current source, it conducts charging current to described time capacitor according to first control signal; Wherein, described discharge circuit comprises second current source, and it conducts discharge current to described time capacitor according to second control signal; And further comprise frequency control circuit, it is used for described first and second control signals are applied to described first and second current sources, with the supply voltage according to described measurement, controls described charging current and described discharge current.

7. the method for a gating pulse width modulated driving circuit, it comprises:

Be created in periodically variable slope clock signal between the upper and lower bound;

Error signal and described slope clock signal are compared;

According to the comparative result of described error signal and described slope clock signal, produce first pulse width modulating signal that is in a dutycycle;

According to described first pulse width modulating signal, drive the control end of first pair of driver transistor, the conductive channel of described first pair of driver transistor is connected in series between supply voltage and the reference voltage;

When described supply voltage is higher than ratings, reduce the described dutycycle of described first pulse width modulating signal; With

When supply voltage is lower than described ratings, improve the described dutycycle of described first pulse width modulating signal.

8. method according to claim 7, wherein said reduction step comprise the described upper limit of raising; With the described lower limit of reduction.

9. method according to claim 8, wherein said raising step comprise the described upper limit of reduction; With the described lower limit of raising.

10. method according to claim 9 further comprises: when described supply voltage is higher than described ratings, improve the described slope of the described slope clock signal between the described lower limit and the described upper limit; And when described supply voltage is lower than described ratings, reduce the described slope of the described slope clock signal between the described lower limit and the described upper limit.

11. method according to claim 9, wherein, the described step that produces described slope clock signal comprises with charging current charges to described time capacitor; Voltage on described time capacitor reaches described to be gone up in limited time, with discharge current described time capacitor is discharged; Reach described in limited time following with the described voltage on described time capacitor, repeat described charge step.

12. method according to claim 11 further comprises: when described supply voltage is higher than described ratings, increase described charging and discharge current; With when described supply voltage is lower than described ratings, reduce described charging and discharge current.

13. a disk drive system, it comprises:

Disk;

Registration arm, it stretches on described disk;

Data transducer, it is installed in the far-end of described registration arm;

Voice coil motor, the near-end that it is connected in described registration arm is used to make described registration arm to rotate around pivot;

First driver is right, it comprises first and second transistors, their conductive channel is connected in series between supply voltage and the ground voltage, described voice coil motor is connected in the node of the join between the described first and second transistorized described conductive channels, and described first and second transistors respectively have a control end;

Pulse width modulation circuit, it is used for producing first pulse width modulating signal according to the comparative result of error signal and slope clock signal;

The first pulsed modulation driver, it has an input of connection, to receive described first pulse width modulating signal and to be connected to a plurality of outputs of the described first and second transistorized described control ends; With

The slope clock generator, it is used to be created in periodically variable slope clock signal between the upper and lower bound, and described slope clock generator comprises a circuit, and this circuit is used for the variation according to described supply voltage, changes the described upper limit and described lower limit.

14. system according to claim 13, wherein said pulse width modulation circuit also is used for the comparative result according to described error signal and described slope clock signal, produces second pulse width modulating signal; Further comprise:

Second driver is right, it comprises third and fourth transistor, their conductive channel is connected in series between described supply voltage and the ground voltage, described voice coil motor is connected in the node of the junction between the described third and fourth transistorized described conductive channel, and described third and fourth transistor respectively has a control end; With

Second pulse width modulation drivers, it has an input of connection, to receive described second pulse width modulating signal and to be connected to a plurality of outputs of the described third and fourth transistorized described control end.

15. system according to claim 13, wherein said slope clock generator further comprises a circuit, and this circuit is used for according to mains voltage variations, changes the described slope of described slope clock signal.

16. system according to claim 13, wherein said slope clock generator comprises:

Time capacitor;

Charging circuit, it is used for periodically described time capacitor being charged;

Discharge circuit, it is used for periodically described time capacitor being discharged;

Level detector, it is used to detect the voltage of described time capacitor, be used to control described charging circuit, when reaching described, detected voltage prescribes a time limit down, described time capacitor is charged, with be used to control described discharge circuit, go up in limited time when detected voltage reaches described, described time capacitor is discharged; With

Control circuit, it is used to measure described supply voltage and is used for sending the described upper limit and described lower limit to described level detector according to measured supply voltage.

17. system according to claim 16, wherein said charging circuit comprises first current source, and it is used for according to first control signal charging current being conducted to described time capacitor; Wherein said discharge circuit comprises second current source, and it is used for according to second control signal discharge current being conducted to described time capacitor; And further comprise frequency control circuit, it is used for described first and second control signals are applied to described first and second current sources, to control described charging and discharge current according to measured supply voltage.

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