CN1956182A - Semiconductor mount circuit board, semiconductor device and method of manufacturing semiconductor package - Google Patents

Semiconductor mount circuit board, semiconductor device and method of manufacturing semiconductor package Download PDF

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Publication number
CN1956182A
CN1956182A CN 200610136578 CN200610136578A CN1956182A CN 1956182 A CN1956182 A CN 1956182A CN 200610136578 CN200610136578 CN 200610136578 CN 200610136578 A CN200610136578 A CN 200610136578A CN 1956182 A CN1956182 A CN 1956182A
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CN
China
Prior art keywords
subregion
circuit board
semiconductor
resin
prostatitis
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CN 200610136578
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Chinese (zh)
Inventor
越智岳雄
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN1956182A publication Critical patent/CN1956182A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Abstract

The invention discloses a semiconductor mount substrate, semiconductor device and method of manufacturing semiconductor package. Segments formed on a wiring substrate are arranged in a staggered array, and tie bars are provided between the segments.

Description

Semiconductor mount circuit board and semiconductor device and manufacturing method of semiconductor module
Technical field
The ball bar battle array) the present invention relates to semiconductor mount circuit board and semiconductor device and manufacturing method of semiconductor module, relate in particular to BGA (Ball Grid Array: the technology of semiconductor subassembly such as.
Background technology
In recent years, many pins of semiconductor subassembly, densification rapid progress.Four line flat packs) etc. in the past, in this semiconductor subassembly, though lead frame type QFP (Quad Flat Package: be main flow,, use the BGA assembly of circuit board to form main flow day by day as the more favourable assembly of terminal density.
The manufacture method of BGA assembly, the general elder generation of its main stream approach is divided into each semiconductor subassembly with each semiconductor device after a wiring circuit forms a plurality of semiconductor device.In recent years, in order to boost productivity, the many array types assembly that a plurality of semiconductor device is formed 2 row on wiring circuit is on the increase.
Below, the BGA component technology that a plurality of semiconductor device is formed 2 row on wiring circuit is described.Figure 21 A illustrates the semiconductor device sealing state of existing wiring circuit, and Figure 21 B illustrates the state that each semiconductor device is divided into individual components.Figure 21 A and Figure 21 B show the chip and the lead of sealing resin section in the mode of penetrating.
Among Figure 21 A and Figure 21 B, 1 expression frame portion (connecting portion), the subregion portion (being divided into the zone of each assembly) in 2 expression prostatitis, 3 expression prostatitis are with being bar, the runner in 4 expression prostatitis, the subregion portion (zone that is divided into each assembly) of 5 expression rank rears, 6 expression rank rears are with being bar, 7 expression rank rear runners, 8 expression peristomes, 9 expression angle holes, BGA packaging part after 10 expressions are divided, 11 expression chips (semiconductor element), 12 expression wirings, the resin-sealed portion of 13 expressions, 14 expression geats, 15 expressions divide the runner of supporting the front.
Shown in Figure 21 A, the state that connects each subregion portion 2,5 with the frame portion 1 of wiring circuit S is loaded into each subregion portion 2,5 with chip 11, after with lead 12 chip 11 being connected to circuit board electrode,, thereby form resin-sealed 13 with sealing resin sealing chip 11 and lead 12.
Form than subregion portion small scale one circle of wiring circuit S with resin-sealed 13.Its reason is in order to prevent that resin from escaping to the outside from the subregion portion 2,5 of wiring circuit S.Form each limit of resin-sealed 13 parallel with each limit of the subregion portion 2,5 of circuit board.
Be configured to each subregion portion 2,5 and sealing resin section 13 rectangular regularly.At frame portion 1 configuration runner 4,7,15.Runner 4,7,15 forms the resin feed path to resin-sealed 13 in the sealing metal mould.In the explanation hereinafter, under the implication of the resin that in the cavity of sealing metal mould or cavity, hardens, use runner 4,7,15 and resin-sealed 13.
The peristome 8 on every side that is arranged on each subregion portion 2,5 surrounds the other parts of subregion portion 2,5 except that the bight of each subregion portion 2,5.Has geat 14 at an angle for resin-sealed 13.
Carry out when resin-sealed with the sealing metal mould, sealing resin enters into the zone in the circuit board from the outside of wiring circuit S, sealing resin by runner 15 toward the vertical direction of the circuit board circumference of frame portion 1 is entered.Runner 15 bends to the angle of 45 degree as prostatitis runner 4 and rank rear runner 7 in the bight of each subregion portion 2,5.
Sealing resin enters into resin-sealed 13 geat 14 by prostatitis runner 4 and rank rear runner 7, supplies with resin-sealed 13 of subregion portion 2,5 of prostatitis and rank rear simultaneously from runner 4,7 both sides.
In the above-mentioned composition, when disconnecting geat, when promptly, making runner 4,7 break away from sealing resin section 13 behind the hardening of resin, to the moment around the axis of the orthogonal axe of runner 15 or with moment loading around the axis of the parallel axes of runner 15 in runner 4,7,15, at geat 14 with runner 4,7 bendings.
Yet in the wiring circuit that existing BGA assembly and this assembly are used, runner 4,7 enters 45 degree that stagger between the angle of resin-sealed 13 angle of subregion portion 2,5 and the frame portion 1 that runner 15 enters wiring circuit S.
And, arriving the runner distance of runner 15,7 of the subregion portion 5 of rank rear, runner 15,7 all adheres to wiring circuit S on its whole length, so it is big to peel off the required power of runner 15,7 from wiring circuit S when cutting off geat.
Therefore, when cutting off geat, to the big stress of runner 4,7,15 effects, this stress acts on this face to the runner 4,7 of geat 14 and resin-sealed 13 composition surface skew 45 degree crustal inclination, thereby exists the part of runner 4,7 to remain in geat 14 or produce breach or resin-sealed 13 problem of peeling off easily at resin-sealed 13.
Method as solving these problems has: make runner 15 linearities that enter subregion portion 1 from the outside of this wiring circuit S enter the middle position of subregion portion 2,5, and crooked halfway.
Yet in this case, in forming resin-sealed 13 the cavity of sealing metal mould, sealing resin is fully diffusion, exists sealing resin stream to be stranded in the problem of resin-sealed 13 middle position.Therefore, when resin-sealed 13 scale is big, near easy 2 bight residual clearance (not potting resin) geat 14.
In order to relax this situation, need (being in resin-sealed 13) in the sealing metal mould to guarantee the state that sealing resin fully flows diffusely.Therefore, need form geat 14 wide, but this is unrealistic being about to arrive the stream of widening runner before resin-sealed 13, its reason be as follows.
It is smooth and easy to peel off runner during in order to ensure the cut-out geat, and wiring circuit generally forms plated portions in the regulation zone corresponding with runner.Therefore, there is the shortcoming that reduces because of the wiring region that expands the plated portions wiring circuit.
In lead frame type assembly, for example disclosed technology of the clear 60-137049 communique of patent disclosure of Japan's patent gazette is arranged.The method that this technology proposes reduces lead and the chip resistance to sealing resin stream by with bonding angle tilt 45 degree, or reduces the stress behind the hardening of resin.Again, the method that the patent disclosure 62-152130 communique of Japan's patent gazette proposes by subregion portion is spent runner direction inclination 45, makes the sealing resin of runner flow smooth and easy.
These schemes are considered sealing resins stream, and are more effective than in the past technology.Yet, be not the best solution of space problems such as (not potting resins) in the bight of problem during to above-mentioned cut-out geat and resin-sealed portion.
As look-ahead technique, the disclosed technology of the flat 4-276414 communique of patent disclosure of Japan's patent gazette is arranged.This technology makes the runner that enters wiring circuit from the outside, enters the central part of the module portion (cavity) that forms sealing resin section with linearity, and is crooked halfway.On wiring circuit, form notch from its outer peripheral edges portion to module portion.
According to this composition, during sealing resin, forming runner with the corresponding position of notch.The geat equivalence portion of the geat of pressing close to connection module portion of this runner does not engage with wiring circuit.Therefore, the part runner residues in geat when preventing to cut off geat, prevents that resin-sealed produces breach or resin-sealed and peel off from wiring circuit.
Yet in this structure, runner does not engage with wiring circuit on the whole runner distance of arrival geat, becomes the structure that supports runner at the geat single armed.Under the situation of runner distance, the load of long runner acts on the narrow cross section of folder of geat, forms fragile supporting construction.
Therefore, the semiconductor device that forms a plurality of resin-sealed portions on the wiring circuit is transported to follow-up geat from resin-sealed operation cuts off waiting of operation midway, since error in operation and to runner toward beyond directive effect power the time, the problem that exists runner to cut off with the state of non-hope.
The present invention solves above-mentioned problem, its purpose can realize with the easiest method to provide a kind of, the space well, does not take place in the geat cuttability and be fit to semiconductor mount circuit board and the semiconductor device and the manufacture method of many arrays.
Summary of the invention
In order to solve above-mentioned problem, semiconductor mount circuit board of the present invention, it is a kind of wiring circuit, this wiring circuit is arranged a plurality of subregion portion with linearity uniformly-spaced, form the subregion group, and a pair of described subregion group is arranged in parallel, and along circuit board circumference configuration outside connecting portion, surround the subregion group in prostatitis and the subregion group of rank rear, described subregion portion has the mounting semiconductor district, internal terminal, and outside terminal, wherein, with prostatitis subregion group and rank rear subregion group's arrangement pitch half spacing that staggers mutually, make described subregion portion be arranged in staggered palisade, the rank rear that the described subregion portion in the prostatitis disposes the described subregion portion that connects rank rear and described outside connecting portion each other is with being bar, disposes the prostatitis of the described subregion portion in connection prostatitis and described outside connecting portion each other with being bar in the described subregion portion of rank rear.
According to said structure, the prostatitis be bar and rank rear with being that the runner that forms on the bar connects into linearity, the geat of the resin-sealed portion that subregion portion is formed does not form bending.Its result, the stress equalization that produces on the runner when geat cuts off act on each position of direction of the orthogonal axe of geat upper edge and runner, thereby the raising of geat cuttability.
By prostatitis subregion portion and rank rear subregion portion are configured to staggered palisade, rank rear can be used is that bar is configured between each subregion portion in prostatitis, it is that bar is configured between the subregion portion of rank rear that the prostatitis is used, thereby can on wiring circuit, efficient be that layout is carried out in the required space of bar to formation well, improve the service efficiency of wiring circuit.
Semiconductor mount circuit board of the present invention utilizes peristome, with the described subregion portion in prostatitis and described rank rear be between the bar and the described subregion portion of rank rear and described prostatitis with being to separate between the bar.
Form according to this, can will be in the past half of the intensive one-tenth of bar, thereby improve the efficient of the cutting action that is divided into each subregion portion.
Semiconductor mount circuit board of the present invention, between the subregion group of the subregion group in prostatitis and rank rear, dispose middle interconnecting piece, around described subregion portion, form peristome, also forming described prostatitis between described outside connecting portion and the described subregion portion and between described middle interconnecting piece and the described subregion portion with being that bar and described rank rear are with being bar simultaneously, the described subregion portion in prostatitis forms the notch from the circuit board circumference of a side to described middle interconnecting piece each other, and the described rank rear that connects the described subregion portion of rank rear and described middle interconnecting piece is with being that bar is positioned on the axis of described notch.
Semiconductor device of the present invention is by to the apex linearity of resin-sealed portion configuration runner, makes that to flow into the resin flow of resin-sealed portion from geat smooth and easy, can reduce the space.And each limit of the circumference by resin-sealed portion is parallel to each limit of the periphery of its relative subregion portion, can make the scale of resin-sealed portion accomplish maximum with respect to subregion portion.
Semiconductor device of the present invention, the profile of resin-sealed portion forms octagon, and each limit of the profile of described sealing resin section is to each limit of the periphery of described subregion portion 45 degree or parallel with each limit of the profile of described sealing resin that tilt.
According to above-mentioned composition, by making resin-sealed for octagon, can have nothing to do to each limit of the scale of the resin-sealed portion of subregion quality award from the ministryization and each subregion portion angle with the circuit board circumference.
Semiconductor device of the present invention, the profile of resin-sealed portion forms pentagon, and the 1st apex of described sealing resin section is positioned at described prostatitis with being bar and described rank rear with being on the axis of bar.
According to above-mentioned composition, by resin-sealed portion is taken as pentagon, and pentagonal the 1st apex is taken as inlet, make in resin-sealed resin flow smooth and easy from geat, resin flows toward opposed the 1st limit from pentagonal apex, thereby the resin flow velocity-stabilization, be not easy to take place lead stream or space.
Semiconductor device of the present invention, the 1st apex of resin-sealed portion has the resin inlet, comprise inflow adjustment district with described resin inlet and the fill area that contains described semiconductor element, also has the slot part that described inflow adjustment district and described fill area are separated, described slot part is parallel with described circuit board circumference, spreads all on the whole width of described fill area and all has this slot part.
Semiconductor device of the present invention, the profile of resin-sealed portion forms hexagon, the 1st apex of described sealing resin section and be positioned at described prostatitis with being bar and described rank rear with being on the axis of bar with opposed the 2nd summit, described the 1st summit, described the 1st apex has the resin inlet, described the 2nd apex has pore, and comprise inflow adjustment district with described resin inlet, the fill area that contains described semiconductor element, and the district that releases with described pore, also has the slot part that described inflow adjustment district and described fill area are separated, described slot part is parallel with described circuit board circumference, spread all on the whole width of described fill area and all have this slot part, have again described fill area and described the 2nd slot part of releasing and separating out, described the 2nd slot part is parallel with described circuit board circumference, spreads all on the whole width of described fill area and all has this slot part.
Semiconductor device of the present invention, have the linearity runner of circuit board circumference to the described resin-sealed portion of the described subregion portion of prostatitis and rank rear, short prostatitis connects described outside connecting portion and described prostatitis with being bar with runner, the rank rear of the length corresponding with described notch with runner only at described middle interconnecting piece and described rank rear with being that bar engages with described semiconductor mount circuit board.
Manufacturing method of semiconductor module of the present invention, in described prostatitis usefulness is that bar and described rank rear usefulness are the electroplating region of bar configuration from the extremely described subregion of described outside connecting portion portion, semiconductor element is loaded in mounting semiconductor district in described subregion portion, use forms the sealing metal mould of linearity runner behind resin-sealed of the described semiconductor element of described subregion portion's formation sealing at described electroplating region, cut off described runner from described subregion portion and described sealing resin section, and cut off described subregion portion from described semiconductor mount circuit board.
Manufacturing method of semiconductor module of the present invention, at the sealing metal mould prostatitis subregion group that a pair of described semiconductor mount circuit board is configured to both sides is parallel to the inboard, to be arranged on the bipartite a plurality of pod shape filling pieces of the described semiconductor mount circuit board shape that uniformly-spaced is arranged in a straight line, form pod shape filling piece group, and make a pair of described pod shape filling piece flock mating be set to parallel, and the arrangement pitch of both sides' described pod shape filling piece half spacing that staggers mutually, described pod shape filling piece is configured to staggered palisade;
The described subregion portion in the described subregion portion of the 1st pod shape filling piece group's described pod shape filling piece, the rank rear of the 1st described semiconductor mount circuit board and the prostatitis of the 2nd described semiconductor mount circuit board is configured on the straight line, forms the equidistant runner of runner from described pod shape filling piece to the described resin-sealed portion that the described subregion both sides of portion form;
The described subregion portion in the described subregion portion of the 2nd pod shape filling piece group's described pod shape filling piece, the rank rear of the 2nd described semiconductor mount circuit board and the prostatitis of the 1st described semiconductor mount circuit board is configured on the straight line, forms the equidistant runner of runner from described pod shape filling piece to the described resin-sealed portion that the described subregion both sides of portion form.
In sum, according to the present invention, then can provide the geat cuttability is good, prevent space and suitable many arrays BGA assembly and wiring circuit thereof.
Moreover though the present invention all points out the component units of straight line, as long as in the scope that obtains as effect of the present invention, each component units may not be straight line.By the unit of part employing curve, can seek relieve stresses and improve resin flow.
Description of drawings
Figure 1A illustrates the embodiment of the invention 1, is the figure of sealing state that the BGA assembly of semiconductor mount circuit board is shown.
Figure 1B is the figure that the state of the BGA assembly after the singualtion is shown.
Fig. 2 A～Fig. 2 E is the figure of manufacturing process that the BGA assembly of this embodiment is shown.
Fig. 3 is the figure of sealing state that the BGA assembly of the embodiment of the invention 2 is shown.
Fig. 4 is the figure of sealing state that the BGA assembly of the embodiment of the invention 3 is shown.
Fig. 5 is the figure of sealing state that the BGA assembly of the embodiment of the invention 4 is shown.
Fig. 6 is the figure of sealing state that the BGA assembly of the embodiment of the invention 5 is shown.
Fig. 7 is the figure of sealing state that the BGA assembly of the embodiment of the invention 6 is shown.
Fig. 8 A illustrates the embodiment of the invention 7, is the figure of sealing state that the BGA assembly of semiconductor mount circuit board is shown.
Fig. 8 B is the A-A cutaway view that Fig. 8 A is shown.
Fig. 9 A illustrates the embodiment of the invention 8, is the figure of sealing state that the BGA assembly of semiconductor mount circuit board is shown.
Fig. 9 B is the A-A cutaway view that Fig. 9 A is shown.
Figure 10 A is the figure of sealing state of BGA assembly that the semiconductor mount circuit board of the embodiment of the invention 9 is shown.
Figure 10 B is the figure that the state of the BGA assembly after the singualtion is shown.
Figure 11 is the A-A cutaway view that Figure 10 A is shown.
Figure 12 A～Figure 12 C is the figure of manufacturing process that the BGA assembly of this embodiment is shown.
Figure 13 A～Figure 13 B is the figure of manufacturing process that the BGA assembly of this embodiment is shown.
Figure 14 is the figure of sealing state that the BGA assembly of the embodiment of the invention 10 is shown.
Figure 15 is the figure of sealing state that the BGA assembly of the embodiment of the invention 11 is shown.
Figure 16 is the figure of sealing state that the BGA assembly of the embodiment of the invention 12 is shown.
Figure 17 is the figure of sealing state that the BGA assembly of the embodiment of the invention 13 is shown.
Figure 18 is the figure of sealing state that the BGA assembly of the embodiment of the invention 14 is shown.
Figure 19 is the figure of sealing state that the BGA assembly of the embodiment of the invention 15 is shown.
Figure 20 is the figure of sealing state that the BGA assembly of the embodiment of the invention 16 is shown.
Figure 21 A illustrates the existing example of forming, and is the figure that the BGA assembly sealing state of circuit board is shown.
Figure 21 B is the figure that the state of the BGA assembly after the singualtion is shown.
Embodiment
Below, with reference to the embodiment of description of drawings semiconductor device of the present invention.The present invention and in lead frame type assembly, can both bring into play effective efficiency not only in the circuit board type assembly, but following execution mode describes the circuit board type assembly that can present its function.
Embodiment 1
Figure 1A illustrates the sealing state of the BGA assembly of the embodiment of the invention 1, and Figure 1B illustrates the BGA assembly after the division.Fig. 2 A to Fig. 2 E illustrates the manufacturing process of the BGA assembly of the semiconductor mount circuit board that uses the embodiment of the invention 1.
Among Fig. 1, Fig. 2 A to Fig. 2 E, S represents semiconductor mount circuit board, 1 expression frame portion (connecting portion), the subregion portion (dividing the zone of each assembly respectively) in 2 expression prostatitis, 3 expression prostatitis are with being bar, the runner in 4 expression prostatitis, the subregion portion (zone that is divided into each assembly respectively) of 5 expression rank rears, 6 expression rank rears are with being bar, 7 expression rank rear runners, 8 expression peristomes, 9 expression dowel holes, the BGA packaging part after 10 expressions are divided, 11 expression chips (semiconductor element), 12 expression leads, the resin-sealed portion of 13 expressions, 14 expression geats (resin inlet).
Shown in Figure 1A, the profile of semiconductor mount circuit board S forms rectangle, and its zone be by uniformly-spaced will forming foursquare each subregion portion 2,5 shape that is arranged in a straight line, formation subregion group, and be arranged in the subregion group of prostatitis and rank rear parallel.And, with the arrangement pitch of prostatitis subregion group and rank rear subregion group's subregion portion 2,5 half spacing that staggers mutually, subregion portion 2,5 is arranged in staggered palisade.
Each subregion portion 2,5 has mounting semiconductor district, internal terminal and outside terminal, and the frame portion 1 that forms the periphery connecting portion is configured to surround the 1st subregion group and the 2nd subregion group.
In prostatitis subregion group's subregion portion 2 each other, configuration connects the rank rear of rank rear subregion group's each subregion portion 5 and frame portion 1 with being bar 6.In rank rear subregion group's subregion portion 5 each other, configuration connects the prostatitis of prostatitis subregion group's each subregion portion 2 and frame portion 1 with being bar 3.
Prostatitis usefulness is that bar 3 and rank rear usefulness are that bar 6 disposes the electroplating region (omitting the figure) from frame portion 1 to each subregion portion 2,5 respectively, and the electroplating region linearity arrives each subregion portion 2,5, and is crooked midway in the path.Utilize peristome 8, with prostatitis subregion group's subregion portion 2 and rank rear subregion group's rank rear be between the bar 6 and prostatitis subregion group's prostatitis be bar 3 with rank rear subregion group's subregion portion 5 between separate.And each limit of periphery of subregion portion 2,5 is parallel to each limit of circuit board periphery of the frame portion 1 of semiconductor mount circuit board S, and each limit of resin-sealed 13 profile is parallel with each limit of periphery of subregion portion 2,5.
With following operation, make the BGA assembly that uses this semiconductor mount circuit board S.At first, the wiring circuit S shown in Figure 1A is bonded to chip 11 the subregion portion 2 in prostatitis and the subregion portion 5 of rank rear like that respectively shown in Fig. 2 B.
Secondly, shown in Fig. 2 C, respectively the electrode of chip 11 with each subregion portion 2,5 is connected with lead 12.Then, shown in Fig. 2 D, form resin-sealed 13 with sealing resin.This formation of resin-sealed 13 is carried out with the sealing metal mould.It is that bar 3, rank rear usefulness are the corresponding linearity flow passage route of electroplating region of bar 6 that sealing metal mould has with prostatitis usefulness.
Then, shown in Fig. 2 E, utilize and cut off geat, remove the runner 4,7 of prostatitis and rank rear from frame portion 1.
In above-mentioned operation, on the wiring circuit S of embodiment 1, composition as its feature, the subregion portion 2 in prostatitis and the subregion portion 5 of rank rear are with its arrangement pitch half spacing that staggers mutually, be in staggered palisade, the configuration rank rear is with being bar 6 between the subregion portion 2 in prostatitis, and the configuration prostatitis and disposes geat 14 at the middle position on profile one side of resin-sealed 13 with being bar 3 between the subregion portion 5 of rank rear.
According to the composition of above-mentioned feature, can make by the prostatitis be bar 3 and rank rear with being the prostatitis runner 4 of bar 6 and the central authorities of resin-sealed (the injection moulding portion) 13 that rank rear runner 7 linearities arrive each subregion portion 2,5, crooked midway in the path not.Therefore, sealing resin can be injected into resin-sealed 13 swimmingly.
When cutting off geat 14, promptly, at geat 14 with runner 4,7 bendings, when making runner break away from sealing resin section, to the moment loading around the axis of the orthogonal axe of runner 4,7 in runner 4,7.
At this moment, the prostatitis be bar 3 and rank rear be the runner 4,7 that forms on the bar 6 toward with the direction straight-line extension of the outer peripheral edges quadrature of the side of semiconductor mount circuit board S, and engage with resin-sealed 13.And runner 4,7 and resin-sealed 13 boundary face are extended toward the direction (promptly parallel with circuit board outer peripheral edges direction) to the orthogonal axe of runner 4,7.The stress equalization that produces when therefore, cutting off geat acts on runner 4,7 and resin-sealed 's 13 the boundary face direction with runner 4,7 quadratures.
This effect derives from feature of the present invention and forms.Promptly, profile forms among the semiconductor mount circuit board S of rectangle, the subregion group of prostatitis and rank rear forms parallel, and each subregion portion 2,5 is arranged in staggered palisade, is that the prostatitis that forms each other of the subregion portion 5 of bar 6 and rank rear is with being bar 3 thereby form rank rear usefulness that the subregion portion 2 in prostatitis forms each other along the direction to the circuit board circumference quadrature of semiconductor mount circuit board S.
Therefore, can suppressing portion runner 4,7 residue in geat 14, and can suppress resin-sealed 13 generation breach or resin-sealed 13 and peel off from subregion portion 2,5.After cutting off geat, cut away subregion portion 2,5 and resin-sealed 13 each assembly of forming from frame portion 1, thereby form BGA assembly 10.
Embodiment 2
Fig. 3 illustrates the embodiment of the invention 2, is the figure that the sealing state of semiconductor mount circuit board BGA assembly is shown.Among Fig. 3, semiconductor mount circuit board S identical with shown in Fig. 2 A forms the circuit board circumference of frame portion 1 each limit of periphery of subregion portion 2,5 parallel.Chip 11 is loaded in mounting semiconductor district in subregion portion 2,5, and forms resin-sealed 13 that seals chip 11 in each subregion portion 2,5.
Each limit of resin-sealed 13 profile is to each limit of the periphery of subregion portion 2,5 45 degree that tilt, and geat 14 is positioned at the central authorities on one side of the periphery of subregion portion 2,5, also on a summit of resin-sealed 13 geat 14 is set simultaneously.
According to above-mentioned composition, identical with embodiment 1, when cutting off geat, runner 4,7 broke away from subregion portions 2,5 and resin-sealed at 13 o'clock, and the stress equalization acts on runner 4,7 and resin-sealed 's 13 the boundary portion direction with runner 4,7 quadratures.
Therefore, can guarantee that the geat cuttability is good.That is to say, can suppressing portion runner 4,7 residue in geat 14, and can suppress resin-sealed 13 generation breach or resin-sealed 13 and peel off from subregion portion 2,5.
And, form as feature, each limit of resin-sealed 13 is to each limit of subregion portion 2,5 45 degree that tilt, and geat 14 is positioned at a summit of resin-sealed 13, and 2 limits of resin-sealed 13 are connected geat 14 in the mode of the angle that keeps spending with the axis 45 of runner 4,7.
2 limits of this resin-sealed 13 this are when resin-sealed, and the guiding sealing resin makes resin-sealed 13 corner be not easy to take place the space, sealing resin can be injected into resin-sealed 13 swimmingly.
Again, flow channel shape can form linearity always before geat 14.Therefore, compare, needn't widen the electroplating region corresponding, can effectively use the wiring region of subregion portion 2,5 with runner 4,7 with the method for widening runner 4,7 before the geat.
Embodiment 3
Fig. 4 illustrates the embodiment of the invention 3, is the figure of sealing state that the BGA assembly of semiconductor mount circuit board S is shown.Among Fig. 4, semiconductor mount circuit board S is identical with shown in Fig. 2 A basically, and difference is the aspect of setting forth below.
That is, subregion portion 4,5 forms the shapes of each limit of its periphery to circuit board circumference inclination 45 degree of frame portion 1.Identical with the embodiment of front, chip 11 loads in each subregion portion 2,5 in the mounting semiconductor district, and forms resin-sealed 13 that chip 11 is sealed.
Each limit of resin-sealed 13 profile, to frame portion 1 inclination, 45 degree, also parallel simultaneously with each limit of periphery of subregion portion 2,5.Geat 14 is positioned at an apex of subregion portion 2,5, also is arranged on an apex of resin-sealed 13 simultaneously.
According to above-mentioned composition, identical with embodiment 1, when cutting off geat, runner 4,7 broke away from subregion portions 2,5 and resin-sealed at 13 o'clock, and the stress equalization acts on runner 4,7 and resin-sealed 's 13 the boundary portion direction with runner 4,7 quadratures.
Therefore, can guarantee that the geat cuttability is good.That is to say, can suppressing portion runner 4,7 residue in geat 14, and can suppress resin-sealed 13 generation breach or resin-sealed 13 and peel off from subregion portion 2,5.
And, forming as feature, subregion portion 4,5 forms the shapes of each limit of its periphery to circuit board circumference inclination 45 degree of frame portion 1; Each limit of resin-sealed 13 profile is to frame portion 1 inclination, 45 degree, and is also parallel with each limit of periphery of subregion portion 2,5 simultaneously; Geat 14 is positioned at an apex of subregion portion 2,5, also is arranged on an apex of resin-sealed 13 simultaneously.
Therefore, identical with embodiment 2,2 limits of resin-sealed 13 guide sealing resin when resin-sealed, make resin-sealed 13 corner be not easy to take place the space, sealing resin can be injected into resin-sealed 13 swimmingly.
Again, flow channel shape can form linearity always before geat 14.Therefore, compare, needn't widen the electroplating region corresponding, can effectively use the wiring region of subregion portion 2,5 with runner 4,7 with the method for widening runner 4,7 before the geat.And resin-sealed 13 profile can be increased to the limit, zone of subregion portion 2,5 always.
In the present embodiment, dowel hole 9 is configured in than the frame portion 1 of the periphery that is configured in prostatitis subregion group and rank rear subregion group in the inner part and the remaining space between each subregion portion 2,5, thereby makes frame portion 1 minimum, can effectively utilize the space of circuit board.
Embodiment 4
Fig. 5 illustrates the embodiment of the invention 4, is the figure that the sealing state of semiconductor mount circuit board BGA assembly is shown.Among Fig. 5, semiconductor mount circuit board S identical with shown in Fig. 2 A forms parallel to each limit of periphery of subregion portion 2,5 and the circuit board circumference of frame portion 1.Load chip 11 in the mounting semiconductor district, and form resin-sealed 13 that seals chip 11 in each subregion portion 2,5.Resin-sealed 13 profile that forms octagon.Geat 14 is positioned at the central authorities on one side of the periphery of subregion portion 2,5, also is arranged on resin-sealed 13 profile central authorities on one side simultaneously.
According to above-mentioned composition, identical with embodiment 1, can guarantee good geat cuttability.And, by resin-sealed 13 formation octagon, when making sealing resin, 2 limits of resin-sealed 13 guide sealing resin near geat 4, be not easy to produce the space, sealing resin can be injected into resin-sealed 13 swimmingly resin-sealed 13 corner.
Again, by making resin-sealed 13 for octagon, each limit that can optimize resin-sealed 13 scale and each subregion portion 2,5 to subregion portion 2,5 has nothing to do with the angle of the circuit board circumference of frame portion 1.
And, since this shape of resin-sealed 13 from the distance of central authorities to the end of subregion portion 2,5 at whole periphery constant, the Zone Full equalization of sealing is applied forming pressure, be not easy to produce the space.
Embodiment 5
Fig. 6 illustrates the embodiment of the invention 5, is the figure of sealing state that the BGA assembly of semiconductor mount circuit board S is shown.Among Fig. 6, semiconductor mount circuit board S is identical with shown in Fig. 2 A basically, and difference is the aspect of setting forth below.
That is, subregion portion 2,5 forms the shapes of each limit of its periphery to circuit board circumference inclination 45 degree of frame portion 1.Identical with the embodiment of front, chip 11 loads in each subregion portion 2,5 in the mounting semiconductor district, and forms resin-sealed 13 that chip 11 is sealed.
Resin-sealed 13 profile that forms octagon.4 limits of resin-sealed 13 profile are parallel with each limit of periphery of subregion portion 2,5.Geat 14 is positioned at the central authorities on one side of the periphery of subregion portion 2,5, also is arranged on resin-sealed 13 profile central authorities on one side simultaneously.
According to above-mentioned composition, identical with embodiment 1, can guarantee good geat cuttability.And, by resin-sealed 13 formation octagon, when making sealing resin, 2 limits of resin-sealed 13 guide sealing resin near geat 4, be not easy to produce the space, sealing resin can be injected into resin-sealed 13 swimmingly resin-sealed 13 corner.
Again, identical by making resin-sealed 13 for octagon with embodiment 4, can make resin-sealed 13 largest with respect to subregion portion 2,5.And, since this shape of resin-sealed 13 from the distance of central authorities to the end of subregion portion 2,5 at whole periphery constant, the Zone Full equalization of sealing is applied forming pressure, be not easy to produce the space.
Embodiment 6
Fig. 7 illustrates the embodiment of the invention 6, is the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Fig. 7, semiconductor mount circuit board S identical with shown in Fig. 2 A forms each limit of periphery of subregion portion 2,5 to such an extent that form parallel to the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.
Form pentagonal profile for resin-sealed 13, the geat 14 when sealing resin is injected in the configuration of the 1st apex.Opposed with the 1st apex, and the 1st limit a parallel with the circuit board circumference of frame portion 1 formation pore (omitting among the figure), the 1st limit a and the 2nd limit b and the 3rd limit c intersect vertically, and are configured to parallel with the 3rd limit c the 2nd limit b.
According to above-mentioned composition, identical with embodiment 1, can guarantee good geat cuttability.And the sealing resin that injects from geat 14 is resin-sealed 13 inside, and its path does not narrow down, and can inject swimmingly, again because 2 limits of resin-sealed 13 guide sealing resin geat 4 near, is not easy the generation space, corner at resin-sealed 13.In resin-sealed 13, sealing resin is easy to move toward pore (omitting among the figure), thus the resin flow speed stability, and be convenient to control flow velocity, can make the generation of space or lead stream minimum.
Again, runner forms and can forms linearity always before geat 14, compares with the method for widening runner 4,7 before the geat, needn't widen the electroplating region corresponding with runner 4,7, can effectively use the wiring region of subregion portion 2,5.
Embodiment 7
Fig. 8 A, Fig. 8 B illustrate the embodiment of the invention 7, are the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Fig. 8 A, Fig. 8 B, semiconductor mount circuit board S identical with shown in Fig. 2 A.Each limit of periphery of subregion portion 2,5 is parallel to the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.
Pass through slot part 13c for resin-sealed 13, divide inflow adjustment district 13a with geat (resin inlet) 14 and the fill area 13b that contains chip 11.This slot part 13c is parallel with the outer peripheral edges portion of the frame portion 1 of semiconductor mount circuit board S, spreads all on the whole width of fill area 13b and all has this slot part.
Flow into to adjust district 13a and form triangular shape, and be that the 1st apex (drift angle) on the axis of bar 3,6 forms geat 14 being positioned at.Fill area 13b forms quadrangle, and 4th limit d that with slot part 13c dock opposed with the 1st summit forms parallel with the outer peripheral edges portion of frame portion 1, and is forming the 1st limit a formation pore (in figure omit) parallel with the 4th limit d.Form parallel with the 2nd limit b that the 1st limit a and the 4th limit d intersect vertically with the 3rd limit c.
According to above-mentioned composition, on resin-sealed 13 the interior location corresponding with slot part 13c, the path narrows down, and forms restriction 13d.The sealing resin that injects from geat 14 flow into adjust that district 13a is temporary transient and stop after, flow into fill area 13b from restriction 13d.At this moment, sealing resin spreads all on the whole width of restriction 13d and disperses, and flow into fill area 13b with even flow, and towards pore (omitting among the figure).
Thereby, identical in the present embodiment with embodiment 1, can guarantee good geat cuttability.And, restriction 13d is set, make the resin flow velocity among the fill area 13b even, thereby can make the generation of the generation in space or lead stream minimum.
Embodiment 8
Fig. 9 A, Fig. 9 B illustrate the embodiment of the invention 8, are the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Fig. 9 A, Fig. 9 B, semiconductor mount circuit board S identical with shown in Fig. 2 A.Each limit of periphery of subregion portion 2,5 is parallel to the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.
Resin-sealed 13, its profile forms hexagon, divides inflow adjustment district 13a with geat 14 and the fill area 13b that contains chip 11 by slot part 13c, and divides fill area 13b and the district 13e that releases with pore (omitting among the figure) by slot part 13f.
This slot part 13c and slot part 13f form parallelly with the outer peripheral edges portion of the frame portion 1 of semiconductor mount circuit board S, and spread all on the whole width of fill area 13b and all have this slot part.
The district 13e that releases that has the inflow adjustment district 13a on the 1st summit and have the 2nd summit forms triangular shape, and the 1st apex and the 2nd apex are bar 3 and are on the axis of bar 6 being positioned at.Flow into the 1st apex of adjusting district 13a and have geat 14, the 2nd apex of the district 13e that releases has pore (omitting among the figure).
Fill area 13b forms quadrangle, and the 4th limit d is opposed with the 1st summit that flows into adjustment district 13a, also dock with slot part 13c simultaneously, and formation is parallel with the outer peripheral edges portion of frame portion 1.Form parallel with the 1st limit a of the 2nd slot part 13f butt joint with the 4th limit d.Form parallel with the 2nd limit b that the 1st limit a and the 4th limit d intersect vertically with the 3rd limit c.
According to above-mentioned composition, on resin-sealed 13 the interior location corresponding with slot part 13c, the path narrows down, and forms restriction 13d.The sealing resin that injects from geat 14 flow into adjust that district 13a is temporary transient and stop after, flow into fill area 13b from restriction 13d.At this moment, the whole width that sealing resin spreads all over restriction 13d disperses, and flow into fill area 13b with even flow, and towards the district 13e that releases.
On resin-sealed 13 the interior location corresponding with slot part 13f, the path narrows down, and forms the 2nd restriction 13g.The air of fill area 13b flows out to the district 13e that releases from the 2nd restriction 13g.At this moment, sealing resin spreads all on the whole width of the 2nd restriction 13g and disperses, and flows out to the district 13e that releases with even flow, and towards pore (omitting among the figure).
Thereby, identical in the present embodiment with embodiment 1, can guarantee good geat cuttability.And, restriction 13d is set, make the resin flow velocity among the fill area 13b even, thereby can make the generation of the generation in space or lead stream minimum.Again, can guarantee simultaneously that even air flows out among the fill area 13b, one side can seek to reduce forming the required expense of a plurality of pores finally at a pore air-out in the past.
Embodiment 9
Figure 10 A illustrates the sealing state of the BGA assembly of the embodiment of the invention 9, and Figure 10 B illustrates the BGA assembly after the division.Figure 11 illustrates resin-sealed operation, and Figure 12 A～Figure 12 C and Figure 13 A～Figure 13 B illustrate the manufacturing process of the BGA assembly of the wiring circuit that uses present embodiment.
Shown in Figure 10 A, Figure 10 B, semiconductor mount circuit board S, its profile forms rectangle, and its zone be by uniformly-spaced will forming foursquare each subregion portion 2,5 shape that is arranged in a straight line, formation subregion group, and be arranged in the subregion group of prostatitis and rank rear parallel.And, with the arrangement pitch of prostatitis subregion group and rank rear subregion group's subregion portion 2,5 half spacing that staggers mutually, subregion portion 2,5 is arranged in staggered palisade.
Each limit of periphery of subregion portion 2,5 is parallel to the circuit board circumference of the frame portion 1 of semiconductor mount circuit board S.Each subregion portion 2,5 has mounting semiconductor district, internal terminal and outside terminal, the frame portion 1 of semiconductor mount circuit board S comprises outside connecting portion 1a and middle interconnecting piece 1b, outside connecting portion 1a is configured in its periphery, surround the subregion group in prostatitis and the subregion group of rank rear, and middle interconnecting piece 1b is configured between prostatitis subregion group and the rank rear subregion group.
Around each subregion portion 2,5, form peristome 8, utilize peristome 8 to make between each subregion portion 2,5 and the wiring circuit S and separate.Between outside connecting portion 1a and each the subregion portion 2,5 and between middle interconnecting piece 1b and each the subregion portion 2,5, form the prostatitis with being that bar 3 and rank rear are with being bar 6.Respectively be to dispose electroplating region (omitting among the figure) in the bar 3,6.
Semiconductor mount circuit board S forms notch 21 between prostatitis subregion group's subregion portion 5, notch 21 arrives middle interconnecting piece 1b from the circuit board circumference of a side.It is that bar 6 is positioned on the axis of notch 21 that rank rear is used.
With following operation, make the BGA assembly that uses this semiconductor mount circuit board S.At first, the wiring circuit S shown in Figure 12 A is bonded to chip 11 the subregion portion 2 in prostatitis and the subregion portion 5 of rank rear like that respectively shown in Figure 12 B.
Secondly, shown in Figure 12 C, respectively the electrode of chip 11 with each subregion portion 2,5 is connected with lead 12.
Then, as shown in FIG. 13A, form resin-sealed 13 with sealing resin.This formation of resin-sealed 13 is carried out with sealing metal mould 22, as shown in figure 11.Sealing metal mould 22 have with the prostatitis with being bar 3 and rank rear with the path that is the corresponding linearity runner 4,7 of bar 6.
Then, shown in Figure 13 B, utilize and cut off geat, remove runner 4,7 from frame portion 1 and subregion portion 2,5.
In above-mentioned operation, on the semiconductor mount circuit board S of present embodiment, the runner 4 in prostatitis and the runner 7 of rank rear, extend toward direction linearity from the circuit board outer peripheral edges of the side of semiconductor mount circuit board S with its quadrature, and be connected to the central authorities of the sealing resin section 13 of each subregion portion 2,5, crooked in the path not midway.
This situation derives from the feature of semiconductor mount circuit board S and forms.Promptly, the subregion portion 2 in prostatitis and the subregion portion 5 of rank rear are with its arrangement pitch half spacing that staggers mutually, be arranged in staggered palisade, and the configuration rank rear is with being bar 6 between the subregion portion 2 in prostatitis, the configuration prostatitis is with being bar 3, the central configuration geat 14 resin-sealed 13 neighboring between the subregion portion 5 of rank rear.
And the runner 4 in prostatitis and the runner 7 of rank rear extend the direction (promptly parallel with circuit board outer peripheral edges direction) of the orthogonal axe of runner 4,7 with resin-sealed 13 boundary face edge.
So, when cutting off geat, promptly cutting away runner at 4,7 o'clock from the assembly that comprises subregion portion 2,5 and resin-sealed 13, stress is orthogonal to the directive effect equalization of runner 4,7 on runner 4,7 and resin-sealed 's 13 boundary face.
Therefore, can suppressing portion runner 4,7 remain in geat 14, and suppress to produce for resin-sealed 13 breach or resin-sealed 13 and produce and peel off, can guarantee good geat cuttability.
Again, the runner 7 of rank rear is formed at the position of the notch 21 of semiconductor mount circuit board S to the long runner distance of major part of subregion portion 5.Therefore, the runner 7 of rank rear does not engage with semiconductor mount circuit board S on its most of position, and near the position of geat and rank rear with being that bar 6 and middle interconnecting piece 1b engage.
On the other hand, the runner 4 in prostatitis on the short runner distance of the linearity from the circuit board circumference of semiconductor mount circuit board S to each subregion portion 2 in prostatitis be that bar 3 engages.Therefore, can the short runner 4 in prostatitis be peeled off from semiconductor mount circuit board S with the power identical with the long runner 7 of rank rear.
And, the position of the close geat of the long runner 7 of rank rear be that bar 6 and middle interconnecting piece 1a engage, so the load of long runner 7 does not act directly on the narrow cross section of geat 14.Therefore, can realize guaranteeing the single armed supporting construction of suitable intensity.So, waiting the power of place midway even carry to the non-hope of runner 7 effects, also can prevent to cut off runner 7 because of carelessness, be convenient to handle.After cutting off geat, cut each assembly that comprises subregion portion 2,5 and resin-sealed 13, form BGA assembly 10 from frame portion 1.
Embodiment 10
Figure 14 illustrates the embodiment of the invention 10, is the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Figure 14, semiconductor mount circuit board S identical with shown in Figure 12 A.Subregion portion 2,5 forms each limit of periphery parallel to the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.
Form pentagonal profile, have geat 14 in the 1st apex for resin-sealed 13.Forming pore (omitting among the figure) with opposed the 1st limit a of the 1st apex for resin-sealed 13, and the 1st limit a is parallel with the circuit board circumference of frame portion 1.The 1st limit a and the 2nd limit b and the 3rd limit c intersect vertically, and the 2nd limit b forms parallel with the 3rd limit c.
According to above-mentioned composition, identical with embodiment 9, can guarantee good geat cuttability.And the sealing resin that injects from geat 14 is resin-sealed 13 inside, and its path does not narrow down, and can inject swimmingly, again because 2 limits of resin-sealed 13 guide sealing resin geat 4 near, is not easy the generation space, corner at resin-sealed 13.In resin-sealed 13, sealing resin is easy to move toward pore (omitting among the figure), thus the resin flow speed stability, and be convenient to control flow velocity, can make the generation of space or lead stream minimum.
Again, runner forms and can forms linearity always before geat 14, compares with the method for widening runner 4,7 before the geat, needn't widen the electroplating region corresponding with runner 4,7, can effectively use the wiring region of subregion portion 2,5.
Embodiment 11
Figure 15 illustrates the embodiment of the invention 11, is the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Figure 15, semiconductor mount circuit board S except that a part, identical with shown in Figure 12 A basically.Each limit of periphery of subregion portion 2,5 is parallel with the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.Resin-sealed 13 with shown in Figure 15 identical, omits its explanation.
The feature composition of this embodiment 11 is, forms notch 31 between outside connecting portion 1a and the middle interconnecting piece 1b, and leaves outside connecting portion 1a.
According to above-mentioned composition, the base end side of the long runner 7 of rank rear engages with outside connecting portion 1a, front near the position of geat be that bar 6 and middle interconnecting piece 1b engage.So the load of long runner 7 does not act directly on the stenosed section of geat 14, form the structure of removing notch 31 and supporting the two ends of long runner 7, can realize suitable intensity.Therefore, wait the power of place midway, also can prevent to cut off runner 7 because of carelessness, be convenient to handle the non-hope of runner 7 effects even carry.Other action effect is identical with embodiment 10.
Embodiment 12
Figure 16 illustrates the embodiment of the invention 12, is the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Figure 16, semiconductor mount circuit board S identical with shown in Fig. 8 A.Each limit of periphery of subregion portion 2,5 is parallel with the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.This resin-sealed 13 identical with shown in Fig. 8 A marks identical symbol, omits its explanation.
Between a pair of semiconductor mount circuit board S, arrange a plurality of turn troughs 16 by the outer peripheral edges portion linearity along semiconductor mount circuit board S uniformly-spaced, runner 4,7 extends into linearity from each turn trough 16 to semiconductor mount circuit board S both sides with the runner distance that equates.Turn trough 16 is lined up 2 row shapes, the arrangement pitch of turn troughs 16 of two row half spacing that staggers.
Below, the manufacture method of this BGA assembly is described.In sealing metal mould (omitting among the figure), the prostatitis subregion portion 2 that a pair of semiconductor mount circuit board S is configured to both sides is parallel to the inboard.In the sealing metal mould, arrange by linearity uniformly-spaced and to be arranged on the bipartite a plurality of pod shape filling pieces of semiconductor mount circuit board S (being shown turn trough 16 among Figure 16), form pod shape filling piece group.Pod shape filling piece group a pair of is configured to parallelly it, and the arrangement pitch of both sides' pod shape filling piece half spacing that staggers is configured to staggered palisade.
At this moment, each subregion portion 2 of prostatitis of each the subregion portion 5 of rank rear of each pod shape filling piece of the 1st pod shape filling piece group, the 1st semiconductor mount circuit board S and the 2nd semiconductor mount circuit board S is positioned on the straight line.
In this state, form the equidistant runner 4,7 of resin-sealed 13 runner that each pod shape filling piece forms to semiconductor mount circuit board S both sides' the subregion portion 2,5.
And each subregion portion 2 of prostatitis of each pod shape filling piece of the 2nd pod shape filling piece group, each subregion portion 5 of rank rear of the 2nd semiconductor mount circuit board S and the 1st semiconductor mount circuit board S is positioned on the straight line.In this state, form the equidistant runner 4,7 of resin-sealed 13 runner that each pod shape filling piece forms to semiconductor mount circuit board S both sides' the subregion portion 2,5.
Therefore, even form at semiconductor mount circuit board S under 2 row subregion groups' the situation, during potting resin, resin also equates resin-sealed 13 the time of advent from each pod shape filling piece to different lines.And, can be from a pod shape filling piece simultaneously to a pair of semiconductor mount circuit board S resin-sealed 13 supply resin separately.
Embodiment 13
Figure 17 illustrates the embodiment of the invention 13, is the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Figure 17, semiconductor mount circuit board S identical with shown in Figure 12 A.Each limit of periphery of subregion portion 2,5 is parallel with the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.This resin-sealed 13 identical with shown in Fig. 8 A marks identical symbol, omits its explanation.
Between a pair of semiconductor mount circuit board S, arrange a plurality of turn troughs 16 by outer peripheral edges portion linearity uniformly-spaced along semiconductor mount circuit board S, runner 4,7 extends to each semiconductor mount circuit board S from each turn trough 16.Turn trough 16 is lined up 2 row shapes, half spacing that staggers of the arrangement pitch of turn trough 16 in two row.
Below, the manufacture method of this BGA assembly is described.In sealing metal mould (omitting among the figure), the prostatitis subregion portion 2 that a pair of semiconductor mount circuit board S is configured to both sides is parallel to the inboard.In the sealing metal mould, arrange by linearity uniformly-spaced and to be arranged on the bipartite a plurality of pod shape filling pieces of semiconductor mount circuit board S (being shown turn trough 16 among Figure 17), form pod shape filling piece group.Pod shape filling piece group a pair of is configured to parallelly it, and the arrangement pitch of both sides' pod shape filling piece half spacing that staggers is configured to staggered palisade.
At this moment, each subregion portion 2 of prostatitis of each the subregion portion 5 of rank rear of each pod shape filling piece of the 1st pod shape filling piece group, the 1st semiconductor mount circuit board S and the 2nd semiconductor mount circuit board S is positioned on the straight line.And each subregion portion 2 of prostatitis of each pod shape filling piece of the 2nd pod shape filling piece group, each subregion portion 5 of rank rear of the 2nd semiconductor mount circuit board S and the 1st semiconductor mount circuit board S is positioned on the straight line.
In this state, from resin-sealed 13 of each subregion portion 5 of rank rear of each pod shape filling piece to the 1 semiconductor mount circuit board S of the 1st pod shape filling piece group, linearity ground forms runner 7, and resin-sealed 13 bending ground of each subregion portion 2 of prostatitis of also past the 1st semiconductor mount circuit board S forms runner 4 simultaneously.
In addition, from resin-sealed 13 of each subregion portion 5 of rank rear of each pod shape filling piece to the 2 semiconductor mount circuit board S of the 2nd pod shape filling piece group, linearity ground forms runner 7, and resin-sealed 13 bending ground of each subregion portion 2 of prostatitis of also past the 2nd semiconductor mount circuit board S forms runner 4 simultaneously.
Therefore, even form at semiconductor mount circuit board S under 2 row subregion groups' the situation, during potting resin, resin also equates resin-sealed 13 the time of advent from each pod shape filling piece to different lines.Resin flow velocity difference and runner distance difference in runner 7 that can be by the combination rectilinear form and the runner 4 of curved shape realize this effect.And, can supply with resin to resin-sealed 13 of the different lines of each semiconductor mount circuit board S simultaneously from a pod shape filling piece.
Embodiment 14
Figure 18 illustrates the embodiment of the invention 14, is the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Figure 18, semiconductor mount circuit board S identical with shown in Figure 12 A.Each limit of periphery of subregion portion 2,5 is parallel with the circuit board circumference of frame portion 1.Chip 11 is loaded in the mounting semiconductor district, and each subregion portion 2,5 forms resin-sealed 13 to chip 11 sealings.This resin-sealed 13 identical with shown in Fig. 8 A marks identical symbol, omits its explanation.
Between a pair of semiconductor mount circuit board S, arrange a plurality of turn troughs 16 by outer peripheral edges portion linearity uniformly-spaced along semiconductor mount circuit board S, runner 4,7 extends to each semiconductor mount circuit board S from each turn trough 16.
Below, the manufacture method of this BGA assembly is described.In sealing metal mould (omitting among the figure), the prostatitis subregion portion 2 that a pair of semiconductor mount circuit board S is configured to both sides is parallel to the inboard.In the sealing metal mould, arrange by linearity uniformly-spaced and to be arranged on the bipartite a plurality of pod shape filling pieces of semiconductor mount circuit board S (being shown turn trough 16 among Figure 18), form pod shape filling piece group.
At this moment, each subregion portion 5 of rank rear of each the subregion portion 5 of rank rear of each pod shape filling piece of pod shape filling piece group, the 1st semiconductor mount circuit board S and the 2nd semiconductor mount circuit board S is positioned on the straight line.And each subregion portion 2 of prostatitis of each pod shape filling piece of pod shape filling piece group, each subregion portion 2 of prostatitis of the 1st semiconductor mount circuit board S and the 2nd semiconductor mount circuit board S is positioned on the straight line.
In this state, form from each pod shape filling piece to each subregion portion 5 of semiconductor mount circuit board S both sides rank rear separately resin-sealed 13, the equidistant runner 7 of linearity ground formation runner.Again, to resin-sealed 13 of each subregion portion 2 of semiconductor mount circuit board S both sides prostatitis separately, the shape that runner 4 forms from this pod shape filling piece bending, and be formed centrally point-symmetric shape in this pod shape filling piece being.
Therefore, even form at semiconductor mount circuit board S under 2 row subregion groups' the situation, during potting resin, resin also equates resin-sealed 13 the time of advent from each pod shape filling piece to different lines.Resin flow velocity difference and runner distance difference in runner 7 that can be by the combination rectilinear form and the runner 4 of curved shape realize this effect.And, can supply with resin to resin-sealed 13 of the different lines of a pair of semiconductor mount circuit board S (be 4 positions resin-sealed 13) here simultaneously from a pod shape filling piece, can seek to reduce the quantity of pod shape filling piece.
Embodiment 15
Figure 19 illustrates the embodiment of the invention 15, is the figure that the BGA assembly sealing state of semiconductor mount circuit board S is shown.Among Figure 19, each subregion portion 41 of semiconductor mount circuit board S has mounting semiconductor district, internal terminal and outside terminal.Chip (omitting among the figure) is loaded in the mounting semiconductor district, and each subregion portion 41 forms resin-sealed 13 to chip (omitting among the figure) sealing.
Semiconductor mount circuit board S arranges a plurality of subregion portion 41 by linearity uniformly-spaced, forms the subregion group, and is arranged in a plurality of subregion groups parallel.The frame portion 1 of semiconductor mount circuit board S comprises outside connecting portion 1a and subregion connecting portion 1c.1c is configured in its periphery with the subregion connecting portion, surrounds each subregion group.With the circuit board circumference configuration of outside connecting portion 1a, and connect subregion connecting portion 1c along a side.
Semiconductor mount circuit board S forms notch 42 between each subregion faciation is mutual.Form notch 42 along the orientation of subregion portion 41, make it from arriving outside connecting portion 1a, and leave frame portion 1 at the sidepiece of semiconductor mount circuit board S with the opposed opposite side circuit board of outside connecting portion 1a circumference.
Around each subregion portion 41, form peristome 8, and be bar 43 forming what is connected subregion connecting portion 1c and each subregion portion 41 with the direction of the orthogonal axe of notch 42.
According to above-mentioned composition, during sealing resin, form long sprue 44 on the position corresponding with notch 42.And, can linearities arrive resin-sealed 13 central authorities of each subregion portion 41 from the short secondary channels 45 of long sprue 44 branches.Short secondary channels 45 may not need only linearity and join each resin-sealed 13 to the angle at right angle from long sprue 44 branches.
Short secondary channels 45 is extended the direction (promptly parallel with circuit board circumference direction) of the orthogonal axe of secondary channels 45 with resin-sealed 13 boundary face edge.
When cutting off geat, promptly when the assembly that comprises subregion portion 41 and resin-sealed 13 cuts away sprue 44 and secondary channels 45, wiring circuit S is lifted long sprue 44.At this moment, in the secondary channels 45, moment is working with around the axis of its orthogonal axe, and the stress equalization acts on runner 45 and resin-sealed 's 13 the boundary face direction with the orthogonal axe of secondary channels 45.
Therefore, can suppress the short secondary channels 45 of part and remain in geat 14, and can suppress resin-sealed 13 generation breach or resin-sealed 13 generation peeled off.
It is last at notch 42 disengaging semiconductor mount circuit board S that long sprue 44 spreads all over its whole runner distance, and short secondary channels 45 only engages subregion connecting portion 1c and is bar 43.Therefore, be configured to identical power short secondary channels 45 to be peeled off from semiconductor mount circuit board S in the whole subregion portion 41 of palisade.
The integral body of long sprue 44 breaks away from semiconductor mount circuit board S at notch 42, but by each short secondary channels 45 and subregion connecting portion 1c be that bar 43 engages, the load of long sprue 44 does not directly act on the narrow cross section of geat 14, can realize suitable intensity.
Therefore,, also can prevent to cut off runner 44,45 because of carelessness, be convenient to handle even carry medium being in way to act on undesirable power on the runner 44,45.
Embodiment 16
Figure 20 illustrates the embodiment of the invention 16, is the figure that the BGA assembly sealing state of wiring circuit S is shown.Among Figure 20, semiconductor mount circuit board S is except that a part, with shown in Figure 19 substantially the same.
During the feature of present embodiment was formed, semiconductor mount circuit board S connected the both sides of each subregion connecting portion 1c along the outside connecting portion 1a of the circuit board circumference configuration block portion 1 of both sides at both sides' outside connecting portion 1a.
Semiconductor mount circuit board S forms notch 51 between each subregion faciation is mutual.Orientation along subregion portion 13 forms notch 51, makes it arrive the opposing party's outside connecting portion 1c from a side outside connecting portion 1c, and leaves the frame portion 1 of the both sides of semiconductor mount circuit board S.
According to above-mentioned composition, long sprue 44 is removed notch 51 and cardinal extremity is engaged with frame portion 1, and supported by a plurality of short secondary channels 45.So the load of long sprue 44 does not directly act on the narrow cross section of geat 14, can realize suitable intensity.
Therefore,, also can prevent to cut off runner 44,45 because of carelessness, be convenient to handle even carry medium being in way to act on undesirable power on the runner 44,45.Other action effect is identical with embodiment 15.
Scope, the effective range utilized of the present invention, not only effective in above-mentioned whole execution modes as the BGA assembly, and as the assembly that for example subregion portion 2,5 is formed lead frame and so on or mentioned above beyond various semiconductor subassemblies or resin sealing body, all effective to multiple use.

Claims (27)

1, a kind of semiconductor mount circuit board is characterized in that,
It is a kind of wiring circuit, this wiring circuit is arranged a plurality of subregion portion with linearity uniformly-spaced, form the subregion group, and a pair of described subregion group is arranged in parallel, and along circuit board circumference configuration outside connecting portion, surround the subregion group in prostatitis and the subregion group of rank rear, described subregion portion has mounting semiconductor district, internal terminal and outside terminal
With the arrangement pitch of prostatitis subregion group and rank rear subregion group's described subregion portion half spacing that staggers mutually, make described subregion portion be arranged in staggered palisade, the rank rear that described subregion portion in the prostatitis disposes the described subregion portion that connects rank rear and described outside connecting portion each other is with being bar, disposes the prostatitis of the described subregion portion in connection prostatitis and described outside connecting portion each other with being bar in the described subregion portion of rank rear.
2, the semiconductor mount circuit board described in claim 1 is characterized in that,
Utilize peristome, with the described subregion portion in prostatitis and described rank rear be between the bar and the described subregion portion of rank rear and described prostatitis with being to separate between the bar.
3, the semiconductor mount circuit board described in claim 1 is characterized in that,
Be the wiring circuit that profile forms rectangle, and each limit of periphery of described subregion portion is parallel with described circuit board circumference.
4, the semiconductor mount circuit board described in claim 1 is characterized in that,
They be the wiring circuit that profile forms rectangle, and each limit of the periphery of described subregion portion is to described circuit board central portion 45 degree that tilt.
5, as each described semiconductor mount circuit board in the claim 1 to 4, it is characterized in that,
The described subregion portion of prostatitis and rank rear is formed lead frame.
6, the semiconductor mount circuit board described in claim 1 is characterized in that,
Between the subregion group of the subregion group in prostatitis and rank rear, dispose middle interconnecting piece, around described subregion portion, form peristome, also forming described prostatitis between described outside connecting portion and the described subregion portion and between described middle interconnecting piece and the described subregion portion with being that bar and described rank rear are with being bar simultaneously, the described subregion portion in prostatitis forms the notch from the circuit board circumference of a side to described middle interconnecting piece each other, and the described rank rear that connects the described subregion portion of rank rear and described middle interconnecting piece is with being that bar is positioned on the axis of described notch.
7, the semiconductor mount circuit board described in claim 1 is characterized in that,
Between the subregion group of the subregion group in prostatitis and rank rear, dispose middle interconnecting piece, around described subregion portion, form peristome, also forming described prostatitis between described outside connecting portion and the described subregion portion and between described middle interconnecting piece and the described subregion portion with being that bar and described rank rear are with being bar simultaneously, the described subregion portion in prostatitis forms the notch from described outside connecting portion to described middle interconnecting piece each other, and the described rank rear that connects the described subregion portion of rank rear and described middle interconnecting piece is with being that bar is positioned on the axis of described notch.
8, a kind of semiconductor mount circuit board is characterized in that,
It is a kind of wiring circuit, this wiring circuit is arranged a plurality of subregion portion with linearity uniformly-spaced, form the subregion group, and a pair of described subregion group is arranged in parallel, and at periphery configure partition connecting portion, surround each subregion group, described subregion portion has mounting semiconductor district, internal terminal and outside terminal
The outside connecting portion that connects each subregion group along the circuit board circumference configuration of a side, described subregion faciation forms and the circuit board circumference of the opposed opposite side of the described outside connecting portion notch to described outside connecting portion along the orientation of described subregion portion between mutually, forming peristome around described subregion portion, is bar forming what be connected described subregion connecting portion and described subregion portion with the direction of the orthogonal axe of described notch part also simultaneously.
9, a kind of semiconductor mount circuit board is characterized in that,
It is a kind of wiring circuit, this wiring circuit is arranged a plurality of subregion portion with linearity uniformly-spaced, form the subregion group, and a pair of described subregion group is arranged in parallel, and at periphery configure partition connecting portion, surround each subregion group, described subregion portion has mounting semiconductor district, internal terminal and outside terminal
The outside connecting portion that connects each subregion group along the circuit board circumference configuration of both sides, orientation along described subregion portion forms the notch of the outside connecting portion of a side to the outside connecting portion of opposite side, forming peristome around described subregion portion, is bar forming what be connected described subregion connecting portion and described subregion portion with the direction of the orthogonal axe of described notch part also simultaneously.
10, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 3, form the resin-sealed portion of the described semiconductor element of sealing in described subregion portion, and each limit of the profile of described sealing resin section is parallel with each limit of the periphery of described subregion portion.
11, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 3, form the resin-sealed portion of the described semiconductor element of sealing in described subregion portion, and each limit of the profile of described sealing resin section is to each limit of the periphery of described subregion portion 45 degree that tilt.
12, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 4, form the resin-sealed portion of the described semiconductor element of sealing in described subregion portion, and each limit of the profile of described sealing resin section is parallel with each limit of the periphery of described subregion portion.
13, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 3, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, the profile of described resin-sealed portion forms octagon, and each limit of the profile of described sealing resin section is to each limit of the periphery of described subregion portion 45 degree or parallel with each limit of the profile of described sealing resin that tilt.
14, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 4, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, the profile of described resin-sealed portion forms octagon, and each limit of the profile of described sealing resin section is to each limit of the periphery of described subregion portion 45 degree or parallel with each limit of the profile of described sealing resin that tilt.
15, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 1, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, the profile of described resin-sealed portion forms pentagon, and the 1st apex of described sealing resin section is positioned at described prostatitis with being bar and described rank rear with being on the axis of bar.
16, the semiconductor device described in claim 15 is characterized in that,
Described resin-sealed portion has the resin inlet in the 1st apex, and forms pore on the 1st opposed with described the 1st apex and parallel with circuit board circumference limit.
17, the semiconductor device described in claim 16 is characterized in that,
The 2nd limit with described the 1st limit intersects vertically of described resin-sealed portion forms parallel with the 3rd limit.
18, the semiconductor device described in claim 15 is characterized in that,
Described resin-sealed portion has the resin inlet in described the 1st apex, comprise inflow adjustment district with described resin inlet and the fill area that contains described semiconductor element, also has the slot part that described inflow adjustment district and described fill area are separated, described slot part is parallel with described circuit board circumference, spreads all on the whole width of described fill area and all has described slot part.
19, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 1, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, the profile of described resin-sealed portion forms hexagon, the 1st apex of described sealing resin section and be positioned at described prostatitis with being bar and described rank rear with being on the axis of bar with opposed the 2nd apex of described the 1st apex, described the 1st apex has the resin inlet, described the 2nd apex has pore, and comprise inflow adjustment district with described resin inlet, the fill area that contains described semiconductor element, and the district that releases with described pore, also has the slot part that described inflow adjustment district and described fill area are separated, described slot part is parallel with described circuit board circumference, and spread all on the whole width of described fill area and all have this slot part, have again described fill area and described the 2nd slot part of releasing and separating out, described the 2nd slot part is parallel with described circuit board circumference, and spreads all on the whole width of described fill area and all have this slot part.
20, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 6, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, have the linearity runner of circuit board circumference to the described resin-sealed portion of the described subregion portion of prostatitis and rank rear, short prostatitis connects described outside connecting portion and described prostatitis with being bar with runner, the rank rear of the length corresponding with described notch with runner only at described middle interconnecting piece and described rank rear with being that bar engages with described semiconductor mount circuit board.
21, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 7, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, have the linearity runner of circuit board circumference to the described resin-sealed portion of the described subregion portion of prostatitis and rank rear, short prostatitis connects described outside connecting portion and described prostatitis with being bar with runner, the rank rear of the length corresponding with described notch with runner only at described middle interconnecting piece and described rank rear with being that bar engages with described semiconductor mount circuit board.
22, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 8, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, has from the circuit board circumference along described notch the sprue that forms the length of linearity toward the orientation of described subregion portion, also has the secondary channels of weak point that is branched off into the described sealing resin section of described subregion portion from described sprue, the described sprue of the length corresponding with described notch does not connect described semiconductor mount circuit board, short described secondary channels only with described connecting portion and described be that bar engages.
23, a kind of semiconductor device is characterized in that,
Semiconductor element is loaded in described mounting semiconductor district in the described subregion portion of the semiconductor mount circuit board described in the claim 9, resin-sealed portion at the described semiconductor element of described subregion portion's formation sealing, has from the circuit board circumference along described notch the sprue that forms the length of linearity toward the orientation of described subregion portion, also has the secondary channels of weak point that is branched off into the described sealing resin section of described subregion portion from described sprue, the described sprue of the length corresponding with described notch only engages with a sidepiece of described semiconductor mount circuit board, short secondary channels only with described connecting portion and described be that bar engages.
24, a kind of manufacturing method of semiconductor module is characterized in that,
Use the semiconductor mount circuit board described in the claim 1, in described prostatitis usefulness is that bar and described rank rear usefulness are the electroplating region of bar configuration from the extremely described subregion of described outside connecting portion portion, semiconductor element is loaded in mounting semiconductor district in described subregion portion, use is after described electroplating region forms the sealing metal mould of linearity runner and forms resin-sealed of the described semiconductor element of sealing in described subregion portion, cut off described runner from described subregion portion and described sealing resin section, and cut off described subregion portion from described semiconductor mount circuit board.
25, the manufacturing method of semiconductor module described in claim 24 is characterized in that,
At described sealing metal mould the prostatitis subregion group that a pair of described semiconductor mount circuit board is configured to both sides is parallel to the inboard, to be arranged on the bipartite a plurality of pod shape filling pieces of the described semiconductor mount circuit board shape that uniformly-spaced is arranged in a straight line, form pod shape filling piece group, and make a pair of described pod shape filling piece group parallel, and the arrangement pitch of both sides' described pod shape filling piece half spacing that staggers mutually, described pod shape filling piece is configured to staggered palisade;
The described subregion portion in the described subregion portion of the 1st pod shape filling piece group's described pod shape filling piece, the rank rear of the 1st described semiconductor mount circuit board and the prostatitis of the 2nd described semiconductor mount circuit board is configured on the straight line, forms the equidistant runner of runner from described pod shape filling piece to the described resin-sealed portion that the described subregion both sides of portion form;
The described subregion portion in the described subregion portion of the 2nd pod shape filling piece group's described pod shape filling piece, the rank rear of the 2nd described semiconductor mount circuit board and the prostatitis of the 1st described semiconductor mount circuit board is configured on the straight line, forms the equidistant runner of runner from described pod shape filling piece to the described resin-sealed portion that the described subregion both sides of portion form.
26, the manufacturing method of semiconductor module described in claim 24 is characterized in that,
At described sealing metal mould the prostatitis subregion group that a pair of described semiconductor mount circuit board is configured to both sides is parallel to the inboard, to be arranged on the bipartite a plurality of pod shape filling pieces of the described semiconductor mount circuit board shape that uniformly-spaced is arranged in a straight line, form pod shape filling piece group, and make a pair of described pod shape filling piece group parallel, and described pod shape filling piece both sides' arrangement pitch half spacing that staggers mutually, described pod shape filling piece is configured to staggered palisade;
The described subregion portion in the described subregion portion of the 1st pod shape filling piece group's described pod shape filling piece, the rank rear of the 1st described semiconductor mount circuit board and the prostatitis of the 2nd described semiconductor mount circuit board is configured on the straight line, also the described subregion portion of the rank rear of the described subregion portion in the prostatitis of the 2nd pod shape filling piece group's described pod shape filling piece, the 1st described semiconductor mount circuit board and the 2nd described semiconductor mount circuit board is configured on the straight line simultaneously;
Described resin-sealed portion from the described subregion portion of the rank rear of the 1st pod shape filling piece group's described pod shape filling piece to the 1 described semiconductor mount circuit board, press linearity and form runner, also to described resin-sealed portion, press bending and form runner simultaneously from the described subregion portion in the prostatitis of this pod shape filling piece to the 1 described semiconductor mount circuit board;
Described resin-sealed portion from the described subregion portion of the rank rear of the 2nd pod shape filling piece group's described pod shape filling piece to the 2 described semiconductor mount circuit boards, press linearity and form runner, also from the described resin-sealed portion of the described subregion portion in the prostatitis of these pod shape filling piece to the 2 described semiconductor mount circuit boards, press bending and form runner simultaneously.
27, the manufacturing method of semiconductor module described in claim 24 is characterized in that,
At described sealing metal mould the prostatitis subregion group that a pair of described semiconductor mount circuit board is configured to both sides is parallel to the inboard, to be arranged on the bipartite a plurality of pod shape filling pieces of the described semiconductor mount circuit board shape that uniformly-spaced is arranged in a straight line, form pod shape filling piece group;
The subregion portion of described pod shape filling piece and described semiconductor mount circuit board both sides' rank rear is configured on the straight line, also the equidistant runner of runner from described pod shape filling piece to the described resin-sealed portion that the described subregion both sides of portion form is formed linearity simultaneously, the described resin-sealed portion that the described subregion portion in the prostatitis of described semiconductor mount circuit board is formed, runner is formed shape from this pod shape filling piece bending, and with this pod shape filling piece point symmetry shape that is the center.
CN 200610136578 2005-10-24 2006-10-23 Semiconductor mount circuit board, semiconductor device and method of manufacturing semiconductor package Pending CN1956182A (en)

Applications Claiming Priority (4)

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JP2005307914 2005-10-24
JP2005307914 2005-10-24
JP2006228511 2006-08-25
JP2006228510 2006-08-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103241702A (en) * 2012-02-09 2013-08-14 精工爱普生株式会社 Electronic device, method for manufacturing thereof, and electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103241702A (en) * 2012-02-09 2013-08-14 精工爱普生株式会社 Electronic device, method for manufacturing thereof, and electronic apparatus
CN103241702B (en) * 2012-02-09 2016-08-24 精工爱普生株式会社 Electronic device and manufacture method thereof and electronic equipment

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