CN1941360A - Packing structure with stacking platform - Google Patents
Packing structure with stacking platform Download PDFInfo
- Publication number
- CN1941360A CN1941360A CNA2005101059234A CN200510105923A CN1941360A CN 1941360 A CN1941360 A CN 1941360A CN A2005101059234 A CNA2005101059234 A CN A2005101059234A CN 200510105923 A CN200510105923 A CN 200510105923A CN 1941360 A CN1941360 A CN 1941360A
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- chip
- substrate
- gold thread
- packaging part
- sealing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention is concerned with the sealing structure, including: the first base panel, the first sealing piece, the second sealing piece and the sealing glue. It is: the first base panel is with the first surface; the first sealing piece includes the first CMOS chip and the liquid sealing glue; the first CMOS chip sets on the first base panel and electric connects with the first base panel by the first metal line; the liquid sealing glue covers the second surface of the first CMOS chip, and covers the first metal line partly, forms the flat at the surface of the liquid sealing glue; the second sealing piece sets on the flat, the sealing glue covers at least part of the first surface of the first base panel, the first sealing piece and the second sealing piece.
Description
Technical field
The present invention relates to a kind of encapsulating structure, and be particularly related to a kind of encapsulating structure with stacking platform.
Background technology
Along with Chip Packaging evolution, present encapsulation technology can be finished very frivolous packaged chip.And the thin recycling chip-stacked technology of chip is a plurality of thin Chip Packaging together, forms so-called answer encapsulate (package in package) chip or multi-chip module (multi chip module, MCM).Please refer to Fig. 1, it is the section of structure of the multiple packaged chip of tradition, and encapsulating structure 100 comprises substrate 10, first packaging part 20, second packaging part 30 and sealing 40.First packaging part 20 comprises chip 21, chip 23 and sept (spacer) 50, and chip 21 is arranged on the substrate 10, and is electrically connected with substrate 10 by gold thread 22.Chip 23 is arranged at chip 21 tops, and is electrically connected with chip 21 and substrate 10 with gold thread 24 and gold thread 25 respectively.Second packaging part 30 is arranged on the surface 51 of sept 50.Second packaging part 30 comprises substrate 31 and chip 32, and chip 32 is arranged on the substrate 31 and with gold thread 33 electrical connection substrate 31, the second packaging parts 30 and with gold thread 35 and is electrically connected with substrate 10.Sealing 34 covers substrate 31, chip 32 and gold thread 33 get up.Sealing 40 coats surface 12, first packaging part 20 and second packaging part 30 of substrate 10, and substrate 10 bottoms have a plurality of soldered balls (solder ball) 11.
But present chip-stacked technology; link the semi-finished product chip of (wire bond) and fail to provide suitable protection for existing gold thread on substrate, therefore the chip that piles up tilts easily and the line style that links is damaged by pressure, causes the failure of encapsulation; reduce the production qualification rate, make production cost improve.As among Fig. 1 since sept 50 only contact with second packaging part 30 with surface 51, because contact area deficiency, make second packaging part 30 tilt easily, and be pressed onto gold thread 22, gold thread 24 and gold thread 25, cause the encapsulation failure because of disequilibrium or slight vibrations or collision.Moreover, because sept 50 and gold thread 22, gold thread 24 and gold thread 25 stop, cause sealing 40 when irritating mould, can not coat each element fully and produce hole easily, especially between chip 23 and the sept 50, very easily there is the gas hole to produce.This hole may be in the variations in temperature of subsequent technique, produces popcorn effect (popcorneffect) and causes sealing to be broken, and reduce product percent of pass.
Summary of the invention
In view of the foregoing, purpose of the present invention just provides a kind of encapsulating structure with stacking platform, utilizes liquid sealing to form stacking platform, provides chip to put, and can protect line style position and the bond site that need keep.
According to purpose of the present invention, a kind of encapsulating structure is proposed, comprise first substrate, first packaging part, second packaging part and sealing, first substrate has first surface.First packaging part comprises first chip and liquid sealing, and first chip is arranged on first substrate, and is electrically connected with first substrate by first gold thread.Liquid sealing covers the second surface of first chip, and first gold thread of covering part branch, and the surface of liquid sealing forms platform.Second packaging part is arranged on the platform, and sealant covers is to first surface, first packaging part and second packaging part of first substrate of small part.
According to a further object of the present invention, a kind of method for packing is proposed.At first, provide first substrate, have first surface.Then, first chip is set on first substrate.Then, be electrically connected first chip and first substrate with first gold thread.Then, cover the second surface and part first gold thread of first chip with liquid sealing, the surface of liquid sealing forms platform.Then, second packaging part is set in the platform top.Then, reach to the first surface of the substrate of small part with sealant covers first packaging part, second packaging part.
For the present invention's above-mentioned purpose, feature and advantage can be become apparent, two embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 is the section of structure of the multiple packaged chip of tradition;
Fig. 2 is the end view of a kind of encapsulating structure of the present invention's first embodiment;
Fig. 3 A～3G is the encapsulation flow chart of the encapsulating structure of the present invention's first embodiment; And
Fig. 4 is the end view of the encapsulating structure of the present invention's second embodiment.
The main element description of symbols
100,200,300: encapsulating structure
10,31,210,231,310,331: substrate
11,211,311: soldered ball
12,51,212,226,312,326: the surface
20,220,320: the first packaging parts
21,23,33,221,223,232,321,323,332: chip
22,24,25,33,35,222,224,225,233,235,322,324,325,333,335: gold thread
30,230,330: the second packaging parts
34,40,234,240,334,340: sealing
50: sept
250,350: liquid sealing
251,351: platform
252,352: the box dam structure
253,353: colloid
260,360: elargol
Embodiment
Embodiment one
Please refer to Fig. 2, it is the end view of a kind of encapsulating structure of the present invention's first embodiment.Encapsulating structure 200 comprises substrate 210, first packaging part 220, second packaging part 230 and sealing 240.First packaging part 220 comprises chip 221, chip 223 and liquid sealing 250, and chip 221 is arranged on the substrate 210, and is electrically connected with substrate 210 by gold thread 222.Chip 223 is arranged at chip 221 tops, and is electrically connected with chip 221 and substrate 210 with gold thread 224 and gold thread 225 respectively.
Please refer to Fig. 3 A～3G, it is the encapsulation flow chart of the encapsulating structure of the present invention's first embodiment.At first, please refer to Fig. 3 A, substrate 210 is provided, substrate 210 has surface 212, afterwards, chip 221 is set on surface 212.Then, please refer to Fig. 3 B, on the surface 226 of chip 221, chip 223 is set.Then, please refer to Fig. 3 C, be electrically connected chip 221 and substrate 210, be electrically connected chip 223 and chip 221, and be electrically connected chip 223 and substrate 210 with gold thread 225 with gold thread 224 with gold thread 222.Then, please refer to Fig. 3 D, bigger with viscosity, the colloid that can not flow arbitrarily forms box dam structure 252 on the surface 226 of chip 221.Preferably box dam structure 252 is formed at around the surface 226, crosses an accommodation space with the core in surface 226.
Then, please refer to Fig. 3 E, the colloid 253 less with viscosity, that flowability is bigger, its similar elargol is inserted in the accommodation space that box dam structure 252 surrounded, and colloid 253 forms liquid sealing 250 with box dam structure 252.Liquid sealing 250 covers surface 226, part gold thread 222, chip 223, gold thread 224 and the part gold thread 225 of chip 221.Afterwards, encapsulating structure is sent in the baking box toasted.After liquid sealing 250 is solidified, again with the surface rubbing of liquid sealing 250, can be to form for the platform 251 of storing, so first packaging part 220 forms.
Then, please refer to Fig. 3 F, second packaging part 230 is adhered on the platform 251 with elargol 260.Second packaging part 230 comprises substrate 231, chip 232 and sealing 234.Chip 232 is arranged on the substrate 231 and with gold thread 233 and is electrically connected with substrate 231.Sealing 234 covers chip 232, gold thread 233 and substrate 231.Second packaging part 230 also is electrically connected with substrate 210 with gold thread 235.Afterwards, please refer to Fig. 3 G, with surface 212, first packaging part 220 and second packaging part 230 to small part of sealing 240 covered substrates 210, present embodiment is that example illustrates it with whole surface 212 of sealing 240 covered substrates 210.Then, form a plurality of soldered balls 211, to finish the encapsulation step of encapsulating structure 200 in substrate 210 bottoms.
In the encapsulating structure 200 of present embodiment, with liquid sealing 250 coating chips 221 and 223, and the gold thread 222,224 and 225 that is connected.So, when second packaging part 230 was stacked and placed on chip 221 and 223, liquid sealing 250 had coated chip 221 and 223.So liquid sealing 250 than parting between shown in Figure 1 50, more can reach coupled gold thread 222,224 and 225 to chip 221 and 223, provides more perfectly and protects, and to keep the line style of gold thread 222,224 and 225, avoids gold thread 222,224 and 225 short circuits.
In addition, because the surface of liquid sealing 250 forms the suitable platform of area of area and chip 221, put for second packaging part 230.Be formed at chip 21 tops among Fig. 1, the sept 50 of the side of chip 23 is compared, the surface of the platform 251 that liquid sealing 250 is provided is greater than the area of sept 50, and platform 251 can touch most of zone of the bottom surface of second packaging part 230.So second packaging part 230 of present embodiment is placed on the platform 251 reposefully, can avoid second packaging part 230 to produce the phenomenon of inclination.
Moreover; because present embodiment uses viscosity liquid sealing 250 less, that flowability is bigger to protect chip 221 and 223; the probability that liquid sealing 250 produces the gas holes is irritated mold technique more than uses of Fig. 1, and to form the probability of sealing 40 little, so the encapsulating structure of present embodiment also has the advantage of raising qualification rate.
Embodiment two
Please refer to Fig. 4, it is the end view of the encapsulating structure of the present invention's second embodiment.The main difference part of the encapsulating structure 300 of present embodiment and the encapsulating structure 200 of first embodiment is the part of liquid sealing and substrate contacts.The liquid sealing 350 of present embodiment is gone back the surface 312 of cover part substrate 310 except that the surface 326 that covers chip 321 fully.The generation type of liquid sealing 350 for example is, forms box dam structure 352 earlier in the surface 312 of substrate 310, and box dam structure 352 is positioned at apart from enclosing outside chip 321 1 segment distances.Afterwards, colloid 353 is inserted in the accommodation space that box dam 352 surrounded, formed the surface 312 of liquid sealing 350 cover part substrates 310 and the surface 326 of chip 321.The annexation of all the other elements is identical with first embodiment with the formation step, repeats no more.
Because the area of the platform 351 of the sealing 350 that formed of second embodiment, greater than the area of the platform 251 of the sealing 250 of first embodiment.So present embodiment can provide bigger platform 351, so that second packaging part 330 is able to be placed in more reposefully on the platform 351.
The encapsulating structure that the above embodiment of the present invention is disclosed with stacking platform; with sealant covers chip and connection gold thread thereof; the protection of protecting chip effectively and connecting gold thread so can be provided, and form platform, put for another chip in liquid sealing surface.So the technology that the present invention's encapsulating structure can be simple also provides chip one preferable stacking platform, the gold thread of avoiding stacked chips to tilt to damage by pressure binding causes damage, can improve the qualification rate of product, reduces production costs, and is the present invention's advantage and characteristic.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (14)
1. encapsulating structure is characterized in that comprising:
First substrate has first surface;
First packaging part comprises:
First chip is arranged on this first substrate, and is electrically connected with this first substrate by first gold thread; And
Liquid sealing covers the second surface of this first chip, and this first gold thread of covering part branchs, the surface formation platform of this liquid state sealing;
Second packaging part is arranged on this platform; And
Sealing coats this first surface, this first packaging part and this second packaging part to this first substrate of small part.
2. the encapsulating structure according to claim 1, what it is characterized in that this first packaging part should the liquid state sealing cover this first chip fully, and this first surface of this first substrate of cover part.
3. the encapsulating structure according to claim 1 is characterized in that this second packaging part comprises second chip, second substrate and second gold thread, and this second chip is electrically connected with this second substrate by this second gold thread.
4. the encapsulating structure according to claim 1 is characterized in that also comprising the 3rd chip, is arranged on this second surface of this first chip, and this liquid state sealing also coats the 3rd chip.
5. the encapsulating structure according to claim 4 is characterized in that the 3rd chip is electrically connected this liquid state sealant covers the 3rd gold thread by at least one the 3rd gold thread with this first chip.
6. the encapsulating structure according to claim 5 is characterized in that the 3rd chip is electrically connected the 4th gold thread of this liquid state sealant covers part by the 4th gold thread with this first substrate.
7. the encapsulating structure according to claim 1 is characterized in that this second packaging part is arranged on this platform by elargol (epoxy).
8. the encapsulating structure according to claim 1 is characterized in that this first base plate bottom has a plurality of soldered balls (solder ball).
9. method for packing is characterized in that comprising:
First substrate is provided, has first surface;
First chip is set on this first substrate;
Be electrically connected this first chip and this first substrate with first gold thread;
Cover second surface and this first gold thread of part of this first chip, the surface of this liquid state sealing formation platform with liquid sealing;
Second packaging part is set in this platform top; And
Reach to this first surface of this substrate of small part with this first packaging part of sealant covers, this second packaging part.
10. the method for packing according to claim 9, it is characterized in that covering this second surface and this first gold thread of part of this first chip in this liquid state sealing, the surface of this liquid state sealing forms in the step of this platform, this first surface of this liquid state sealing and this first substrate of cover part.
11. the method for packing according to claim 9, it is characterized in that this second packaging part also comprises second chip, second substrate and second gold thread, be provided with in the step of this second packaging part above this platform, also comprising: be electrically connected this second chip and this second substrate with this second gold thread.
12. the method for packing according to claim 9, it is characterized in that in be provided with this first chip on this first substrate after, also comprise:
The 3rd chip is set on this second surface of this first chip;
Wherein, at this second surface that covers this first chip with this liquid state sealing and this first gold thread of part, the surface of this liquid state sealing forms in the step of this platform, also with this liquid state sealant covers the 3rd chip.
13. the method for packing according to claim 12, it is characterized in that in be provided with the 3rd chip on this second surface of this first chip after, also comprise:
Be electrically connected the 3rd chip and this first chip with the 3rd gold thread, and be electrically connected the 3rd chip and this first substrate with the 4th gold thread;
Wherein, the 4th gold thread of this liquid state sealant covers the 3rd gold thread and part.
14. the method for packing according to claim 9 is characterized in that also comprising in this second packaging part being set in the step of this platform top:
With bonding this second packaging part of elargol (epoxy) on this platform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101059234A CN100541782C (en) | 2005-09-30 | 2005-09-30 | Encapsulating structure and method for packing thereof with stacking platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101059234A CN100541782C (en) | 2005-09-30 | 2005-09-30 | Encapsulating structure and method for packing thereof with stacking platform |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941360A true CN1941360A (en) | 2007-04-04 |
| CN100541782C CN100541782C (en) | 2009-09-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005101059234A Active CN100541782C (en) | 2005-09-30 | 2005-09-30 | Encapsulating structure and method for packing thereof with stacking platform |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124223A (en) * | 2013-04-23 | 2014-10-29 | 巨擘科技股份有限公司 | Electronic system and core module thereof |
-
2005
- 2005-09-30 CN CNB2005101059234A patent/CN100541782C/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124223A (en) * | 2013-04-23 | 2014-10-29 | 巨擘科技股份有限公司 | Electronic system and core module thereof |
| CN104124223B (en) * | 2013-04-23 | 2017-05-03 | 巨擘科技股份有限公司 | Electronic system and core module thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100541782C (en) | 2009-09-16 |
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