CN1941198B - Internal signal generator for use in semiconductor memory device - Google Patents
Internal signal generator for use in semiconductor memory device Download PDFInfo
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- CN1941198B CN1941198B CN2006101412038A CN200610141203A CN1941198B CN 1941198 B CN1941198 B CN 1941198B CN 2006101412038 A CN2006101412038 A CN 2006101412038A CN 200610141203 A CN200610141203 A CN 200610141203A CN 1941198 B CN1941198 B CN 1941198B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
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Abstract
A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches, each of which latches an external address in response to the activation of an external command and outputs an internal address in response to the activation of an internal command corresponding to the external command. A pipe latch control unit is configured to control the pipe latch unit to sequentially enable the plurality of pipe latches. An output drive unit is configured to selectively output the internal address or the external address. The internal command is activated after a predetermined latency from an activation timing of the external command.
Description
Technical field
The invention relates to a kind of semiconductor storage, and more specific be about a kind of internal signal generator that is used to reduce current drain in the semiconductor storage that is used in.
Background technology
Semiconductor storage receives outer array order after accomplishing immediately at input one activation command (active command) and in response to the operation of this activation command usually, for example external read order or external write order.Hereinafter, the delay between the input of the input of activation command and outer array order is called tRCD.Input is ordered a together address of input with outer array after tRCD.Yet,, also possibly set the input timing of outer array order such as the semiconductor storage of DDR2 SDRAM even before tRCD.The outer array order that semiconductor storage will be imported before tRCD keeps a schedule time, and generation is ordered corresponding to the inner array of this outer array order after the sequential of this activation command is gone through tRCD, for example internal read order or inner write order.The schedule time between the generation that the input of outer array order and inner array are ordered is called additional delay (AL).An external address of together importing with the outer array order also keeps additional delay (AL), and produces the home address corresponding to this external address subsequently.
Fig. 1 is the sequential chart of the read operation of semiconductor storage.
For carrying out read operation, after the input timing of external read order RD and external address EXT_ADDR is gone through additional delay AL, such as semiconductor storage generation internal read address RD_IADD and the internal read order IRD of DDR2 SDRAM.After a schedule time of internal read order IRD and internal read address RD_IADD generation, semiconductor storage begins to read valid data D0 to D3.Internal read is ordered the schedule time between the beginning of generation and read operation of IRD and home address RD_IADD be called column address strobe (CAS) time-delay CL.After the additional delay AL and CAS time-delay CL of the input timing of read command and address, semiconductor storage begins to carry out read operation.The value that obtains through CAS is delayed time CL and additional delay AL addition is called as read latch RL.
Fig. 2 is the sequential chart of the write operation of semiconductor storage.
Under the situation of write operation, semiconductor storage produces inner write order IWT and inner write address WT_IADD, and from the input timing of write order WT and external address EXT_ADDR write time-delay WL after carry out write operation.Write time-delay WL and lack a clock than read latch RL.That is WL=RL-1=(AL+CL)-1.
Fig. 3 is the calcspar of the convention internal signal generator of semiconductor storage.
Internal signal generator can be used for producing home address and internal command usually.That is, provide internal signal generator respectively to be used for each of external address EXT_ADDR, read write command and thesaurus (bank) address.Among Fig. 3, internal signal generator is used to produce an internal column address.
Internal signal generator comprises reads address-generation unit 10, write address generation unit 20 and output unit 30.Read address-generation unit 10 and postpone external address EXT_ADDR, and output is corresponding to the internal read address RD_IADD of the additional delay of this semiconductor storage in response to clock signal clk.Write address generation unit 20 postpones internal read address RD_IADD in response to clock signal clk, and output is corresponding to the inside write address WT_IADD that writes time-delay of this semiconductor storage.Output unit 30 is selected one of internal read address RD_IADD and inner write address WT_IADD in response to writing status signal WTS, exports internal column address CA by this.Write status signal WTS and during write operation, be in state of activation.
Read address-generation unit 10 and comprise the additional delay delay cell 12 and first selected cell 14.Additional delay delay cell 12 produces a plurality of extra addresses through postponing external address EXT_ADDR in response to clock signal clk.First selected cell 14 is selected in the extra addresses extra address corresponding to the additional delay of semiconductor storage, and output should selected extra address as internal read address RD_IADD.Write address generation unit 20 comprises the CAS time-delay delay cell 22 and second selected cell 24.CAS time-delay delay cell 22 is through postponing internal read address RD_IADD in response to clock signal clk, to produce a plurality of CAS address.Second selected cell 24 is selected in the CAS addresses CAS address corresponding to the CAS time-delay of semiconductor storage, and output should selected CAS address as inner write address WT_IADD.
Additional delay delay cell 12 comprises a plurality of triggers that are one another in series and connect.CAS time-delay delay cell 22 also comprises a plurality of triggers that are one another in series and connect.The number of the trigger that comprises in additional delay delay cell 12 and the CAS time-delay delay cell 22 is corresponding to maximum additional delay and maximum CAS time-delay.When maximum additional delay is six clocks and maximum CAS time-delay when being seven clocks, an internal signal generator comprises 13 triggers.As previously discussed, because provide internal signal generator to be used for each of external address EXT_ADDR, read write command and thesaurus address, so need hundreds of triggers to be used for semiconductor storage.Therefore, a large amount of electric currents of semiconductor storage consumption, and the size of semiconductor storage increases.In addition, when additional delay that sets when semiconductor storage and CAS time-delay are different from maximum additional delay and maximum CAS time-delay, needn't make in additional delay delay cell 12 and the CAS time-delay delay cell 22 each included trigger all carry out latch operation.Yet each included trigger is all carried out latch operation in additional delay delay cell 12 and the CAS time-delay delay cell 22 under the situation of not considering additional delay and CAS time-delay.Therefore, the internal signal generator shown in Fig. 3 has caused unnecessary current drain.
Summary of the invention
A kind of semiconductor storage comprises the internal signal generator that is used to reduce current drain and chip size.
According to an aspect of the present invention; A kind of semiconductor storage comprises that one has the pipeline latch unit of a plurality of pipeline latch; In the said pipeline latch each latchs an external address in response to the startup of an external command; And, export a home address in response to a startup corresponding to the internal command of this external command.One pipeline latch control module is through being configured to control this pipeline latch unit to launch this a plurality of pipeline latch in proper order.One output driver element is through being configured to selectivity this home address of output or this external address.This internal command is starting after a predetermined time-delay of the startup of this correspondence external command.And, when this semiconductor device is not carried out write operation under the situation that does not have additional delay, export this home address, otherwise export this external address.
According to a further aspect in the invention, a kind of method that is used in generation one home address in the semiconductor storage is provided, it comprises: in response to the input of an external command, an external address is latched in a pipeline latch; Produce an internal command through postponing this external command according to a predetermined time-delay; In response to the startup of this internal command, export this through the external address that latchs as this home address; And select in this home address and this external address, wherein when this semiconductor device is not carried out write operation under the situation that does not have additional delay, export this home address, otherwise export this external address.
Description of drawings
Through the description of with reference to the accompanying drawings preferred embodiment being carried out, above-mentioned and other purposes of the present invention and characteristic will become obviously, wherein:
Fig. 1 is the sequential chart of the read operation of semiconductor storage;
Fig. 2 is the sequential chart of the write operation of semiconductor storage;
Fig. 3 is the calcspar that is used for the convention internal signal generator of semiconductor storage;
Fig. 4 is for be used for the calcspar of the internal signal generator of semiconductor storage according to an embodiment of the invention;
Fig. 5 is the calcspar of the pipeline latch control module shown in Fig. 4;
Fig. 6 A is the schematic circuit of the initialization unit shown in Fig. 5 according to an embodiment of the invention;
Fig. 6 B is the schematic circuit of the initialization unit shown in Fig. 5 according to another embodiment of the present invention;
Fig. 6 C is the schematic circuit of the initialization unit shown in Fig. 5 according to still another embodiment of the invention;
Fig. 7 is the schematic circuit of the PI drive signal generation unit shown in Fig. 5;
Fig. 8 is the schematic circuit of the PO drive signal generation unit shown in Fig. 5;
Fig. 9 is the calcspar of the PI shift unit shown in Fig. 5;
Figure 10 is the internal circuit diagram of reseting trigger shown in Fig. 9;
Figure 11 is the internal circuit diagram of the SFF shown in Fig. 9;
Figure 12 is the internal circuit diagram of the PI driver element shown in Fig. 5;
Figure 13 is the calcspar of the PO shift unit shown in Fig. 5;
Figure 14 is the internal circuit diagram of the PO driver element shown in Fig. 5;
Figure 15 is the oscillogram of the operation of the PI signal generation unit shown in Fig. 5;
Figure 16 is the oscillogram of the operation of the PO signal generation unit shown in Fig. 5;
Figure 17 is the schematic circuit of first pipeline latch shown in Fig. 4; And
Figure 18 is the schematic circuit of the output driver element shown in Fig. 4.
Embodiment
Hereinafter will describe in detail according to semiconductor storage of the present invention referring to accompanying drawing.
Fig. 4 is for be used for the calcspar of the internal signal generator of semiconductor storage according to an embodiment of the invention.
Internal signal generator comprises pipeline latch control module 100, pipeline latch unit 200 and output driver element 300.Pipeline latch control module 100 is launched pipeline input signal PI < 0:N>in proper order when externally read command EXT_RD or external write order EXT_WT imports at every turn.Pipeline latch control module 100 is also launched pipeline output signal PO < 0:N>in proper order when internal read orders INT_RD or inner write order INT_WT to import at every turn.Pipeline latch unit 200 comprises a plurality of pipeline latch; First pipeline latch 210 for example; Wherein each pipeline latch all latchs external address EXT_ADDR in response to the pipeline input signal PI < 0:N>of correspondence; And export signal PO < 0:N>in response to the pipeline of correspondence and export through the address of latching, as home address INT_ADDR.Output driver element 300 is in response to zero additional delay signal AL < 0>and write status signal WTS, and selectivity is exported among home address INT_ADDR and the external address EXT_ADDR.When the additional delay of semiconductor storage was made as zero clock, zero additional delay signal AL < 0>was in state of activation.Write status signal WTS and during write operation, be in state of activation.
Internal signal generator further comprises first and second delay cell 400 and 500.First delay cell 400 postpones external read order EXT_RD and output is ordered INT_RD corresponding to the internal read of the additional delay of semiconductor storage.Second delay cell 500 postpones external write order EXT_WT and exports the inside write order INT_WT that writes time-delay corresponding to semiconductor storage.In one embodiment of this invention, the available circuit of reading address-generation unit 10 and write address generation unit 20 that is similar to is realized first and second delay cell 400 and 500 respectively.
Fig. 5 is the calcspar of the pipeline latch control module 100 shown in Fig. 4.
Pipeline latch control module 100 comprises initialization unit 110, pipeline input (PI) drive signal generation unit 120, pipeline output (PO) drive signal generation unit 130, pipeline input (PI) signal generation unit 140, and pipeline output (PO) signal generation unit 150.
Initialization unit 110 in response to zero additional delay signal AL < 0 >, write status signal WTS and initially reset signal ST_FL, produce and reset signal RST, to be used for initialization PI signal generation unit 140 and PO signal generation unit 150.In the initial operation time of semiconductor storage, initially reset signal ST_FL and reset PI signal generation unit 140 and PO signal generation unit 150, being intended to a reliable operation is target.When external read ordered EXT_RD or external write order EXT_WT to be in state of activation, PI drive signal generation unit 120 was launched pipeline input (PI) drive signal ERW.When internal read ordered INT_RD or inner write order INT_WT to be in state of activation, PO drive signal generation unit 130 was launched pipeline output (PO) drive signal IRW.PI signal generation unit 140 is activated one of pipeline input signal PI < 0:N>corresponding to PI drive signal ERW.PO signal generation unit 150 is activated one of pipeline output signal PO < 0:N>corresponding to PO drive signal IRW.That is PI signal generation unit 140 output channel input signal PI < 0:N>one by one when each input external read order EXT_RD or external write order EXT_WT.Similarly, PO signal generation unit 150 output channel output signal PO < 0:N>one by one when each input internal read order INT_RD or inner write order INT_WT.
PI signal generation unit 140 comprises pipeline input (PI) shift unit 142 and pipeline input (PI) driver element 144.PI shift unit 142 produces a plurality of pipeline input (PI) inhibit signal P < 0:N>in proper order with the mode that is synchronized with PI drive signal ERW.In other words, when each input external read order EXT_RD or external write order EXT_WT, export PI inhibit signal P < 0:N>one by one.The PI driver element 144 that receives PI inhibit signal P < 0:N>and PI drive signal ERW drives pipeline input signal PI < 0:N>in proper order.PO signal generation unit 150 comprises pipeline output (PO) shift unit 152 and pipeline output (PO) driver element 154.PO shift unit 152 produces a plurality of pipeline output (PO) inhibit signals in proper order with the mode that is synchronized with PO drive signal IRW.In other words, when each input internal read order INT_RD or inner write order INT_WT, export the PO inhibit signal one by one.The PO driver element 154 that receives PO inhibit signal and PO drive signal IRW drives pipeline output signal PO < 0:N>in proper order.
Fig. 6 A is the schematic circuit of the initialization unit shown in Fig. 5 according to an embodiment of the invention.
Initialization unit 110a output with two phase inverter I1 and I2 is initially reseted signal ST_FL as reseting signal RST.When starting weight was established signal ST_FL and is in state of activation originally, initialization unit 110a launched and resets signal RST.
Fig. 6 B is the schematic circuit of the initialization unit shown in Fig. 5 according to another embodiment of the present invention.
Fig. 6 C is the schematic circuit of the initialization unit shown in Fig. 5 according to still another embodiment of the invention.
Initialization unit 110c comprises the 4th phase inverter I4, the second AND gate AD2 and the second OR-gate OR2.The 4th phase inverter I4 makes and writes status signal WTS anti-phase.The second AND gate AD2 logical combination is write status signal WTS, zero additional delay signal AL < 0>and test mode signal TS_MD through anti-phase.Test mode signal TS_MD is in state of activation during test pattern.The output of the second OR-gate OR2 logical combination, the second AND gate AD2 with initially reset signal ST_FL.When test mode signal TS_MD is in that state of activation, zero additional delay signal AL < 0>are in state of activation and when writing status signal WTS and being in unactivated state, initialization unit 110c launches and resets signal RST.
Fig. 7 is the schematic circuit of the PI drive signal generation unit 120 shown in Fig. 5.
PI drive signal generation unit 120 comprises the 3rd OR-gate OR3, its logical combination external read order EXT_RD and external write order EXT_WT.When external read order EXT_RD was in state of activation or external write order EXT_WT and is in state of activation, PI drive signal generation unit 120 was launched PI drive signal ERW.
Fig. 8 is the schematic circuit of the PO drive signal generation unit 130 shown in Fig. 5.
PO drive signal generation unit 130 comprises the 4th OR-gate OR4, its logical combination internal read order INT_RD and inner write order INT_WT.When internal read order INT_RD was in state of activation or inner write order INT_WT and is in state of activation, PO drive signal generation unit 130 was launched PO drive signal IRW.
Fig. 9 is the calcspar of the PI shift unit 142 shown in Fig. 5.
PI shift unit 142 comprises a plurality of trigger (for example 142a) and SFF 142d of reseting.Reseting trigger is one another in series and connects and output PI inhibit signal P < 0:N >.Each resets trigger (for example 142a) to be synchronized with the mode of PI drive signal ERW, will transfer to next via the first lead-out terminal Q via an input signal of input terminal D input and reset trigger.Each second output of reseting trigger (for example 142a) is output as the PI inhibit signal via second lead-out terminal/Q, for example P < 0 >.First output of reseting trigger 142b transfers to the input terminal D of the most last trigger 142c and the input terminal D of SFF 142d.First output of SFF 142d via first reset trigger 142a input terminal D export this to and first reset trigger 142a.Reset trigger and reset its first and second output in response to reseting signal RST.SFF 142d sets its first and second output in response to reseting signal RST.
Figure 10 is the internal circuit diagram of reseting trigger shown in Fig. 9.
Reset trigger and comprise two transmission gate TG1 and TG2, two latchs 1 and 2, and the 7th phase inverter I7.The first transmission gate TG1 is in response to the PI drive signal ERW of logic low, and transmission is via an input signal of input terminal D input.First latch 1 latchs the output of the first transmission gate TG1.When reseting signal RST and be in state of activation, the output of first latch, 1 output logic high level.When reseting signal RST and be in unactivated state, the output that first latch 1 latched and exported the first transmission gate TG1.The 7th phase inverter I7 makes the output anti-phase of first latch 1, and exports PI inhibit signal P < 0:N>via second terminal/Q.The second transmission gate TG2 transmits the output of first latch 1 in response to the PI drive signal ERW of logic high.When reseting signal RST and be in state of activation, the low level output of second latch, 2 output logics.When reseting signal RST and be in unactivated state, the output that second latch 2 latchs and exports the second transmission gate TG2 via the first lead-out terminal Q.
When reseting signal RST and be in state of activation, shown in Figure 10 reset trigger will be respectively via first and second lead-out terminal Q and/first and second output of Q output is reset to logic low.When reseting signal RST and be in unactivated state, reset trigger when PI drive signal ERW has logic low, will be output as PI inhibit signal P < 0:N>via second lead-out terminal/Q via the input signal of input terminal D input.When reseting signal RST and be in unactivated state and PI drive signal ERW and have logic high, reset trigger via this input signal of first lead-out terminal Q output.
Figure 11 is the internal circuit diagram of the SFF shown in Fig. 9.
SFF comprises two transmission gate TG3 and TG4, two latchs 3 and 4, and the tenth phase inverter I10.When PI drive signal ERW had logic low, the 3rd transmission gate TG3 transmission was via an input signal of input terminal D input.When reseting signal RST and be in state of activation, the low level output of the 3rd latch 3 output logics.When reseting signal RST and be in unactivated state, the output that the 3rd latch 3 latched and exported the 3rd transmission gate TG3.The tenth phase inverter I10 makes the output anti-phase of the 3rd latch 3.The output of the tenth phase inverter I10 is via second lead-out terminal/Q output.The 4th transmission gate TG4 transmits the output of the 3rd latch 3 in response to the PI drive signal of logic high.When reseting signal RST and be in state of activation, the low level output signal of quad latch 4 output logics.When reseting signal RST and be in unactivated state, the output that quad latch 4 latchs and exports the 4th transmission gate TG4 via the first lead-out terminal Q.
The 3rd latch 3 comprises the second NOR gate NR2 and the 9th phase inverter I9.The output that the second NOR gate NR2 logical combination is reseted signal RST and the 3rd transmission gate TG3.The 9th phase inverter I9 makes the output anti-phase of the second NOR gate NR2.The lead-out terminal of the 9th phase inverter I9 is connected to the lead-out terminal of the 3rd transmission gate TG3.Quad latch 4 comprises the second NOT-AND gate ND2 and two phase inverter I11 and I12.The 11 phase inverter I11 makes and resets signal RST anti-phase.The output of the second NOT-AND gate ND2 logical combination the 11 phase inverter I11 and the output of the 4th transmission gate TG4.The 12 phase inverter I12 makes the output anti-phase of the 4th transmission gate TG4.The lead-out terminal of the 12 phase inverter I12 is connected to the lead-out terminal of the 4th transmission gate TG4.
When reseting signal RST and be in state of activation, the SFF shown in Figure 11 will be respectively via first and second lead-out terminal Q and/first and second output of Q output is set at logic low.When reseting signal RST and be in unactivated state, when SFF has logic low in PI drive signal ERW, will be via the input signal of input terminal D input via second lead-out terminal/Q output.When reseting signal RST and be in unactivated state and PI drive signal ERW and have logic high, SFF is via this input signal of first lead-out terminal Q output.
Figure 12 is the internal circuit diagram of the PI driver element 144 shown in Fig. 5.
Figure 13 is the calcspar of the PO shift unit 152 shown in Fig. 5.
Except each reset trigger and SFF all with the synchronous executable operations of PO drive signal IRW, PO shift unit 152 has the circuit of the PI shift unit 142 that is similar to shown in Fig. 9.Reseting trigger and SFF has and is similar to the circuit of reseting trigger and SFF shown in Figure 10 and 11 respectively.
Figure 14 is the internal circuit diagram of the PO driver element 154 shown in Fig. 5.
PO driver element 154 comprises a plurality of impact dampers.Each buffer buffers is exported the PO inhibit signal P ' < 0:N>from the correspondence of PO shift unit 152, and it is output as pipeline output signal PO < 0:N >.
Figure 15 is the oscillogram of the operation of the PI signal generation unit 140 shown in Fig. 5.
When reseting signal RST and be in state of activation, the trigger of reseting in the PI signal generation unit 140 is reset to logic low with its first and second output.SFF is set at logic high with its first and second output.
When reseting signal RST and be in unactivated state; First resets the input signal of trigger 142a transmission from SFF 142d; And in response to the PI drive signal ERW of logic low, via a PI inhibit signal P < 0>of second lead-out terminal/Q output logic high level.When PI drive signal ERW had logic high, first reseted first output of trigger 142a via the first lead-out terminal Q output logic high level.Subsequently; When PI drive signal ERW has logic low; Second resets the input signal (that is, first reset first output of trigger 142a) of trigger transmission via input terminal D input, and exports the 2nd PI inhibit signal P < 1>via second lead-out terminal/Q.When PI drive signal ERW had logic high, second reseted first output of trigger output logic high level.As previously discussed, PI shift unit 142 is launched PI inhibit signal P < 0:N>in proper order in response to cancelling of PI drive signal ERW.Between the starting period of PI drive signal ERW, the driver output PI inhibit signal P < 0:N>in the PI driver element 144 is as pipeline input signal PI < 0:N >.Therefore, the pulsewidth of pipeline input signal PI < 0:N>is identical with the pulsewidth of PI drive signal ERW.
Figure 16 is the oscillogram of the operation of the PO signal generation unit 150 shown in Fig. 5.
When reseting signal RST and be in unactivated state, first resets the input signal of trigger transmission from SFF, and in response to the PO drive signal IRW of logic low, via a PO inhibit signal of second lead-out terminal/Q output logic high level.When PO drive signal IRW had logic high, first reseted first output of trigger via the first lead-out terminal Q output logic high level.Subsequently, when PO drive signal IRW had logic low, second reseted the input signal (that is, first reset first output of trigger) of trigger transmission via input terminal D input, and exports the 2nd PO inhibit signal via second lead-out terminal/Q.When PO drive signal IRW had logic high, second reseted first output of trigger output logic high level.As previously discussed, PO shift unit 152 is launched the PO inhibit signal in proper order in response to cancelling of PO drive signal IRW.Driver output PO inhibit signal in the PO driver element 154 is as pipeline output signal PO < 0:N >.The pulsewidth of pipeline output signal PO < 0:N>is identical with the pulsewidth of PO inhibit signal.That is, the input timing of self-corresponding internal command rises and ends until the input timing of next internal command, and pipeline output signal PO < 0:N>is in state of activation.
Figure 17 is the schematic circuit of first pipeline latch 210 shown in Fig. 4.
Internal signal generator of the present invention comprises a plurality of pipeline latch, for example 210.Therefore, each of external address EXT_ADDR all latchs in different pipeline latch.Confirm the number of pipeline latch included in the pipeline latch unit 200 by the delay (hereinafter being called tCCD) that writes time-delay WL and CAS to CAS of semiconductor storage.That is, the number of pipeline latch is WL/tCCD.TCCD representes two continuous shortest times between the input timing of the external commands of input.In other words, internal signal generator comprises and the as many pipeline latch of carry out the needed maximum delay of an operation according to an external command EXT_ADDR in, importing of external address EXT_ADDR.For example, the tCCD of DDR2 SDRAM is two clocks.When maximum additional delay is six clocks and maximum CAS time-delay when being seven clocks, it is 13 clocks that the maximum of DDR2 SDRAM writes time-delay WL.In the case, DDR2 SDRAM comprises seven pipeline latch.Compare with the conventional devices shown in Fig. 3, when maximum additional delay and maximum CAS delay time when identical, the internal signal generator shown in Fig. 4 comprises the trigger of similar number, and therefore the present invention can reduce chip size.
Figure 18 is the schematic circuit of the output driver element 300 shown in Fig. 4.
When zero additional delay signal AL < 0>is in state of activation and when writing status signal WTS and being in unactivated state, selects the selection signal of signal generation unit 340 output logic high level.Otherwise, select signal to have logic low.When selecting signal to be logic high, selected cell 360 is selected external address EXT_ADDR.When selecting signal to have logic low, selected cell 360 selects to latch the home address INT_ADDR in second latch unit 320.That is, when the additional delay of semiconductor storage was zero clock and semiconductor storage execution read operation, output driver element 300 output external address EXT_ADDR were as column address CA.Otherwise INT_ADDR is as column address for output driver output home address.
As previously discussed, the present invention latchs external address EXT_ADDR but not displacement external address EXT_ADDR in a predetermined time-delay, so that output home address INT_ADDR.That is, the present invention latchs the external address EXT_ADDR that together imports with external read order or external write order, and exports the external address EXT_ADDR through latching in response to the startup of internal read order or inner write order, as home address INT_ADDR.Therefore, the present invention has reduced the number of trigger, and therefore can reduce current drain.
The application's case contains the theme (respectively at applying for Korean Patent office on September 29th, 2005 and on Dec 29th, 2005) relevant for korean patent application case 2005-090891 number and 2005-134002 number, and the full content of said patent application case is incorporated herein by reference.
Though described the present invention about specific embodiment, it will be apparent to those skilled in the art that and under the situation of spirit of the present invention that does not depart from following claims and defined and category, to make various changes and modification.
Claims (31)
1. semiconductor storage, it comprises:
One pipeline latch control module, it launches the pipeline input signal through being configured to circulate in response to external command, and circulates in response to internal command and to launch pipeline output signal;
One pipeline latch unit, it comprises a plurality of pipeline latch, each in the said pipeline latch latchs external address in response to the pipeline input signal, and exports one and latch external address as a home address in response to pipeline output signal; And
One output driver element; It is through being configured to receive home address and the external address from the output of pipeline latch unit; And this home address of selectivity output or this external address be as column address, wherein when this semiconductor device when not carry out write operation and additional delay be zero, export this external address; Otherwise export this home address
Wherein this internal command is after a predetermined time-delay of the startup that starts from a corresponding external command, to start,
Wherein said pipeline latch control module comprises
One pipeline input drive signal generation unit, it is through being configured to produce a pipeline input drive signal in response to the startup of this external command,
One pipeline input signal generation unit; Its through a plurality of triggers of reseting of being configured to connect by being one another in series in response to this pipeline input drive signal; Reset the pipeline input delay signal of second lead-out terminal output, one correspondence of trigger via each; And circulate in response to this pipeline input drive signal and this a plurality of pipeline input delay signals and to launch the pipeline input signal, reach
One initialization unit, it resets signal through being configured to produce one, being used for during the initial operation or when this semiconductor storage is carried out a read operation under the situation that does not have an additional delay, this pipeline input signal generation unit of initialization, and
Wherein, Said a plurality of this one first output of reseting trigger of reseting the end position place of second in the trigger is received by the input terminal of a SFF; And this SFF provides its first output to this and a plurality ofly resets in the trigger this and first reset trigger; The said trigger of reseting is reseted the startup of signal in response to this, its first and second output is reset to one second logic level, and this SFF is reseted the startup of signal in response to this; Its first and second output is set at one first logic level, and said a plurality of each that reset in the trigger comprise
One the 3rd transmission gate, it is in order to transmit this input signal in response to this pipeline input drive signal of this second logic level;
One second latch unit, it is used for reseting the output that signal latchs the 3rd transmission gate when cancelling at this;
One second phase inverter, it is used to make an output anti-phase of this second latch unit, and via this second lead-out terminal output;
One the 4th transmission gate, it transmits this output of this second latch unit in order to this pipeline input drive signal in response to this first logic level; And
One the 3rd latch unit, it is used for reseting the output that signal latchs the 4th transmission gate when being cancelled at this, and output should be through latched signal as this second output.
2. semiconductor storage as claimed in claim 1, wherein this external command comprises external read order and external write order, and this internal command comprises an internal read order and an inner write order.
3. semiconductor storage as claimed in claim 2, wherein this output driver element comprises:
One latch unit, it is through being configured to latch this home address;
One selects the signal generation unit; It is set to zero clock and this semiconductor storage when not carrying out a write operation through being configured to a additional delay at this semiconductor storage; Produce one of one first logic level and select signal, otherwise produce this selection signal of one second logic level;
One selected cell, it is through being configured to export this external address in response to this selection signal of this first logic level, and exports this home address in response to this selection signal of this second logic level; And
One output driver; It is exported as an internal column address through being configured to export one of this selected cell; Wherein be activated and one when writing status signal and being cancelled when one zero additional delay signals, this select this first logic level of signal generation unit output this select signal.
4. semiconductor storage as claimed in claim 3, wherein this selection signal generation unit comprises:
One first phase inverter, it is used to make this to write the status signal anti-phase; And
One first AND gate, it is used for logical groups should an output of first phase inverter and this zero additional delay signal.
5. semiconductor storage as claimed in claim 4, wherein this selected cell comprises:
One first transmission gate, it is in order to transmit this external address in response to this selection signal of this first logic level; And
One second transmission gate, it is in order to transmit this home address in response to this selection signal of this second logic level.
6. semiconductor storage as claimed in claim 5, wherein this output driver comprises the phase inverter of the even number of the connection that is one another in series.
7. semiconductor storage as claimed in claim 6, each in the wherein said pipeline latch comprises:
One first phase inverter, it is used to make this external address anti-phase;
One first transmission gate, it transmits an output of this first phase inverter in order to the startup in response to a corresponding pipeline input signal;
One first latch unit, it is used to latch an output of this first transmission gate; And
One second transmission gate, it transmits an output of this first latch unit, as this home address in order to the startup in response to a corresponding pipeline output signal.
8. semiconductor storage as claimed in claim 2, each in the wherein said pipeline latch comprises:
One first phase inverter, it is used to make this external address anti-phase;
One first transmission gate, it transmits an output of this first phase inverter in order to the startup in response to a corresponding pipeline input signal;
One first latch unit, it is used to latch an output of this first transmission gate; And
One second transmission gate, it transmits an output of this first latch unit, as this home address in order to the startup in response to a corresponding pipeline output signal.
9. semiconductor storage as claimed in claim 8, wherein this pipeline latch control module also comprises:
One pipeline output drive signal generation unit, it is through being configured to produce a pipeline output drive signal in response to the startup of this internal command; An and pipeline output signal generation unit; It exports signals through being configured to produce a plurality of pipelines in response to this pipeline output drive signal; And wherein; This initialization unit also utilizes this to reset signal during the initial operation or when this semiconductor storage is carried out read operation under the situation that does not have an additional delay, this pipeline output signal generation unit of initialization.
10. semiconductor storage as claimed in claim 9, wherein this pipeline input drive signal generation unit comprises one first OR-gate, this first OR-gate logical groups is should external read order and this external write order.
11. like the semiconductor storage of claim 10, wherein this pipeline output drive signal generation unit comprises one second OR-gate, this second OR-gate logical groups is should internal read order and this inside write order.
12. like the semiconductor storage of claim 11, wherein when one initially resets signal and is activated or when one zero additional delay signals were in state of activation and and write status signal and cancelled, this reseted signal this initialization unit output.
13. like the semiconductor storage of claim 12, wherein this initialization unit comprises the phase inverter of the even number that connects of being one another in series, said phase inverter receives this and initially resets signal as an input and export this and reset signal.
14. like the semiconductor storage of claim 12, wherein this initialization unit comprises:
One second phase inverter, it is used to make this to write the status signal anti-phase;
One AND gate, it is used for logical groups should an output of second phase inverter and this zero additional delay signal; And
One the 3rd OR-gate, it is used for logical groups should an output of AND gate is initially reseted signal with this, resets signal to export this.
15. like the semiconductor storage of claim 12, wherein this initialization unit comprises:
One second phase inverter, it is used to make this to write the status signal anti-phase;
One AND gate, it is used for logical groups should an output of second phase inverter, this zero an additional delay signal and a test mode signal that during a test mode operation, starts; And
One the 3rd OR-gate, it is used for logical groups should an output of AND gate is initially reseted signal with this, resets signal to export this.
16. like the semiconductor storage of claim 11, wherein this pipeline input signal generation unit comprises:
One pipeline input shift unit, it is through being configured in response to this pipeline input drive signal a plurality of pipeline input delay signals of output through launching in proper order; And
One pipeline input driver element, it exports said pipeline input delay signal as said pipeline input signal through being configured in response to this pipeline input drive signal.
17. like the semiconductor storage of claim 16, wherein this pipeline output signal generation unit comprises:
One pipeline output shift unit, it is through being configured in response to this pipeline output drive signal a plurality of pipeline output delay signals of output through launching in proper order; And
One pipeline output driver element, it exports said pipeline output delay signal as said pipeline output signal through being configured in response to this pipeline output drive signal.
18. like the semiconductor storage of claim 17, wherein this pipeline input shift unit comprises a plurality of triggers of reseting that this is one another in series and connects, and SFF.
19. semiconductor storage like claim 18; Wherein when this is reseted signal and is cancelled; Said each this pipeline input drive signal of reseting in the trigger in response to this second logic level; Transmit an input signal via its second lead-out terminal, and in response to this pipeline input drive signal of this first logic level, via its this input signal of first lead-out terminal transmission.
20. semiconductor storage like claim 19; Wherein this SFF is in response to this pipeline input drive signal of this second logic level; Transmit an input signal via its second lead-out terminal; And in response to this pipeline input drive signal of this first logic level, via its this input signal of first lead-out terminal transmission.
21. like the semiconductor storage of claim 20, wherein this SFF comprises:
One the 5th transmission gate, it transmits this input signal in order to this pipeline input drive signal in response to this second logic level;
One quad latch unit, it is used for reseting the output that signal latchs the 5th transmission gate when cancelling at this;
One the 3rd phase inverter, it is used to make an output anti-phase of this quad latch unit, and via this second terminal output;
One the 6th transmission gate, it transmits this output of this quad latch unit in order to this pipeline input drive signal in response to this first logic level; And
One the 5th latch unit, it is used for reseting the output that signal latched and exported the 6th transmission gate when cancelling at this.
22. like the semiconductor storage of claim 21, wherein this second latch unit comprises:
One the 4th phase inverter, it is used to make this to reset signal inversion;
One first NOT-AND gate, it is used for logical groups should an output of the 4th phase inverter and this output of the 3rd transmission gate; And
One the 5th phase inverter, it is used to make an output anti-phase of this first NOT-AND gate, and wherein a lead-out terminal of the 5th phase inverter is connected to a lead-out terminal of the 3rd transmission gate.
23. like the semiconductor storage of claim 22, wherein the 3rd latch unit comprises:
One first NOR gate, it is used for logical groups should reset signal and this output of the 4th transmission gate; And
One hex inverter, it is used to make an output anti-phase of this first NOR gate, and wherein a lead-out terminal of this hex inverter is connected to a lead-out terminal of the 4th transmission gate.
24. like the semiconductor storage of claim 23, wherein this quad latch unit comprises:
One second NOR gate, it is used for logical groups should reset signal and this output of the 5th transmission gate; And
One the 7th phase inverter, it is used to make an output anti-phase of this second NOR gate, and wherein a lead-out terminal of the 7th phase inverter is connected to a lead-out terminal of the 5th transmission gate.
25. like the semiconductor storage of claim 24, wherein the 5th latch unit comprises:
One the 8th phase inverter, it is used to make this to reset signal inversion;
One second NOT-AND gate, it is used for logical groups should an output of the 8th phase inverter and this output of the 6th transmission gate; And
One the 9th phase inverter, it is used to make an output anti-phase of this second NOT-AND gate, and wherein a lead-out terminal of the 9th phase inverter is connected to a lead-out terminal of the 6th transmission gate.
26. like the semiconductor storage of claim 25, wherein this pipeline output shift unit comprises:
The a plurality of triggers of reseting that are one another in series and connect are saidly reseted in the trigger each in response to this pipeline output drive signal, via the corresponding pipeline output delay signal of its second lead-out terminal output one; And
One SFF; It receives this that be arranged in these a plurality of places, position, second end that reset trigger via its input terminal and resets one first output of trigger; And this SFF first inputs to it this and a plurality ofly resets in the trigger this and first reset trigger
The wherein said trigger of reseting is reseted the startup of signal in response to this, and its first and second output is reset to this second logic level, and this SFF resets the startup of signal in response to this, and its first and second output is set at this first logic level.
27. semiconductor storage like claim 26; Wherein when this is reseted signal and is cancelled; Said each this pipeline output drive signal of reseting in the trigger in response to this second logic level; Transmit an input signal via its second lead-out terminal, and in response to this pipeline output drive signal of this first logic level, via its this input signal of first lead-out terminal transmission.
28. semiconductor storage like claim 27; Wherein this SFF in this pipeline output shift unit is in response to this pipeline output drive signal of this second logic level; Transmit an input signal via its second lead-out terminal; And in response to this pipeline output drive signal of this first logic level, via its this input signal of first lead-out terminal transmission.
29. a method that is used in generation one home address in the semiconductor storage, it comprises:
In response to the input of an external command, an external address is latched in a pipeline latch, and produce the external address that latchs;
Through postponing this external command, produce an internal command according to a predetermined time-delay;
In response to the startup of this internal command, export this through the external address that latchs as this home address; And
Select one in this home address and this external address wherein when this semiconductor device is not carried out write operation under the situation that does not have additional delay, to export this external address, otherwise export this home address as column address,
Wherein latching this external address comprises:
Produce a pipeline input drive signal in response to the input of this external command;
The a plurality of triggers of reseting that connect by being one another in series are reseted the pipeline input delay signal of second lead-out terminal output, one correspondence of trigger in response to this pipeline input drive signal via each;
Through logical groups should pipeline input drive signal and said pipeline input delay signal produce a plurality of pipeline input signals; And
In response to the startup of the corresponding pipeline input signal of one in the said pipeline input signal, this external address is latched in this pipeline latch,
Wherein, Said a plurality of this one first output of reseting trigger of reseting the end position place of second in the trigger is received by the input terminal of a SFF; And this SFF provides its first output to this and a plurality ofly resets in the trigger this and first reset trigger; Said reset trigger in response to one reset signal startup, its first and second output is reset to one second logic level, and this SFF is reseted the startup of signal in response to this; Its first and second output is set at one first logic level, saidly comprises via each second lead-out terminal output, one corresponding pipeline input delay signal of reseting trigger
Utilize one the 3rd transmission gate to transmit this input signal in response to this pipeline input drive signal of this second logic level;
Utilize one second latch unit to reset the output that signal latchs the 3rd transmission gate when cancelling at this;
Utilize one second phase inverter to make one of this second latch unit export anti-phase, and via this second lead-out terminal output;
Utilize one the 4th transmission gate this pipeline input drive signal, transmit this output of this second latch unit in response to this first logic level; And
Utilize one the 3rd latch unit to reset the output that signal latchs the 4th transmission gate when being cancelled, and output should be through latched signal as this second output at this.
30. like the method for claim 29, wherein this time-delay comprises an additional delay and column address strobe CAS time-delay.
31., wherein export this home address and comprise like the method for claim 30:
Produce a pipeline output drive signal in response to the startup of this internal command;
Produce a plurality of pipeline output delay signals in response to this pipeline output drive signal;
Produce a plurality of pipeline output signals through cushioning said pipeline output delay signal; And
In response to the startup that the corresponding pipeline in the said pipeline output signal is exported signal, output latch this home address in this pipeline latch.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR90891/05 | 2005-09-29 | ||
| KR20050090891 | 2005-09-29 | ||
| KR1020050134002A KR100670729B1 (en) | 2005-09-29 | 2005-12-29 | Internal address generator of semiconductor memory device |
| KR134002/05 | 2005-12-29 |
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| Publication Number | Publication Date |
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| CN1941198A CN1941198A (en) | 2007-04-04 |
| CN1941198B true CN1941198B (en) | 2012-06-27 |
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| CN2006101412038A Expired - Fee Related CN1941198B (en) | 2005-09-29 | 2006-09-28 | Internal signal generator for use in semiconductor memory device |
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| KR (1) | KR100670729B1 (en) |
| CN (1) | CN1941198B (en) |
| TW (1) | TWI320188B (en) |
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| KR100931024B1 (en) * | 2008-09-19 | 2009-12-11 | 주식회사 하이닉스반도체 | A test mode signal generator for semiconductor memory and a method of generation of the test mode signal |
| KR20130119170A (en) | 2012-04-23 | 2013-10-31 | 에스케이하이닉스 주식회사 | Pipe register circuit and semiconductor memory apparatus comprising the same |
| KR20150130065A (en) * | 2014-05-13 | 2015-11-23 | 에스케이하이닉스 주식회사 | Semiconductor Memory Apparatus |
| KR20180126321A (en) * | 2017-05-17 | 2018-11-27 | 에스케이하이닉스 주식회사 | Memory device and operating method thereof |
| KR102508309B1 (en) * | 2018-04-23 | 2023-03-10 | 에스케이하이닉스 주식회사 | Pipe latch, semiconductor apparatus and semiconductor system using the same |
| CN112735493B (en) * | 2019-10-28 | 2023-06-13 | 敦泰电子股份有限公司 | Static random access memory system and data read-write method thereof |
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| US5337168A (en) * | 1992-03-10 | 1994-08-09 | Ricoh Company, Ltd. | Image data processing apparatus for locating pixel having maximum coincidence count in input image data |
| US5767718A (en) * | 1996-09-04 | 1998-06-16 | Etron Technology, Inc. | High speed conditional synchronous one shot circuit |
| US6366515B2 (en) * | 2000-06-21 | 2002-04-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
| US6711084B2 (en) * | 2002-01-28 | 2004-03-23 | Renesas Technology Corp. | Semiconductor device capable of reliable power-on reset |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010001968A (en) * | 1999-06-10 | 2001-01-05 | 윤종용 | Address buffer of semiconductor memory device |
| JP4345204B2 (en) | 2000-07-04 | 2009-10-14 | エルピーダメモリ株式会社 | Semiconductor memory device |
-
2005
- 2005-12-29 KR KR1020050134002A patent/KR100670729B1/en not_active IP Right Cessation
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2006
- 2006-06-30 TW TW095123955A patent/TWI320188B/en not_active IP Right Cessation
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5337168A (en) * | 1992-03-10 | 1994-08-09 | Ricoh Company, Ltd. | Image data processing apparatus for locating pixel having maximum coincidence count in input image data |
| US5767718A (en) * | 1996-09-04 | 1998-06-16 | Etron Technology, Inc. | High speed conditional synchronous one shot circuit |
| US6366515B2 (en) * | 2000-06-21 | 2002-04-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
| US6711084B2 (en) * | 2002-01-28 | 2004-03-23 | Renesas Technology Corp. | Semiconductor device capable of reliable power-on reset |
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| CN1941198A (en) | 2007-04-04 |
| TWI320188B (en) | 2010-02-01 |
| KR100670729B1 (en) | 2007-01-17 |
| TW200717539A (en) | 2007-05-01 |
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