CN1940130A - Production of silicon-nitride layer and self-aligning metal silicide layer - Google Patents
Production of silicon-nitride layer and self-aligning metal silicide layer Download PDFInfo
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- CN1940130A CN1940130A CN 200510107199 CN200510107199A CN1940130A CN 1940130 A CN1940130 A CN 1940130A CN 200510107199 CN200510107199 CN 200510107199 CN 200510107199 A CN200510107199 A CN 200510107199A CN 1940130 A CN1940130 A CN 1940130A
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Abstract
A manufacture method of nitride silicon layer, it takes gaseous mixture as the reaction gas to produce the nitride silicon layer; the gaseous mixture includes silicon hydride (SiH4), nitrogen (N2) and micro ammonia (NH3). Because the said gaseous mixture only provides micro ammonia even whose flux is 0, therefore it can reduce the etching speed of the nitride silicon layer greatly; keep the nitride silicon layer from damaging in the process of etching.
Description
Technical field
The present invention relates to a kind of silicon nitride (silicon nitride, Si
xN
y) layer making method, relate in particular to a kind of making method that can significantly reduce the silicon nitride layer of etching speed (etching rate) and be applied to the making method of self-aligned metal silicate (metal self-aligned silicide, metal salicide) layer with it.
Background technology
Silicon nitride be a kind of in semiconductor technology (semiconductor process) common dielectric material.Its main application is the etching mask (etching mask) as silicon oxide layer; and be difficult for advantage by oxygen permeated by silicon nitride layer; this layer mask can also be as carrying out zone of oxidation when making; prevent the mask layer that the active area of chip surface suffers oxidation; except this is used; because silicon nitride layer is difficult for being permeated by aqueous vapor, so be widely used protective layer as semiconducter device.Also because silicon nitride layer has much more so purposes, so silicon nitride layer occupies a consequence very in semiconductor technology.With present manufacturing process, normally (chemical vapordeposition CVD) makes silicon nitride layer with chemical vapour deposition.
But at present the etching speed for silicon nitride layer but can't reduce effectively, so that deal with the infringement to silicon nitride layer of subsequent etch process or cleaning process.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of making method of silicon nitride layer, can reduce the etching speed of silicon nitride layer, make this silicon nitride layer can keep out the infringement that etching process causes.
A further object of the present invention provides a kind of making method of self-aligned metal silicate layer, so that the blocking layer of the self-aligned metal silicate with low etching speed to be provided.
The present invention proposes a kind of making method of silicon nitride layer, is to utilize a mixed gas (mixed gas) as the reactant gases (reacting gas) of making silicon nitride layer, and wherein mixed gas comprises silane (SiH
4), nitrogen (N
2) and micro-ammonia (NH
3).
According to the making method of the described silicon nitride layer of embodiments of the present invention, the flow of the ammonia in the above-mentioned mixed gas (flow rate) is lower than 0.06SLM (standard liters/minute), and the flow of preferred ammonia is 0.
According to the making method of the described silicon nitride layer of embodiments of the present invention, the flow of the silane in the above-mentioned mixed gas is about 0.05SLM～0.1SLM, and the flow of the nitrogen in the mixed gas is about 1SLM～5SLM.
According to the making method of the described silicon nitride layer of embodiments of the present invention, the technology of above-mentioned making silicon nitride layer comprise plasma enhanced chemical vapor deposition (plasma enhanced chemicalvapor deposition, PECVD).
The present invention reintroduces a kind of making method of self-aligned metal silicate layer, it comprises provides a substrate (substrate), this substrate is divided into first district and second district, and has been formed with a plurality of semiconducter device (semiconductor devices) in first district and second district.Then, utilize a mixed gas as reactant gases, form a self-aligned metal silicate blocking layer (salicide block layer) on substrate and semiconductor device surface, wherein mixed gas comprises the ammonia of silane, nitrogen and trace.Then, remove the self-aligned metal silicate blocking layer in first district, carry out an autoregistration metal silication (metalself-aligned silicidation) technology again, to form a self-aligned metal silicate floor on the semiconducter device in first district.
According to the making method of the described self-aligned metal silicate layer of embodiments of the present invention, the flow of the ammonia in the above-mentioned mixed gas is lower than 0.06SLM, and the flow of preferred ammonia is 0.
According to the making method of the described self-aligned metal silicate layer of embodiments of the present invention, the flow of the silane in the above-mentioned mixed gas is about 0.05SLM～0.1SLM, and the flow of the nitrogen in the mixed gas is about 1SLM～5SLM.
Making method according to the described self-aligned metal silicate layer of embodiments of the present invention, the method on above-mentioned formation self-aligned metal silicate blocking layer comprises plasma enhanced chemical vapor deposition, and the time on formation self-aligned metal silicate blocking layer is 3～4 seconds.
According to the making method of the described self-aligned metal silicate layer of embodiments of the present invention, above-mentioned self-aligned metal silicate blocking layer is a silicon nitride layer.
Making method according to the described self-aligned metal silicate layer of embodiments of the present invention, above-mentioned self-aligned metal silicate technology comprises prior to forming a metal level on the substrate, cover substrate and semiconductor device surface in first district, and cover the self-aligned metal silicate blocking layer in second district.Then, carry out a thermal process,, again the unreacted metal layer is removed so that the pasc reaction in metal level and substrate and the semiconducter device forms the self-aligned metal silicate layer.
The present invention so can significantly reduce the etching speed of formed silicon nitride layer, makes this silicon nitride layer can keep out the infringement that etching process causes because it is 0 ammonia that trace or even flow only are provided in above-mentioned mixed gas.When for example such silicon nitride layer being applied in passivation layer (passivationlayer), self-aligned metal silicate blocking layer or etch stop (etching stop layer), can prevent the infringement of the silicon nitride layer that the over etching (over-etching) after the subsequent etch process causes effectively.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment more cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the making processes block diagram according to the silicon nitride layer of the first embodiment of the present invention;
Fig. 2 A to Fig. 2 D is the manufacturing process flow sectional view according to the self-aligned metal silicate layer of the second embodiment of the present invention;
Fig. 3 is the sectional structure chart of the semiconductor subassembly of another example of the present invention.
The main element nomenclature
100～120: step 200,300: substrate
202a: the first district 202b: second district
204: shallow slot isolation structure 206: grid
208: source electrode and drain electrode 210a, 210b and 210c: semiconducter device
212:N type well 214:P type well
216: gate oxide 218: spaced walls
219: shallow doped-drain 220: mixed gas
222: the self-aligned metal silicate blocking layer
224,304: metal level 226: thermal process
228: self-aligned metal silicate layer 302: medium layer
306: etch stop 310: opening
Embodiment
Fig. 1 is the making processes block diagram according to the silicon nitride layer of the first embodiment of the present invention.
See also Fig. 1, making method in this embodiment is carry out step 100 earlier, and a substrate (substrate) is provided, and according to the function of formed silicon nitride layer, can form the rete of various semiconductor subassemblies or various materials earlier on this substrate.For instance, (inter-layer dielectric ILD), then forms transistor (transistor) earlier on substrate if silicon nitride layer is used as interlayer dielectric layer; If silicon nitride layer is as etch stop, then can on substrate, form rete earlier as metal or other dielectric material.Then, carry out step 110, utilize a mixed gas (mixed gas) as the reactant gases (reacting gas) of making silicon nitride layer, and mixed gas comprises silane (SiH
4), nitrogen (N
2) and micro-ammonia (NH
3).And the flow of the ammonia in the mixed gas (flow rate) is such as the standard liters that is lower than per minute 0.06 (standard-liters/minute, unit symbol are SLM), and the flow of preferred ammonia is 0.In addition, the silane in the above-mentioned mixed gas and the flow of nitrogen can be with reference to prior aries, and for example the flow of silane is about 0.05SLM～0.1SLM, and the flow of the nitrogen in the mixed gas is about 1SLM～5SLM.Then, carry out step 120, makes silicon nitride layer, and the technology of making comprise plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD).
Below table one be only to change the flow of the ammonia in the aforementioned mixed gas and the RCA etching speed (etching rate) of the silicon nitride layer that obtains relatively, wherein RCA is a kind of use ammonium hydroxide (ammonium hydroxide, NH
4OH) and hydrogen peroxide (hydrogen peroxide, H
2O
2) as the matting of etching solution.And the thickness of resulting silicon nitride layer is about 340 dusts.
Table one
| The flow of ammonia (SLM) | RCA wet corrosion speed (dust/minute) |
| 0.1 | 77 |
| 0.18 | 63 |
| 0.06 | 60 |
| 0 | 33 |
As shown in Table 1, along with the minimizing of the flow of ammonia, the RCA etching speed of silicon nitride layer can significantly reduce really.
The second embodiment of the present invention relates to a kind of manufacturing process of self-aligned metal silicate layer, shown in Fig. 2 A to Fig. 2 D, is its flow process sectional view.
See also Fig. 2 A, a substrate 200 is provided earlier, this substrate 200 is divided into the first district 202a and the second district 202b, and has been formed with several semiconducter device (devices) 210a, 210b, 210c in the first district 202a and the second district 202b.With this figure is example, each semiconducter device 210a, 210b and 210c comprise grid 206 and source electrode and drain electrode 208, and shallow slot isolation structure (shallow trench isolation, STI) 204 that isolation of semiconductor devices 210a, 210b and 210c are arranged in the substrate 200.Moreover, semiconducter device 210a for example is metal-oxide semiconductor (MOS) (the p-type metal oxidesemiconductor of P type, PMOS), semiconducter device 210b for example is the metal-oxide semiconductor (MOS) (NMOS) of N type, at the semiconducter device 210c of the second district 202b then for example is static discharge (electrostatic discharge, ESD) device, so in the substrate 200 of semiconducter device 210a, have N type well (N-well) 212, and in the substrate 200 of semiconducter device 210b and 210c, have p type wells (P-well) 214.In addition, semiconducter device 210a, 210b and 210c generally also be included in the gate oxide (gate oxide layer) 216 of 200 of grid 206 and substrates, in the spaced walls (spacer) 218 of grid 206 sidewalls be arranged in lightly doped drain (lightly dopeddrain, LDD) 219 of the substrate 200 of grid 206 both sides.
Then, see also Fig. 2 B, utilize a mixed gas 220 as reactant gases, on substrate 200 and semiconducter device 210a, 210b and 210c surface, form a self-aligned metal silicate blocking layer (salicide block layer) 222, to stop follow-up formed self-aligned metal silicate, wherein mixed gas 220 comprises the ammonia of silane, nitrogen and trace, and wherein self-aligned metal silicate blocking layer 222 for example is a silicon nitride layer.And the flow of the ammonia in the above-mentioned mixed gas 220 for example is lower than 0.06SLM, and the flow of preferred ammonia is 0.In addition, as described in first embodiment, the throughput ratio of the silane in the above-mentioned mixed gas 220 in this way about the flow of 0.05SLM～0.1SLM and nitrogen about 1SLM～5SLM.And the method on above-mentioned formation self-aligned metal silicate blocking layer 222 for example comprises plasma enhanced chemical vapor deposition or other suitable manufacturing process, and the time that forms self-aligned metal silicate blocking layer 222 can be decided according to the predetermined thickness that forms, such as being 3～4 seconds.
Then, see also Fig. 2 C, remove the self-aligned metal silicate blocking layer 222 in the first district 202a.Come again, carry out an autoregistration metal silication (self-aligned silicide, salicide) technology, and this technology is such as being prior to forming a metal level 224 on the substrate 200, cover interior substrate 200 of the first district 202a and the surface of semiconducter device 210a and 210b, and cover the self-aligned metal silicate blocking layer 222 in the second district 202b.
Then, see also Fig. 2 D, carry out a thermal process (thermal process) 226, so that the pasc reaction among metal level 224 and substrate 220 and semiconducter device 210a and the 210b forms self-aligned metal silicate layer 228, for second embodiment, self-aligned metal silicate layer 228 can be formed on grid 206 and source electrode and drain electrode 208 surfaces of semiconducter device 210a and 210b; And the semiconducter device 210c in the second district 202b is because be coated with self-aligned metal silicate blocking layer 222, so can't form the self-aligned metal silicate layer.Afterwards, can remove unreacted metal layer 224.
Because the self-aligned metal silicate blocking layer 222 of the foregoing description only provides trace or even flow when making be that 0 ammonia is in aforementioned mixed gas; so can significantly reduce the etching speed on formed self-aligned metal silicate blocking layer 222, and the semiconducter device 210c under when removing unreacted metal layer 224, protecting.
In addition, the present invention also can be applicable in interconnection line (interconnect) structure, is the sectional structure chart of the semiconductor subassembly of another example of the present invention as Fig. 3.
See also Fig. 3, in a dual damascene (dual damascene) structure, comprise substrate 300, medium layer 302, metal level 304 and etch stop 306 usually.Wherein, medium layer 302 is to change mutually layer by layer on substrate 300 with etch stop 306, and metal level 304 just is formed in the opening 310 in medium layer 302 and the etch stop 306.Etch stop 306 in this embodiment be exactly utilize among preceding two embodiment provide trace or even flow be 0 ammonia in mixed gas, and the silicon nitride layer of making.
Comprehensive the above, characteristics of the present invention are that trace or even flow only are provided in above-mentioned mixed gas is 0 ammonia, make the etching speed of formed silicon nitride layer significantly to reduce.Thus, this silicon nitride layer just can be kept out the infringement that etching process causes.
Though with the preferred embodiment explanation as above, it is not to be used to limit the present invention in the present invention, any those skilled in the art under the premise without departing from the spirit and scope of the present invention, can do various renewals and improvement.But protection scope of the present invention should be with being as the criterion that claim was defined.
Claims (15)
1. the making method of a silicon nitride layer is to utilize the reactant gases of a mixed gas as making one silicon nitride layer, wherein:
This mixed gas comprises the ammonia of silane, nitrogen and trace.
2. the making method of silicon nitride layer according to claim 1, wherein: the flow of the ammonia in this mixed gas is lower than 0.06SLM.
3. the making method of silicon nitride layer according to claim 2, wherein: the flow of the ammonia in this mixed gas is 0.
4. the making method of silicon nitride layer according to claim 1, wherein: the flow of the silane in this mixed gas is at 0.05SLM～0.1SLM.
5. the making method of silicon nitride layer according to claim 1, wherein: the flow of the nitrogen in this mixed gas is at 1SLM～5SLM.
6. the making method of silicon nitride layer according to claim 1, wherein: the technology of making this silicon nitride layer comprises plasma enhanced chemical vapor deposition.
7. the making method of a self-aligned metal silicate layer comprises:
One substrate is provided, and this substrate is divided into first district and second district, and has been formed with several semiconducter device in this first district and this second district;
Utilize a mixed gas as reactant gases, form a self-aligned metal silicate blocking layer on this substrate and those semiconductor device surfaces, wherein this mixed gas comprises the ammonia of silane, nitrogen and trace;
Remove this self-aligned metal silicate blocking layer in this first district; And
Carry out an autoregistration silication technique for metal, to form a self-aligned metal silicate floor on those semiconducter device in this first district.
8. the making method of self-aligned metal silicate layer according to claim 7, wherein: the flow of the ammonia in this mixed gas is lower than 0.06SLM.
9. the making method of self-aligned metal silicate layer according to claim 8, wherein: the flow of the ammonia in this mixed gas is 0.
10. the making method of self-aligned metal silicate layer according to claim 7, wherein: the flow of the silane in this mixed gas is at 0.05SLM～0.1SLM.
11. the making method of self-aligned metal silicate layer according to claim 7, wherein: the flow of the nitrogen in this mixed gas is at 1SLM～5SLM.
12. the making method of self-aligned metal silicate layer according to claim 7, wherein: the method that forms this self-aligned metal silicate blocking layer comprises plasma enhanced chemical vapor deposition.
13. the making method of self-aligned metal silicate layer according to claim 12, wherein: the time that forms this self-aligned metal silicate blocking layer is 3～4 seconds.
14. the making method of self-aligned metal silicate layer according to claim 7, wherein: this self-aligned metal silicate blocking layer is a silicon nitride layer.
15. the making method of self-aligned metal silicate layer according to claim 7, wherein: this self-aligned metal silicate technology comprises:
On this substrate, form a metal level, cover this substrate and those semiconductor device surfaces in this first district, and cover this self-aligned metal silicate blocking layer in this second district;
Carry out a thermal process, so that the pasc reaction in this metal level and this substrate and those semiconducter device forms this self-aligned metal silicate layer; And
Remove unreacted this metal level.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510107199 CN1940130A (en) | 2005-09-28 | 2005-09-28 | Production of silicon-nitride layer and self-aligning metal silicide layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510107199 CN1940130A (en) | 2005-09-28 | 2005-09-28 | Production of silicon-nitride layer and self-aligning metal silicide layer |
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| CN1940130A true CN1940130A (en) | 2007-04-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101451272B (en) * | 2007-11-30 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Silicon nitride production method capable of reducing cavity formation probability in metal front medium layer |
| CN115602542A (en) * | 2022-01-29 | 2023-01-13 | 和舰芯片制造（苏州）股份有限公司（Cn） | Manufacturing method of semiconductor SAB capable of preventing electric leakage and semiconductor device |
-
2005
- 2005-09-28 CN CN 200510107199 patent/CN1940130A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101451272B (en) * | 2007-11-30 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Silicon nitride production method capable of reducing cavity formation probability in metal front medium layer |
| CN115602542A (en) * | 2022-01-29 | 2023-01-13 | 和舰芯片制造（苏州）股份有限公司（Cn） | Manufacturing method of semiconductor SAB capable of preventing electric leakage and semiconductor device |
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