CN1929116A - Integrated circuit including silicon wafer with annealed glass paste - Google Patents
Integrated circuit including silicon wafer with annealed glass paste Download PDFInfo
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- CN1929116A CN1929116A CN 200610126947 CN200610126947A CN1929116A CN 1929116 A CN1929116 A CN 1929116A CN 200610126947 CN200610126947 CN 200610126947 CN 200610126947 A CN200610126947 A CN 200610126947A CN 1929116 A CN1929116 A CN 1929116A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
An integrated circuit (IC) package comprises an IC wafer and an annealed glass paste (AGP) layer that is arranged adjacent to the IC wafer. A molding material encapsulates at least part of the IC wafer and the AGP layer. The AGP layer is arranged on at least one side of the IC wafer. The AGP layer is arranged on a plurality of disjoint areas on at least one side of the IC wafer. A layer of a conductive material is arranged on a portion of the AGP layer.
Description
Technical field
The present invention relates to integrated circuit, more specifically, relate to the integrated circuit of on silicon wafer, having arranged the annealed glass slurry.
Background technology
In a variety of electronic equipments (for example cell phone and other handheld devices), all need accurate frequency reference.Crystal oscillator is used to provide accurate frequency reference usually in these electronic equipments.But crystal oscillator has some latent defects, comprises that volume is big, frangible and expensive.In addition, the size of crystal oscillator is relevant with resonance frequency with cost, thereby when frequency increased, size reduced, and cost and fragility may increase fast.Along with the size of electronic equipment constantly reduces, the use of crystal oscillator is owing to increasing problem appears in the restriction of its size, fragility and cost.
Semiconductor oscillistor is a kind of relatively poor alternative to crystal oscillator, and generally is not suitable for use in accurate frequency reference, and this is because the variation of the frequency of oscillation of semiconductor oscillistor is excessive, especially is easy to change with variation of temperature.
Summary of the invention
According to an aspect of the present invention, provide a kind of integrated circuit encapsulation, having comprised: integrated circuit (IC) wafer; And with the annealed glass of the adjacent layout of this IC wafer slurry (AGP) layer.
According to a further aspect in the invention, provide another kind of integrated circuit encapsulation, having comprised: integrated circuit (IC) wafer; First with the adjacent layout of this IC wafer; With the adjacent layout of this IC wafer and with the isolated second portion of described first, wherein said first and second parts comprise at least a in annealed glass slurry and the epoxy; And with the layer of the adjacent layout of described first and second parts, make to form the air gap between described layer, described first and second parts and the described IC wafer.
According to another aspect of the invention, provide another integrated circuit encapsulation, having comprised: integrated circuit (IC) wafer that comprises circuit; And with the C shape layer of the adjacent layout of substrate, make to form the air gap between the circuit of described C shape layer and described IC wafer.
Description of drawings
Fig. 1 is the block diagram that an aspect of crystal oscillator emulator is shown;
Fig. 2 is the table that the relation between temperature and the correction factor is shown;
Fig. 3 is the figure that the relation between temperature and the correction factor is shown;
Fig. 4 is the block diagram that an aspect of crystal oscillator emulator is shown;
Fig. 5 is the two dimension view of an aspect that is connected to the crystal oscillator emulator of external impedance;
Fig. 6 is the detailed diagram of an aspect that is connected to the crystal oscillator emulator of external impedance;
Fig. 7 A and Fig. 7 B are the figure that the relation between external impedance value and the digital value is shown;
Fig. 8 is the block diagram of an aspect that is used to generate the oscillator assembly of the output with periodic waveform;
Fig. 9 is the block diagram of an aspect of spread spectrum generator;
Figure 10 is the flow chart that is used for the operation of emulation crystal oscillator;
Figure 11 is the block diagram of an aspect of low-power oscillator;
Figure 12 is the block diagram on the other hand of low-power oscillator;
Figure 13 is the functional block diagram of integrated circuit of crystal oscillator emulator that comprises one or more circuit and be used to generate the clock signal of these one or more circuit;
Figure 14 is the functional block diagram of integrated circuit of crystal oscillator emulator that comprises processor and be used to generate the clock signal of this processor;
Figure 15 comprises processor and is used to generate the clock signal of this processor and adopts external module that the functional block diagram of integrated circuit of the crystal oscillator emulator of clock rate is set;
Figure 16 is the functional block diagram of integrated circuit of Clock dividers that comprises one or more circuit, crystal oscillator emulator and be used to generate the clock signal of one or more other clock frequencies;
Figure 17 is the functional block diagram of integrated circuit of Clock dividers that comprises processor, one or more circuit, crystal oscillator emulator and be used to generate the clock signal of other clock frequencies;
Figure 18 is the functional block diagram of integrated circuit that comprises the crystal oscillator emulator of processor, graphic process unit, one or more circuit, memory and generation clock signal;
Figure 19 is the functional block diagram of integrated circuit that comprises the low-power oscillator of processor and Figure 11;
Figure 20 is the functional block diagram that the integrated circuit in the encapsulating material that is encapsulated in prior art is shown;
Figure 21 is the functional block diagram that the integrated circuit of the sheet semiconductor-on-insulator oscillator that has temperature-compensating is shown, and this integrated circuit is encapsulated in according in the encapsulating material with low dielectric absorption of the present invention;
Figure 22 illustrates in greater detail a kind of exemplary implementation of the integrated circuit encapsulation of Figure 21;
Figure 23 is the side cross-sectional view that comprises another integrated circuit encapsulation of sheet semiconductor-on-insulator oscillator according to of the present invention;
Figure 24 is the side cross-sectional view that comprises another integrated circuit encapsulation of sheet semiconductor-on-insulator oscillator according to of the present invention;
Figure 25 is the plane section figure that illustrates in greater detail the integrated circuit encapsulation of Figure 24;
Figure 26 is the functional block diagram that illustrates based on the capacitor of tuning semiconductor-on-insulator oscillator of temperature-compensating;
Figure 27 is the functional block diagram that comprises the fractional phase locked loop (PLL) of temperature-compensating input;
Figure 28 is the functional block diagram that comprises the Delta-Sigma fractional phase locked loop of temperature-compensating input;
Figure 29 illustrates to be used to measure sample calibration point and to use the linearity curve fitting algorithm to generate the flow chart of the step of the calibration data between the sample calibration point;
Figure 30 illustrates to be used to measure sample calibration point and to use the curve fitting algorithm of high-order more to generate the flow chart of the step of the calibration data between the sample calibration point;
Figure 31 A is the functional block diagram of hard disk drive;
Figure 31 B is the functional block diagram of digital versatile disc (DVD);
Figure 31 C is the functional block diagram of high definition television;
Figure 31 D is the functional block diagram of vehicle control system;
Figure 31 E is cellular functional block diagram;
Figure 31 F is the functional block diagram of set-top box;
Figure 31 G is the functional block diagram of media player;
Figure 32 A is the side cross-sectional view that comprises another integrated circuit encapsulation of annealed glass slurry at least a portion that is formed on silicon wafer and/or epoxy layer;
Figure 32 B be comprise annealed glass slurry and/or the epoxy layer at least a portion that is formed on silicon wafer and be formed on annealed glass slurry and/or at least a portion of epoxy layer on the side cross-sectional view of another integrated circuit encapsulation of conductive material layer;
Figure 32 C is the side cross-sectional view that comprises another integrated circuit encapsulation of the isolated annealed glass slurry layer on the selected portion that is formed on silicon wafer;
Figure 32 D is the side cross-sectional view that comprises another integrated circuit encapsulation of isolated annealed glass slurry on the selected portion that is formed on silicon wafer and/or epoxy layer and conductive material layer;
Figure 33 A is the side cross-sectional view that comprises another integrated circuit encapsulation of the annealed glass slurry adjacent with the circuit of silicon wafer and/or epoxy layer and conductive material layer;
Figure 33 B is the side cross-sectional view that comprises another integrated circuit encapsulation of the annealed glass slurry adjacent with the oscillator of silicon wafer and/or epoxy layer and conductive material layer;
Figure 33 C is the side cross-sectional view that comprises another integrated circuit encapsulation of the annealed glass slurry adjacent with the inductor of silicon wafer and/or epoxy layer and conductive material layer;
Figure 33 D is the side cross-sectional view of another integrated circuit encapsulation of the adjacent annealed glass slurry of the inductor in the pierce circuit that comprises with silicon wafer and/or epoxy layer and conductive material layer;
Figure 34 A is the side cross-sectional view that comprises another integrated circuit encapsulation of the glass of setting up the air gap or silicon layer and annealed glass slurry and/or epoxy moieties to Figure 34 D;
Figure 35 A is the side cross-sectional view that comprises another integrated circuit encapsulation of the C shape glass of setting up the air gap or silicon layer to Figure 35 B;
Figure 36 A is the side cross-sectional view that comprises the wafer of a plurality of integrated circuit encapsulation that comprise the glass of setting up the air gap or silicon layer and annealed glass slurry and/or epoxy moieties to Figure 36 C;
Figure 37 A is to comprise that the annealed glass that has applied electric conducting material is starched and/or the side cross-sectional view of the integrated circuit encapsulation of epoxy moieties to Figure 37 B; And
Figure 38 illustrates and is used for the illustrative steps of shop drawings 32A to the method for the integrated circuit encapsulation of Figure 32 D.
Similar label indication like in each accompanying drawing.
Embodiment
Fig. 1 illustrates an aspect of the crystal oscillator emulator 10 that is used to generate the output signal 12 with precise frequency.This crystal oscillator emulator 10 can utilize any technology (comprising complementary metal oxide semiconductors (CMOS) (CMOS) technology) to be structured on the single semiconductor die.
Crystal oscillator emulator 10 can comprise semiconductor oscillistor 14, is used to generate output signal 12.The semiconductor oscillistor of any kind all can use, and comprises LC oscillator, RC oscillator and ring oscillator.Semiconductor oscillistor 14 comprises control input 16, is used to change output signal frequency.Control input 16 can be any electricity input that influences the controlled change of output signal frequency, for example the supply voltage of ring oscillator and to the voltage input of the variable capacitance diode of LC oscillator.
Fig. 2 illustrates the memory technology 30 that is used at nonvolatile memory 18 storage calibration informations 20.This memory technology 30 can be any type of database, comprises CAM, index scheme, look-up table and hash table.
Fig. 3 illustrates a series of exemplary curve Figure 32 of the relation of the correction factor value of the constant output signal frequency that is used to keep crystal oscillator emulator 10 and temperature.The data that are used for curve construction can obtain with any way that comprises device level test and batch mode test.
The test of exemplary means level can comprise each device of test, keeps constant correction factor to determine the usefulness that will be applied to semiconductor oscillistor so that output frequency varies with temperature.In a kind of scheme, the baseline value of semiconductor oscillistor control input is to go up at preset frequency and at the predetermined temperature (for example minimum operating temperature) of the semiconductor die of device to determine.Baseline value can directly be measured, also can be from interpolation the measurement result of another device property is obtained.Also can measure baseline value for each potential output frequency.And, may be with for example by using the known circuit relation obtain at the baseline value of each potential output frequency from baseline value extrapolation at preset frequency.Can be stored as absolute value or ratio, a frequency factor come to calculate a plurality of baseline values from single baseline value at the baseline value of each potential output frequency.
Subsequently, the temperature of semiconductor die several times discrete steps rise to about maximum operating temperature from about minimum operating temperature.The number of times of discrete steps preferably is limited in about 6 temperature levels to reduce testing cost, and still the discrete steps of any number of times all can be used.Preferably, the sheet upper heater is used to heat semiconductor die, but also can adopt any device that changes the semiconductor die temperature.When each discrete steps, semiconductor die temperature and the correction factor that is used to make output keep constant frequency can be measured.
The preferably such ratio of correction factor, it is applied to baseline value to obtain the regulated value of control input.Correction factor can change according to any baseline value (for example 1).Preferably, calculate a correction factor at each temperature stepping, thereby apply it to semiconductor oscillistor output signal is maintained on any one frequency in a large amount of preset frequencies.For example, if correction factor 1.218 is confirmed as the variations in temperature corresponding to 45 ℃, then for example can the control input of semiconductor oscillistor be adjusted as the function of correction factor by changing the control input pro rata with this correction factor.In another substitute mode, correction factor can be applied to and the corresponding baseline value of required output frequency, to generate the calibration value after the control input is adjusted.In another substitute mode, can be when each temperature stepping and each frequency measurement update factor accordingly in some output frequencies.
Fig. 4 illustrates crystal oscillator emulator 40 on the other hand.The label range of crystal oscillator emulator 40 is similar to crystal oscillator emulator 10 in the respective element of 40-52 on function, but crystal oscillator emulator 40 can also comprise one or more heaters 54, controller 56 and select input 58 that these elements exist alone or in combination.
In one case, heater 54 can be brought up to maximum operating temperature with the temperature of semiconductor die.Here, at device or level test period in batches, be to determine only, thereby reduced cost corresponding to the correction factor of maximum operating temperature.
Fig. 5 illustrates an aspect of crystal oscillator emulator 100, and this crystal oscillator emulator 100 for example has two and selects pin 102 and 104, is used to be connected to two external impedances 106 and 108.One or more pins can be used to interface to external module.Crystal oscillator emulator 100 is surveyed or is obtained from the information that is connected to the external module of selecting pin 102 and 104.The information that obtains may have three or more the intended level scopes corresponding to selected simulator characteristic levels.For example, the single pin that is connected to external resistor can be used to select any one in 16 output frequency ranks.The resistance of external resistor preferably is chosen as in 16 predetermined standard value.In 16 resistance values each is corresponding to one in 16 output frequency ranks.In addition, the passive block of low accuracy is preferably reduced cost and stock as external module.Predetermined nominal value that each external module may have a plurality of (N), wherein each predetermined nominal value is corresponding to other selection of predetermined properties level.If use a pin, then can select N different characteristic levels.If use two pins, then can select N*N different characteristic levels, by that analogy.Type that for example can selecteed device property comprises output frequency, frequency tolerance and the baseline correction factor.For example, crystal oscillator emulator 100 can have a selection pin 102 that is connected to external resistor, and this external resistor can have the nominal value of selecting from the group of 16 predetermined values.In these 16 predetermined values each has a measured value range, and this scope is corresponding to 16 scopes in may the predetermined output frequency rank from 1MHz to 100MHz.
External impedance 106 and 108 is the combination of resistor, capacitor or resistor and capacitor preferably, but also can be the random component that mainly shows as inductance, resistance, electric capacity or its combination.External impedance 106 and 108 may be connected to pin 102 and 104 from any energy source (for example Vdd and ground) or any suitable reference directly or indirectly.For example, external impedance 106 can be connected to Vdd by the resistor/transistor network, and is connected to selection pin 102 by capacitor network.
Crystal oscillator emulator 100 can be determined and the corresponding predetermined selective value of measured value that is connected to the impedance of selecting pin.Preferably, impedance be chosen as and have with tolerance and be 10% (for example 470,560,680...) the corresponding standard value of resistor (for example normal resistance) to reduce device and cost of inventory.In order to consider the tolerance of measuring tolerance and external impedance, the scope of resistance value can be corresponding to single selective value.Selective value is a digital value preferably, but also can be an analogue value.For example, the resistance value of measuring from 2400 ohm to 3000 ohm can be associated with the digital value corresponding to 2.And the resistance value of measuring from 3001 ohm to 4700 ohm can be associated with the digital value corresponding to 3.The resistance of measuring comprises because the caused variation of tolerance of external impedance and internal measurement circuit.Be used to determine the corresponding digital value in each impedance of selecting to measure on the pin.The scope of digital value can comprise 3 or more a plurality of digital value, and preferred range is that each selects 10 digital value to 16 digital values of pin.Select the digital value of pin to be used in combination corresponding to each and describe storage address.For example, have three and select the device of pin can describe 1000 storage addresss or look-up table value, wherein each selects pin to be used for interface to the resistance value that is mapped to one of 10 digital values.Be used to be provided with the output of device or the value of bulk properties with the content of the corresponding memory location of storage address.Another exemplary means can comprise that two are selected pins, and wherein each selects pin to be joined the external impedance of value for the digital value of interface in the scope that is mapped as 10 values.Set of digital values can be described 1000 storage addresss or look-up table value altogether, and wherein each storage address or look-up table value can comprise the data of the characteristic that is used to be provided with crystal oscillator emulator 100.
Fig. 6 illustrates the block diagram of an aspect of crystal oscillator emulator 120.Crystal oscillator emulator 120 comprises selects pin 122, is used for the external impedance 124 of interface to the configuration that is used to select crystal oscillator emulator 120.External impedance 124 is similar to external impedance 106 and 108 on function and scope.
Be connected to the electrical characteristic of measuring circuit 126 measurements of selection pin 122 as the function of external impedance 124.For example, electric current can be provided to external impedance, and the voltage that is formed on the external impedance 124 subsequently can be measured.And voltage can be applied on the external impedance 124, measures electric current then.Any measuring technique that is used to measure passive block all can be used to measure electrical characteristic, comprises dynamically and static technique.Exemplary measuring technique comprises sequence circuit, analog to digital converter (ADC) and digital to analog converter (DAC).Preferably, measuring circuit has high dynamic range.Measuring circuit 126 can generate the output of its value corresponding to the value of external impedance 124.Output can be the numeral or the simulation.Same output valve is preferably represented certain scope of external impedance value, because the value that factors such as technology, temperature and power cause changes, for example the tolerance in the external impedance value, interconnection are lost and the measuring circuit tolerance with compensation.For example, scope can be relevant with digital output value " 0100 " from all the external impedance values measured greater than 22 ohm to 32 ohm.And scope can be relevant with digital output value " 0101 " from all the external impedance values measured greater than 32 ohm to 54 ohm.Actual external impedance value is a subclass of the external impedance value measured, changes with the value of taking into account.For example, under above situation, actual external impedance value may be from 24 ohm to 30 ohm with from 36 ohm to 50 ohm.In each case, can select cheap low accuracy resistor, its resistance value is in the centre of above-mentioned scope, for example 27 ohm and 43 ohm.So, can use cheap low accuracy assembly to come from the scope of pinpoint accuracy output, to select.Selective value can be used directly as the device property that variable value is controlled crystal oscillator emulator 120.This variable value also can be determined indirectly from selective value.
The situation that output valve that generates for measuring circuit 126 and external impedance value have one-to-one relationship, digital value determiner 128 subsequently can output valve be set to the selective value corresponding to the scope of external impedance value.
Fig. 7 A illustrates the relation of resistance value group 150 and relevant selective value 154.Resistance value group 150 may have one-to-one relationship with digital output value group 152, and digital output value group 152 is converted into the selective value 154 that is associated with each resistance value group 150.The resistance value of scope from the minimum impedance value to the maximum impedance value is divided into three or more groups, and wherein each group has nominal impedance.The nominal impedance value of each group can be selected, so that have certain between the nominal impedance value at interval.Here, the interval that has 16 ohm between 27 ohm and 43 ohm of the nominal values of resistance value group.Interval between the resistance value group is preferably based on geometric progression, but any arithmetic relation all can be used to set up interblock space, for example logarithm, linear and index.Interval between the impedance group can comprise nominal value, mean value, median, initial value and end value based on any resistance value in the group.Influence the impedance ranges of group and the factor of selection at interval and may comprise various tolerances, for example the tolerance of the tolerance of the tolerance of external impedance, builtin voltage and current source and measuring circuit.Tolerance for example may be caused by technology, temperature and variable power.
Fig. 7 B illustrates the relation between resistance value scope 156 and the relevant selective value 158.Resistance value scope 156 has direct corresponding relation with selective value 158.The resistance value of scope from the minimum impedance value to the maximum impedance value is divided into three or more groups, and wherein each group has nominal impedance.The nominal impedance value of each group can be chosen as has certain at interval between the nominal impedance value.Here, the interval that has 16 ohm between 27 ohm and 43 ohm of the nominal values of resistance value group.Direct corresponding relation between this resistance value scope 156 and the relevant selective value 158 for example can utilize the nonlinear analog-to-digital converter (not shown) to realize.
Return with reference to figure 6, address generator 130 can be determined the memory location corresponding to the digital output value that is associated with the external impedance that is connected to the selection pin.Memory location can make up by any way, for example at the tabulation of single selection pin, select the look-up table of pins and at three three rank tables of selecting pins at two.
In one aspect, be connected to many purposes and select first scope of the resistance value of pin 124 can be used to dispose crystal oscillator emulator 120, and the operation of additional function can be by the voltage or electric current or the resistance value control in addition of resistance value first scope that are applied on many purposes selection pins 124.
Fig. 8 illustrates the aspect that oscillator assembly 200 is used to generate the output with periodic waveform.Oscillator assembly 200 comprises crystal oscillator emulator 202, is used to drive phase-locked loop (PLL) 204.Crystal oscillator emulator 202 can be similar to the various aspects of above-mentioned crystal oscillator emulator on function and structure.Oscillator assembly 200 can comprise the PLL204 of any type, for example digital PLL and analog PLL.
Many purposes selection pins 206 and 208 can be used to select the running parameter of PLL 204, for example Frequency Dividing Factor.Many purposes select pins 206 and 208 also can be used to the control and the operation of crystal oscillator emulator 202, and for example output frequency is selected and the reference clock that is used to calibrate receives. External resistor 210 and 212 can be connected to many purposes and select pin 206 and 208 to select operating frequency.The scope of external resistor 210 and 212 value is corresponding to the selection of different operating frequency.Each external resistor 210 and 212 can be used to select a kind of in 16 kinds of predetermined work frequencies.Combine, external resistor 210 and 212 can be selected from 256 kinds of operating frequencies.In order to control a plurality of functions, each many purpose selects pin 206 and 208 can receive the interior signal of different voltage ranges.For example, purpose more than one selects pin 206 can be connected to external resistor 210, the voltage that externally can apply from 0 to 2 volt of scope on the resistor 210 to be determining resistance, and many purposes are selected pin 206 to receive to be operated in 2 to 3 volts of reference clock signals in the scope.Decoder 214 can detect the signal on many purposes selection pins 206 and 208.
Fig. 9 illustrates the spread spectrum oscillator 300 that is used to generate the output signal with variable frequency.Spread spectrum oscillator 300 comprises the crystal oscillator emulator 302 that is connected to PLL 304.The frequency control device that is connected to crystal oscillator emulator 302 can dynamically be controlled the output frequency of crystal oscillator emulator 302.This frequency control device can be any device or the technology that comprises variable capacitance diode, the bias current sources of its control semiconductor oscillistor, and control is applied to the control input voltage of the resonant capacitor of semiconductor oscillistor.
Figure 10 illustrates the operation of an aspect of crystal oscillator emulator.At square frame 400, semiconductor oscillistor is used to generate the output signal with periodic waveform.Proceed to square frame 402, semiconductor oscillistor can be calibrated, to generate constant frequency on predetermined temperature range.In one aspect, calibration can be included in the temperature that changes semiconductor die on the predetermined temperature range and measure the calibration information that is used to keep the constant output frequency.The nude film temperature can be measured near semiconductor oscillistor.Calibration information can comprise that control input value and being used to keeps the relation between the nude film temperature of constant output frequency.Calibration information can be stored in the nonvolatile memory on the semiconductor die.At square frame 404, can determine operating frequency by surveying external module.Proceed to square frame 406, semiconductor oscillistor generates the output signal with operating frequency.At square frame 408, the temperature of semiconductor die is determined near semiconductor oscillistor.Proceed to square frame 410, semiconductor die can be heated or cooled, the nude film temperature is controlled to one or more predetermined temperature ranks.At square frame 412, the control input can be used as the function Be Controlled of nude film temperature, to compensate the change of the output signal operating frequency that is caused by temperature change.The calibration information of storage can be used to control control input.The corresponding nude film temperature of the temperature that calibration information can be directly used in and store.For other nude film temperature, the control input value can be extrapolated from the calibration information of storage.Proceed to square frame 414, the function that output signal frequency can be used as frequency control signal dynamically changes.
Figure 11 illustrates an aspect of the low-power oscillator 320 that is used to generate cyclical signal.Low-power oscillator 320 comprises crystal oscillator emulator 322, is used to calibrate active silicon oscillator 324.Crystal oscillator emulator 322 is in off state usually to reduce power consumption.With predetermined space, crystal oscillator emulator 322 is switched to the on-state that powers up to calibrate active silicon oscillator 324.The power that active silicon oscillator 324 consumes will be less than the power that crystal oscillator emulator 322 consumes, and therefore makes active silicon oscillator 324 continuous operations and only makes crystal oscillator emulator 322 intermittent works reduce the total power consumption of low-power oscillator 320.The active silicon oscillator of any type all can be used, and comprises ring oscillator and RC oscillator.Crystal oscillator emulator 322 can dispose according to the either side in the many aspects of the present invention of describing in this specification and illustrating.
In operation, active silicon oscillator 324 is in on-state usually to generate periodic output signal.Crystal oscillator emulator 322 is in off state usually.In off state, all or part of of crystal oscillator emulator 322 is de-energized to save power.At the fixed time, power is supplied to crystal oscillator emulator 322.The semiconductor oscillistor of crystal oscillator emulator 322 utilizes the calibration information of storage to be calibrated subsequently.The output signal frequency of crystal oscillator emulator 322 is compared with the output signal frequency of active silicon oscillator 324, to determine the frequency error of active silicon oscillator 324.Control signal 334 changes in response to frequency error, thereby causes the supply voltage displacement from voltage adjuster 332, causes the output frequency of active silicon oscillator 324 to change, and reduces frequency error.
Figure 12 illustrates an aspect of another low-power oscillator 350 that is used to generate cyclical signal.Low-power oscillator 350 comprises crystal oscillator emulator 352, and it is communicated by letter with charge pump oscillator 354.Crystal oscillator emulator 352 is in off-position usually, to reduce power consumption.During off-position, all or part of of crystal oscillator emulator 352 is de-energized.With predetermined space, crystal oscillator emulator 352 can be powered, and is used to calibrate charge pump oscillator 354.This predetermined space can be used as the function of any circuit parameter to be determined, described parameter for example is operating time, semi-conductive variations in temperature, variation of ambient temperature, conductor temperature and mains voltage variations.
Charge pump oscillator 354 can comprise charge pump 356, loop filter 358, voltage controlled oscillator (VCO) 360 and phase detectors 362.Except the reference clock signal of reference input reception from crystal oscillator emulator 352 of phase detectors 362, charge pump oscillator 354 is similar in operation to traditional charge pump oscillator.
The output signal that multiplexer 364 receives from crystal oscillator emulator 352 and charge pump oscillator 354.One of output signal is selected and arrives phase-locked loop 366 through multiplexer 364.Phase-locked loop 366 generates the output signal of conduct from the function of the output signal of crystal oscillator emulator 352 and charge pump oscillator 354.
In operation, charge pump oscillator 354 is in on-state usually, to generate periodic output signal.Crystal oscillator emulator 352 is in off state usually.In off state, all or part of of crystal oscillator emulator 352 is de-energized to reduce power consumption.At the fixed time, power is provided to crystal oscillator emulator 352.The semiconductor oscillistor of crystal oscillator emulator 352 utilizes the calibration information of storage to be calibrated subsequently.The output signal of crystal oscillator emulator 352 is compared with the output signal of charge pump oscillator 354 to determine the phase error of charge pump oscillator 354.VCO360 is controlled to reduce phase error subsequently, thereby the output signal of charge pump oscillator 354 is calibrated to the output signal of crystal oscillator emulator 352.One of output signal subsequently can be selected and be provided to PLL366.
With reference now to Figure 13-15,, integrated circuit 500 comprises the crystal oscillator emulator 502 that generates clock signal.One or more circuit 504 receive clock signals in the integrated circuit 500.Crystal oscillator emulator 502 can be realized to the described mode of Figure 12 in conjunction with Fig. 1 by above.Circuit 502 can comprise processor shown in Figure 14 512 or other circuit.External module 506 can be used to select the clock frequency of crystal oscillator emulator 502 alternatively, as Figure 13 and shown in Figure 15.
With reference now to Figure 16-18,, integrated circuit 518 comprises Clock dividers 520, its on another one or a plurality of other clock frequency, generate be used for circuit 522-1,522-2 ... and the clock signal of 522-N (general designation circuit 522).Circuit 522 can interconnect by any way each other.Clock dividers 520 multiply by clock signal with clock divided by an integer (for example X) and/or with Y, adjusts to be used for 1/X, Y and/or Y/X.Clock dividers 520 also can use one or more other ratios and/or divisor to produce the different clocks signal that is used for other circuit 522.Clock dividers 520 will shown in N-1 clock signal output to N-1 circuit 522 in the integrated circuit 518.
In Figure 17, one of circuit comprises processor 530.Processor 530 can be connected to Clock dividers 520 and be free of attachment to crystal oscillator emulator 502 and/or be connected to Clock dividers 520 and crystal oscillator emulator 502 both.Adjunct circuit 532-1,532-2 ... communicate by letter with Clock dividers 520 with 532-N.
In Figure 18, crystal oscillator emulator 502 is provided for the clock signal of the one or more circuit 544 in processor 530, graphic process unit 540, memory 542 and/or the integrated circuit 518.The Clock dividers (not shown) also can be provided.Processor 530, graphic process unit 540, memory 542 and/or other circuit 544 can interconnect in any suitable manner.
With reference now to Figure 19,, integrated circuit 600 comprise one or more circuit 602-1,602-2 ... and 602-N (general designation circuit 602) and low-power oscillator 320, they are worked in conjunction with the described mode of Figure 11 by above.One of circuit can comprise processor, is illustrated as 610.As mentioned above, the Clock dividers (not shown) also can be provided.
Integrated circuit (IC) is loaded in the encapsulating material usually.Encapsulating material can comprise plastics.The IC substrate can comprise the pad that is connected to the lead-in wire of lead frame via closing line (bondwire).IC substrate, closing line and part lead-in wire can be installed in the plastics.The attribute that is commonly used to encapsulate the encapsulating material of IC may change in time.These variations may cause on the sheet frequency of oscillation of oscillator to be drifted about in time.The variation of encapsulation may be that the dielectric absorption owing to encapsulating material changes in time and causes.The variation of encapsulation also may be because the water absorption of encapsulating material on the different humidity rank causes.As a result, encapsulating material may limit attainable calibration accuracy.
With reference now to Figure 20,, integrated circuit 700 is encapsulated in the encapsulating material 704 according to prior art.Can recognize that the characteristic of encapsulating material 704 may change and/or in time as the function of environmental condition.For example, when encapsulating material 704 comprised plastic material, the dielectric absorption of plastic material may change in time, and this may have a negative impact to calibration accuracy.Term used herein " dielectric absorption " refers to the energy loss that finally causes the dielectric temperature rising that is placed in the AC field.Heating be since when dipole attempts to utilize the vibration () of incident wave to redefine himself direction " molecular friction " of the dipole in the material cause.For example, when heating things in microwave, the dipole vibration related with the water in the food also is heated.Some material such as certain plastics is not suitable for being used in the microwave, because they absorb too many heat.These materials have high dielectric absorption characteristic.Other materials (for example plastics of other type) experiences very little or does not experience heating.These materials have low dielectric absorption characteristic.Because circuit described herein can be worked on microwave frequency, therefore low dielectric absorption material is preferred.
Plastic material water absorption in time also may have a negative impact to the calibration accuracy.Because glassware for drinking water has high dielectric absorption, therefore increase the dielectric absorption that water content in the encapsulating material is easy to increase encapsulating material.In other features, encapsulating material also can be a low-stress material.Heavily stressed material is easy to bending, and this may for example influence the circuit characteristic of adjacent circuit by changing channel length.Term used herein " low stress " refers to the stable encapsulating material that is not easy to change with STRESS VARIATION the electrical characteristics of integrated circuit.In some implementation, the electrical dissipation factor that encapsulating material has (DLF) (for example greater than 1GHz) on the related work frequency is less than or equal to Teflon (polytetrafluoroethylene).
With reference now to Figure 21,, the integrated circuit 710 with the sheet semiconductor-on-insulator oscillator 711 that has temperature-compensating is illustrated as being encapsulated in according in the encapsulating material 714 with low dielectric absorption of the present invention.Encapsulating material 714 can be the plastic encapsulant with low dielectric absorption.The dielectric absorption that term used herein " low dielectric absorption " refers to material is less than or equal to Teflon on the related work frequency of IC.The operating frequency of IC may be greater than 1GHz and/or 2.4GHz.Encapsulating material 714 can also comprise Teflon
, Teflon
Polytrifluorochloroethylene (PCTFE), Teflon
Teflon
Perfluoroethylene-propylene (FEP), polytetrafluoroethylene (PFA), Tefzel
And Teflon
Ethylene-tetrafluoroethylene copolymer (ETFE), low dielectric absorption plastics, high quality glass, air and/or other materials.Can consider to use any other dielectric absorptions to be less than or equal to the encapsulating material of Teflon.Encapsulating material also may have relatively low water absorption.
With reference now to Figure 22,, illustrates in greater detail the exemplary implementation of the integrated circuit encapsulation of Figure 21.Integrated circuit encapsulation 718 comprises integrated circuit 724, and integrated circuit 724 comprises pad 728.The lead-in wire 732 of lead frame 733 is connected to the pad 728 of integrated circuit by closing line 734.Can recognize that this integrated circuit comprises above-mentioned sheet semiconductor-on-insulator oscillator with temperature-compensating.A part, closing line 734 and the integrated circuit 724 of lead-in wire 732 are encapsulated in the encapsulating material 736.Encapsulating material 736 can be the plastic encapsulant with low dielectric absorption.Can recognize, in this embodiment and/or other embodiment, can adopt the encapsulation of other type, for example ball grid array (BGA), flip-chip and/or other suitable encapsulation technologies arbitrarily.
With reference now to Figure 23,, another integrated circuit encapsulation 738 sheet semiconductor-on-insulator oscillators 741 that comprise according to band temperature-compensating of the present invention.In this embodiment, semiconductor oscillistor 741 comprises integrated circuit inductor 742.Glassy layer 744 joins ic substrate 740 to by extremely thin epoxy layer 750.Epoxy layer 750 can have low dielectric absorption.Glassy layer 744, epoxy layer 750 and ic substrate 740 are encapsulated in the encapsulating material 760.In the case, because the distance between inductor 742 and the encapsulating material 760, therefore harsh no longer so to the requirement of the dielectric absorption of encapsulating material.Therefore, harsh no longer so to requirement as the variation of the dielectric absorption of the encapsulating material 760 of the function of time and/or other characteristics.But encapsulating material can be low dielectric absorption material.Though glassy layer is shown on the whole integrated circuit, glassy layer also can be confined to be close to semiconductor oscillistor than in the zonule.
With reference now to Figure 24 and 25,, the integrated circuit encapsulation that another comprises sheet semiconductor-on-insulator oscillator according to the present invention is illustrated.This embodiment is similar to the above embodiment that illustrates and describe in conjunction with Figure 23.But glassy layer 744 defines a cavity 746.Cavity 746 and inductor be 742 adjacent, align and spread on the inductor 742.Air chamber 752 is formed between inductor 742 and the glassy layer 744.Thin epoxy layer 750 is formed between glassy layer 744 and the ic substrate 740, but does not comprise the zone of cavity 746.Glassy layer 744 can be etched with the qualification cavity, and be immersed in the epoxy.Similarly, glassy layer can comprise compound glass, and is being formed with cavity in one deck at least.
With reference now to Figure 26,, the capacitor of sheet semiconductor-on-insulator oscillator can compensate based on said temperature and adjust.But, can recognize, exist additive method can be independent of the capacitor of semiconductor oscillistor and/or frequency of oscillation is adjusted in the adjustment of inductor.
With reference now to Figure 27,, integrated circuit 830 comprises the fractional phase locked loop 831 with temperature-compensating input.Fractional phase locked loop 831 comprises phase-frequency detector 836, and it receives the output of the integrated circuit oscillator 832 of working in a manner described.Phase-frequency detector 836 generates differential signal based on the difference of reference frequency and VCO frequency.This differential signal is output to charge pump 840.The output of charge pump 840 is imported into optional loop filter 844.The output of loop filter 844 is transfused to voltage controlled oscillator (VCO), this voltage controlled oscillator generated frequency with to the relevant VCO output of the voltage of its input.Convergent-divergent (scaling) circuit 850 selectively with the VCO frequency divided by N or N+1.Though adopt divisor N and N+1, divisor also can be other values.
The output of convergent-divergent circuit 850 is fed back to phase-frequency detector 836.Measure the temperature of integrated circuit 830 near the zone of temperature sensor 854 IC oscillator 832.Temperature sensor 854 outputs are used to the temperature signal of the calibration information 858 of addressable storage in memory 856.Selected calibration information is used to adjust convergent-divergent circuit 850.Selected calibration information is adjusted the divisor N of convergent-divergent circuit 850 uses and the ratio of N+1.
With reference now to Figure 28,, Delta-Sigma fractional phase locked loop 858 is illustrated, and it is used to comprise the integrated circuit 860 of temperature-compensating input.Selected calibration information is used to adjust the output of Sigma Delta modulator 870.Selected calibration information can be adjusted the divisor N of convergent-divergent circuit 850 uses and the modulation between the N+1.
With reference now to Figure 29,, flow chart 900 illustrates and is used to measure sample calibration point and utilizes the linearity curve fitting algorithm to generate the step of calibration data.Control starts from step 902.In step 904, the sample calibration point on a plurality of temperature of control survey.In step 906, the linearity curve fitting algorithm is used to generate the curve of other temperature spots between these sample points.
With reference now to Figure 30,, flow chart 920 illustrates and is used to measure sample calibration point and uses the more step of luminance curve fitting algorithm generation calibration data.Step shown in Figure 29 can utilize the computer that comprises processor and memory to realize.Control starts from step 922.In step 924, the sample calibration point on a plurality of temperature of control survey.In step 926, more the luminance curve fitting algorithm is used to generate the curve of other temperature spots between these sample points.In step 928, control finishes.
With reference now to Figure 31 A, to Figure 31 G, various exemplary implementations of the present invention are illustrated.With reference now to Figure 31 A,, the present invention is implemented in the hard disk drive 1000.The present invention can realize any integrated circuit, for example signal processing and/or control circuit, and they are summarized in Figure 31 A and are designated 1002.In some implementation, signal processing among the HDD1000 and/or control circuit 1002 and/or other circuit (not shown) can deal with data, carry out coding and/or encryption, carry out and calculate, and/or to outputing to and/or be received from the data placement form of magnetic storage medium 1006.
HDD1000 can communicate by letter with the main process equipment (not shown) via one or more wired or wireless communication links 1008, and main process equipment for example is computer, the mobile computing device such as personal digital assistant, cell phone, medium or MP3 player and/or other equipment.HDD1000 can be connected to memory 1009, for example random access storage device (RAM), the low latency nonvolatile memory such as flash memory, read-only memory (ROM) and/or other suitable electronic data storage.
With reference now to Figure 31 B,, the present invention is implemented in digital versatile disc (DVD) driver 1010.The present invention can realize any integrated circuit of signal processing for example and/or control circuit (they summarize be designated 1012) and/or the Mass Data Storage Facility of DVD driver 1010 in Figure 31 B.Signal processing among the DVD1010 and/or control circuit 1012 and/or other circuit (not shown) can deal with data, carry out coding and/or encrypt, carry out and calculate, and/or to read from and/or write the data placement form of optical storage media 1016.In some implementation, signal processing among the DVD1010 and/or control circuit 1012 and/or other circuit (not shown) can also be carried out other functions, for example encode and/or decode, and/or drive any other signal processing function that is associated with DVD.
DVD driver 1010 can be communicated by letter with the output equipment (not shown) such as computer, TV or other equipment via one or more wired or wireless communication links 1017.DVD1010 can communicate by letter with the Mass Data Storage Facility 1018 with the non-volatile storage data.Mass Data Storage Facility 1018 can comprise hard disk drive (HDD).HDD can have shown in Figure 31 A and disposes.HDD comprises that one or more diameters are less than about 1.8 " the mini HDD of disc (platter).DVD1010 can be connected to memory 1019, for example RAM, ROM, the low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
With reference now to Figure 31 C,, the present invention is implemented in the high definition television (HDTV) 1020.The present invention can realize the Mass Data Storage Facility of any integrated circuit, WLAN interface and/or the HDTV1020 of signal processing for example and/or control circuit (they summarize be designated 1022) in Figure 31 C.HDTV1020 receives the HDTV input signal of wired or wireless form and generates the HDTV output signal that is used for display 1026.In some implementation, the signal processing of HDTV1020 and/or control circuit 1022 and/or other circuit (not shown) can deal with data, carry out coding and/or encrypt, carry out and calculate, data massaging and/or the HDTV that carries out any kind that needs are handled.
HDTV1020 can communicate by letter with Mass Data Storage Facility 1027, and this memory device 1027 is with the non-volatile storage data, for example light and/or magnetic storage apparatus.At least one HDD can have shown in Figure 31 A and disposes, and/or at least one DVD can have shown in Figure 31 B and disposes.HDD comprises that one or more diameters are less than about 1.8 " the mini HDD of disc.HDTV1020 can be connected to memory 1028, for example RAM, ROM, the low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.HDTV1020 can also support being connected via wlan network interface 1029 and WLAN.
With reference now to Figure 31 D,, the present invention has realized the Mass Data Storage Facility of any integrated circuit, WLAN interface and/or vehicle control system in the control system of vehicle 1030.In some implementation, the present invention has realized power assembly control system 1032, and it receives from the input of one or more transducers (for example temperature sensor, pressure sensor, rotation sensor, pneumatic sensor and/or other right sensors arbitrarily) and/or generates one or more output control signals (for example engine running parameter, transmission running parameter and/or other control signals).
The present invention also is implemented in the other control system 1040 of vehicle 1030.Control system 1040 can output to one or more output equipments 1044 from input pickup 1042 received signals and/or with control signal equally.In some implementation, control system 1040 can be anti-lock braking system (ABS), navigation system, information communication system, information of vehicles communication system, deviation system, adaptability cruise control system, such as the part in the vehicle entertainment system of stereo, DVD, compact disk etc.Other implementations also can be conceived to.
Power assembly control system 1032 can be communicated by letter with the Mass Data Storage Facility 1046 with the non-volatile storage data.Mass Data Storage Facility 1046 can comprise light and/or magnetic storage apparatus, for example hard disk drive HDD and/or DVD.At least one HDD can have shown in Figure 31 A and disposes, and/or at least one DVD can have shown in Figure 31 B and disposes.HDD comprises that one or more diameters are less than about 1.8 " the mini HDD of disc.Power assembly control system 1032 can be connected to memory 1047, for example RAM, ROM, the low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.Power assembly control system 1032 can also be supported being connected via wlan network interface 1048 and WLAN.Control system 1040 can also comprise Mass Data Storage Facility, memory and/or WLAN interface (all not shown).
With reference now to Figure 31 E,, the present invention is implemented in the cell phone 1050 that can comprise cellular antenna 1051.The present invention can realize the Mass Data Storage Facility of any integrated circuit, WLAN interface and/or the cell phone 1050 of signal processing for example and/or control circuit (they summarize be designated 1052) in Figure 31 E.In some implementation, cell phone 1050 comprises microphone 1056, the output of the audio frequency such as loud speaker and/or audio frequency output plug 1058, display 1060 and/or the input equipment 1062 such as keyboard, some optional equipment, voice-activated and/or other input equipments.Signal processing in the cell phone 1050 and/or control circuit 1052 and/or other circuit (not shown) can deal with data, carry out coding and/or encrypt, carry out calculate, to the data massaging and/or carry out other cellular telephone functions.
With reference now to Figure 31 F,, the present invention is implemented in the set-top box 1080.The present invention can realize the Mass Data Storage Facility of any integrated circuit, WLAN interface and/or the set-top box 1080 of signal processing for example and/or control circuit (they summarize be designated 1084) in Figure 31 F.Set-top box 1080 receives from the signal of source (for example broad band source) and exports standard and/or the HD Audio/vision signal that is suitable for display 1088, and described display 1088 for example is TV and/or monitor and/or other video and/or audio output equipments.The signal processing of set-top box 1080 and/or control circuit 1084 and/or other circuit (not shown) can deal with data, carry out coding and/or encrypt, carry out calculate, to the data massaging and/or carry out other set-top box functionality arbitrarily.
Set-top box 1080 can be communicated by letter with the Mass Data Storage Facility 1090 with the non-volatile storage data.This Mass Data Storage Facility 1090 can comprise light and/or magnetic storage apparatus, for example hard disk drive HDD and/or DVD.At least one HDD can have shown in Figure 31 A and disposes, and/or at least one DVD can have shown in Figure 31 B and disposes.HDD comprises that one or more diameters are less than about 1.8 " the mini HDD of disc.Set-top box 1080 can be connected to memory 1094, for example RAM, ROM, the low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.Set-top box 1080 can also be supported being connected via wlan network interface 1096 and WLAN.
With reference now to Figure 31 G,, the present invention is implemented in the media player 1100.The present invention can realize the Mass Data Storage Facility of any integrated circuit, WLAN interface and/or the media player 1100 of signal processing for example and/or control circuit (they summarize be designated 1104) in Figure 31 G.In some implementation, media player 1100 comprises that display 1107 and/or user import 1108, for example keyboard, touch dish or the like.In some implementation, media player 1100 can be imported 1108 via display 1107 and/or user and use graphic user interface (GUI), and this graphic user interface adopts menu, drop-down menu, icon usually and/or clicks the interface.Media player 1100 also comprises audio frequency output 1109, for example loud speaker and/or audio frequency output plug.The signal processing of media player 1100 and/or control circuit 1104 and/or other circuit (not shown) can deal with data, carry out coding and/or encrypt, carry out calculate, to the data massaging and/or carry out other media player functions arbitrarily.
Media player 1100 can with communicate by letter with the Mass Data Storage Facility 1110 of non-volatile storage data (for example compressed audio and/or video content).In some implementation, compacted voice file comprises the file of following MP3 format or other proper compression audio frequency and/or video format.This Mass Data Storage Facility can comprise light and/or magnetic storage apparatus, for example hard disk drive HDD and/or DVD.At least one HDD can have shown in Figure 31 A and disposes, and/or at least one DVD can have shown in Figure 31 B and disposes.HDD comprises that one or more diameters are less than about 1.8 " the mini HDD of disc.Media player 1100 can be connected to memory 1114, for example RAM, ROM, the low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.Media player 1100 can also be supported being connected via wlan network interface 1116 and WLAN.Other implementations except above-mentioned implementation also can be conceived to.
With reference now to Figure 32 A-32D,, shown in integrated circuit encapsulation incorporated annealed glass slurry or epoxy into as one deck and/or a plurality of " islands " adjacent with the one or more selected feature of silicon wafer.One or more " islands " of annealed glass slurry or epoxy layer can be set on some part of one or both sides of silicon wafer.In Figure 32 A, another integrated circuit encapsulation 1200 comprises silicon wafer 1204.A plurality of parts 1206 of annealed glass slurry layer or annealed glass slurry are formed on the silicon wafer 1204.Mold material 1208 can be used to encapsulate all or part of of silicon wafer 1204.Annealed glass slurry layer 1206 has also reduced stress over time.The influence of the variation of all or part of dielectric properties (the some loss for example is situated between) that is not subjected to mold material 1208 that annealed glass slurry layer 1206 is easy to make silicon wafer 1204.
In Figure 32 B, another integrated circuit encapsulation 1210 comprises conductive material layer or coating 1212, and it is applied on glass paste or the epoxy layer 1206.Conductive material layer 1212 can comprise the conductive epoxy layer.Conductive material layer 1212 can be used as liquid and applies, and is cured then.Conductive material layer 1212 can comprise conductive epoxy coating.Conductive material layer 1212 can apply in any suitable manner, comprises silicon wafer 1204 is immersed in the container (for example plate) that comprises electric conducting material.Conductive material layer 1212 is easy to reduce the electromagnetic interference from external equipment.
In Figure 32 C, integrated circuit encapsulation 1220 comprises annealed glass slurry layer 1206, and it is applied on the selected portion of silicon wafer 1204.In Figure 32 D, integrated circuit encapsulation 1230 comprises annealed glass slurry or epoxy moieties 1206 and electric conducting material 1212.Electric conducting material 1212 can capping annealing glass paste layer 1206, touches or do not touch silicon wafer 1204 simultaneously.
With reference now to Figure 33 A-33D,, other integrated circuit encapsulation are illustrated.In Figure 33 A, another integrated circuit encapsulation 1240 comprises annealed glass slurry layer 1206 and conductive material layer 1212, and they are positioned near the circuit unit 1242 of silicon wafer 1204.In Figure 33 B, another integrated circuit encapsulation 1250 comprises annealed glass slurry layer 1206 and conductive material layer 1212, and they are positioned near the oscillator 1252 of silicon wafer 1204.
In Figure 33 C, another integrated circuit encapsulation 1260 comprises annealed glass slurry layer 1206 and conductive material layer 1212, and they are positioned near the inductor 1262 of silicon wafer 1204.Inductor 1262 can be on-chip inductors, for example spiral inductor.In Figure 33 D, another integrated circuit encapsulation 1270 comprises annealed glass slurry layer 1206 and conductive material layer 1212, and they are positioned near the pierce circuit 1272 that has inductor 1274.
Annealed glass slurry layer also is easy to reduce contingent stress over time.The influence of the variation of all or part of dielectric properties (for example dielectric absorption) that is not subjected to mold material that annealed glass slurry layer makes silicon wafer.This is especially useful when attempting to utilize temperature to calibrate (as mentioned above).
With reference now to Figure 34 A-34D,, the encapsulation of other integrated circuits is illustrated, and they are included in annealed glass slurry and/or epoxy moieties and glass or the silicon layer of having set up the air gap on some part of silicon wafer.In Figure 34 A-34B, integrated circuit encapsulation 1300 and 1330 comprises silicon wafer 1304.Annealed glass slurry part 1306 is formed on the silicon wafer 1304 with the relation of separating on certain space.AGP part 1306 can form in a manner described.Mold material 1308 can be used.The reprocessing of AGP part 1306 can be performed (for example polishing or other steps) flat outer surface is provided.
Glass or silicon layer 1310 rely on AGP part 1306 to be supported on silicon wafer 1304 tops.Epoxy or other grafting materials can be used to glass or silicon layer 1310 are pasted on the AGP part 1306.AGP part 1306 and glass or silicon layer 1310 are at oscillator 1320 (Figure 34 A) and/or form air gap 1324 above other circuit 1322 (Figure 34 B) arbitrarily.Air gap 1324 provides the material (air) with minimum possible dielectric absorption.On the contrary, when using crystal oscillator, need air to allow crystal resonance, in other words, air is used to allow mechanical oscillation.
In Figure 34 C-34D, integrated circuit encapsulation 1340 and 1360 comprises silicon wafer 1304.Epoxy moieties 1342 is formed on the silicon wafer 1304 with the relation of separating on certain space.Epoxy moieties 1342 can form in a manner described.The reprocessing of epoxy moieties 1342 can be performed (for example polishing or other steps) flat outer surface is provided.Glass or silicon layer 1310 rely on epoxy moieties 1342 to be supported on silicon wafer 1304 tops.Epoxy or other grafting materials can be used to glass or silicon layer 1310 are pasted on the epoxy moieties 1342.Epoxy moieties 1342 and glass or silicon layer 1310 are at oscillator 1320 (Figure 34 C) and/or form air gap 1324 above other circuit 1322 (Figure 34 D) arbitrarily.
With reference now to Figure 35 A-35B,, other integrated circuit encapsulation are illustrated, and they comprise glass or the silicon part of having set up the air gap.In Figure 35 A, integrated circuit encapsulation 1380 comprises " C " shape glass or silicon part 1382, and it defines air gap 1384." C " shape glass or silicon part 1382 can comprise a plurality of segmentations that connect together.Air gap 1384 is positioned at oscillator 1320 tops.In Figure 35 B, integrated circuit encapsulation 1390 comprises " C " shape glass or silicon layer 1382, and it defines air gap 1384.Air gap 1384 is positioned at circuit 1322 tops.
With reference now to Figure 36 A-36C,, shows the method that is used to make the said integrated circuit encapsulation.Integrated circuit structure 1400 comprises silicon wafer 1404, a plurality of isolated AGP and/or epoxy moieties 1410A and 1410B (being referred to as part 1410) and glass or silicon layer 1408.Integrated circuit structure 1400 is cut into a plurality of segmentations along dotted line 1414, and to set up a plurality of integrated circuits, these integrated circuits can be encapsulated in the above-mentioned mold material (not shown).
In Figure 36 B, silicon wafer 1404 can comprise one or more bond pads 1420.The otch of 1414-1 and 1414-2 place layer 1408 can relative 1414-3 place silicon wafer otch be offset to some extent, to be provided for the closing line (not shown) is attached to the interval of bond pad 1420.In Figure 36 C, be illustrated at one of integrated circuit 1450 that from integrated circuit structure 1400, is partitioned into.
With reference now to Figure 37 A-37B,, integrated circuit encapsulation 1450 comprises and has a plurality of isolated annealed glass slurry of layer of conductive material 1456 coated and/or the silicon wafer of epoxy moieties 1410.In Figure 37 A, part 1410 is submerged in the container 1454, comprises electric conducting material 1456 in the container 1454.Silicon wafer 1408 can be along one or more tangent line 1462 by stripping and slicing, and can comprise bond pad 1460, as shown in the figure.
With reference now to Figure 38,, the step of method 1500 that is used for the integrated circuit encapsulation of shop drawings 32A-33D is illustrated.Control starts from step 1502.In step 1504, glass paste layer 1206 is applied on one or more surfaces of silicon wafer 1204 and/or on institute's favored area of silicon wafer 1204.In step 1506, glass paste layer 1206 is carried out annealing operation by silicon wafer 1204 and glass paste layer 1206 are placed on to come in the baking oven.The temperature of baking oven can be set to be enough to solidify the temperature of (cure) glass paste layer 1206.For example, about 400 ℃ temperature is enough to make the annealing of glass dust slurry in scheduled time slot, and can not damage silicon wafer 1204.In step 1508, conductive material layer 1212 is applied to annealed glass slurry layer 1206.In step 1510, all or part of of silicon wafer 1204 is loaded in the mold material 1208, and this mold material is plastics, other materials described herein and/or other suitable mold materials for example.In step 1520, control finishes.
In above-mentioned each embodiment, silicon wafer can be replaced by other wafers or other substrates, and the annealed glass slurry can be replaced by epoxy.
A plurality of embodiment of invention have been described.Yet, will be understood that, under the situation that does not break away from the spirit and scope of the present invention, can carry out various modifications.Therefore, other embodiment also within the scope of the appended claims.
The application requires the U.S. Provisional Application No.60/714 that submitted on September 6th, 2005,454, the U.S. Provisional Application No.60/756 that on January 6th, 2006 submitted, the U.S. Provisional Application No.60/730 that on October 27th, 828 and 2005 submitted, 568 priority, and the application is the U.S. Patent application No.10/892 that submitted on July 16th, 2004,709 part continuation application, and application No.10/892,709 is the U.S. Patent application No.10/272 that submitted on October 15th, 2002,247 part continuation application, the full content of above all applications is incorporated into this by reference in view of the above.
Claims (33)
1. integrated circuit encapsulation comprises:
Integrated circuit (IC) wafer; And
Annealed glass slurry layer with the adjacent layout of described integrated circuit (IC) wafer.
2. integrated circuit encapsulation as claimed in claim 1 also comprises mold material, and it encapsulates at least a portion of described annealed glass slurry layer and described integrated circuit (IC) wafer.
3. integrated circuit encapsulation as claimed in claim 1, wherein said annealed glass slurry layer is disposed at least one side of described integrated circuit (IC) wafer.
4. integrated circuit as claimed in claim 1 encapsulation, wherein said annealed glass slurry layer are disposed on a plurality of separated regions at least one side of described integrated circuit (IC) wafer.
5. integrated circuit encapsulation as claimed in claim 1 also comprises conductive material layer, and it is disposed on the part of described annealed glass slurry layer.
6. integrated circuit encapsulation as claimed in claim 2, wherein said integrated circuit (IC) wafer comprises the circuit unit that is arranged on the described integrated circuit (IC) wafer, wherein said annealed glass slurry layer is disposed between described circuit unit and the described mold material.
7. integrated circuit as claimed in claim 6 encapsulation, wherein said circuit unit comprise at least a in oscillator and the inductor.
8. integrated circuit encapsulation as claimed in claim 7, wherein said inductor comprises spiral inductor.
9. integrated circuit encapsulation as claimed in claim 2, wherein said mold material has encapsulated the part of described integrated circuit (IC) wafer.
10. integrated circuit encapsulation as claimed in claim 1, wherein said annealed glass slurry layer comprises glass dust.
11. integrated circuit as claimed in claim 1 encapsulation, wherein said annealed glass slurry layer are to utilize a kind of in coating of silk screen printing, dipping and color separation and by with the adjacent layout of described integrated circuit (IC) wafer.
12. integrated circuit as claimed in claim 5 encapsulation, wherein said electric conducting material comprise a kind of in conductive epoxy and the conductive epoxy coating.
13. integrated circuit encapsulation as claimed in claim 5, wherein said conductive material layer are to be disposed in the container that comprises described electric conducting material on the described annealed glass slurry layer by described integrated circuit encapsulation is immersed in.
14. an integrated circuit encapsulation comprises:
Integrated circuit (IC) wafer;
First with the adjacent layout of described integrated circuit (IC) wafer;
Adjacent layout with described integrated circuit (IC) wafer and with the isolated second portion of described first, wherein said first and second parts comprise at least a in annealed glass slurry and the epoxy; And
With the layer of the adjacent layout of described first and second parts, make between described layer, described first and second parts and described integrated circuit (IC) wafer, to form the air gap.
15. integrated circuit encapsulation as claimed in claim 14, wherein said integrated circuit (IC) wafer comprises silicon wafer.
16. integrated circuit encapsulation as claimed in claim 14 also comprises mold material, it encapsulates at least a portion of described first and second parts, described layer and described integrated circuit (IC) wafer.
17. integrated circuit as claimed in claim 14 encapsulation, wherein said layer comprise at least a in glass and the silicon.
18. integrated circuit encapsulation as claimed in claim 14 also comprises the electric conducting material with the adjacent layout of described first and second parts.
19. integrated circuit encapsulation as claimed in claim 15, wherein said silicon wafer comprises circuit unit, and wherein said air gap is disposed between described circuit unit, described layer and described first and second parts.
20. integrated circuit as claimed in claim 19 encapsulation, wherein said circuit unit comprise at least a in oscillator and the inductor.
21. integrated circuit encapsulation as claimed in claim 20, wherein said inductor comprises spiral inductor.
22. integrated circuit encapsulation as claimed in claim 14, wherein said first and second parts comprise glass dust.
23. integrated circuit as claimed in claim 14 encapsulation, wherein said first and second parts are to utilize a kind of in coating of silk screen printing, dipping and color separation and be applied to described silicon wafer.
24. integrated circuit as claimed in claim 18 encapsulation, wherein said electric conducting material comprise a kind of in conductive epoxy and the conductive epoxy coating.
25. integrated circuit encapsulation as claimed in claim 18, wherein said electric conducting material are to be immersed in by at least a portion with described integrated circuit encapsulation to be applied to described first and second parts in the container that comprises described electric conducting material.
26. integrated circuit encapsulation as claimed in claim 14, wherein said layer has first width, and this first width is less than second width of described silicon wafer.
27. integrated circuit encapsulation as claimed in claim 14, wherein said integrated circuit (IC) wafer comprises bond pad.
28. integrated circuit encapsulation as claimed in claim 1, wherein said layer has first width, and this first width is less than second width of described silicon wafer, and the encapsulation of described integrated circuit also comprises the bond pad of the perimeter that is arranged in described silicon wafer.
29. an integrated circuit encapsulation comprises:
The integrated circuit (IC) wafer that comprises circuit; And
With the C shape layer of the adjacent layout of substrate, make to form the air gap between the described circuit of described C shape layer and described integrated circuit (IC) wafer.
30. integrated circuit encapsulation as claimed in claim 29 also comprises mold material, it encapsulates at least a portion of described C type layer and described integrated circuit (IC) wafer.
31. integrated circuit as claimed in claim 29 encapsulation, wherein said C type layer comprise at least a in glass and the silicon.
32. integrated circuit as claimed in claim 29 encapsulation, wherein said circuit unit comprise at least a in oscillator and the inductor.
33. integrated circuit encapsulation as claimed in claim 32, wherein said inductor comprises spiral inductor.
Applications Claiming Priority (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US71445405P | 2005-09-06 | 2005-09-06 | |
| US60/714,454 | 2005-09-06 | ||
| US60/730,568 | 2005-10-27 | ||
| US60/756,828 | 2006-01-06 | ||
| US11/328,979 | 2006-01-10 | ||
| US11/487,077 | 2006-07-14 | ||
| US11/486,898 | 2006-07-14 | ||
| US11/486,557 | 2006-07-14 | ||
| US11/486,945 | 2006-07-14 | ||
| US11/486,944 | 2006-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1929116A true CN1929116A (en) | 2007-03-14 |
Family
ID=37859005
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610126947 Pending CN1929116A (en) | 2005-09-06 | 2006-09-06 | Integrated circuit including silicon wafer with annealed glass paste |
| CN 200610126949 Expired - Fee Related CN1929117B (en) | 2005-09-06 | 2006-09-06 | Integrated circuit package with glass layer and oscillator |
| CN 200610126948 Pending CN1929308A (en) | 2005-09-06 | 2006-09-06 | Phase locked loop with temperature compensation |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610126949 Expired - Fee Related CN1929117B (en) | 2005-09-06 | 2006-09-06 | Integrated circuit package with glass layer and oscillator |
| CN 200610126948 Pending CN1929308A (en) | 2005-09-06 | 2006-09-06 | Phase locked loop with temperature compensation |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104767487A (en) * | 2014-01-08 | 2015-07-08 | 新唐科技股份有限公司 | Voltage generator, oscillation device and operation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5780045B2 (en) * | 2011-08-08 | 2015-09-16 | 日本電波工業株式会社 | Oscillator |
| US9366718B2 (en) * | 2013-09-12 | 2016-06-14 | Cisco Technology Inc. | Detection of disassembly of multi-die chip assemblies |
| TWI543540B (en) * | 2014-01-06 | 2016-07-21 | 南亞科技股份有限公司 | Integrated circuit and method for adjusting duty cycle thereof |
| CN105099439B (en) * | 2014-05-12 | 2018-05-25 | 瑞昱半导体股份有限公司 | clock generating circuit and method |
| CN105656440B (en) * | 2015-12-28 | 2018-06-22 | 哈尔滨工业大学 | The dual signal output lock-in amplifier that a kind of phase difference is continuously adjusted |
| US11588470B2 (en) * | 2020-02-18 | 2023-02-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6982475B1 (en) * | 1998-03-20 | 2006-01-03 | Mcsp, Llc | Hermetic wafer scale integrated circuit structure |
| JP3985633B2 (en) * | 2002-08-26 | 2007-10-03 | 株式会社日立製作所 | High frequency electronic components using low dielectric loss tangent insulation materials |
| US7042301B2 (en) * | 2002-10-15 | 2006-05-09 | Marvell International Ltd. | Crystal oscillator emulator |
-
2006
- 2006-09-06 CN CN 200610126947 patent/CN1929116A/en active Pending
- 2006-09-06 CN CN 200610126949 patent/CN1929117B/en not_active Expired - Fee Related
- 2006-09-06 CN CN 200610126948 patent/CN1929308A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104767487A (en) * | 2014-01-08 | 2015-07-08 | 新唐科技股份有限公司 | Voltage generator, oscillation device and operation method |
| CN104767487B (en) * | 2014-01-08 | 2018-06-08 | 新唐科技股份有限公司 | Voltage generator, oscillation device and operation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1929117B (en) | 2010-06-16 |
| CN1929117A (en) | 2007-03-14 |
| CN1929308A (en) | 2007-03-14 |
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