CN1925433A

CN1925433A - Signal collecting module with exchanging convergence function

Info

Publication number: CN1925433A
Application number: CN 200510093738
Authority: CN
Inventors: 周文瑞; 刘燕; 朱红军
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2005-08-29
Filing date: 2005-08-29
Publication date: 2007-03-07
Anticipated expiration: 2025-08-29
Also published as: CN100444561C

Abstract

This invention discloses one signal collection module with exchange function, which comprises logic control unit, power time unit, E1 interface unit, signal data extraction unit, communication unit and exchange matrix unit, wherein, the said E1 interface unit is to realize I/O E1 signal linkage conversion and to extract synchronous signals as local board reference clock; through exchange chip to extract unit to the said E1 interface unit as copy linkage output; exchange matrix unit outputs signal linkage any time gap into E1 basic interface circuit.

Description

A kind of signal collecting module with exchanging convergence function

Technical field

The present invention relates to a kind of communication system monitoring signaling device, specifically, is a kind of signal collecting module that is used for the signaling centralized monitoring system.

Background technology

In the prior art, signal collecting module is the nucleus module in the Signaling System Number 7 centralized monitoring system, realization is the data acquisition of HDB3 code signaling link to coded format, data frame head and the postamble removing useless filling information and have nothing to do with signaling message, the Signaling System Number 7 data that collect are analyzed through delivering in the Signaling System Number 7 analytical system after certain processing, as shown in Figure 1.

In Chinese patent CN 00127444.9 " Signaling System Number 7 analyzer ", introduced a kind of method and apparatus that is used for signal collecting and processing, as shown in Figure 2, the ISA module card has the signaling data acquisition function in this patent, can gather the Signaling System Number 7 of any time slot of inter-exchange 64Kbit/s digital channel, this module is made up of E1 basic interface circuit, data acquisition unit, information exchanging channel, logic controller and power supply clock.E1 basic interface circuit connects tested trunk line in the module, translation interface sign indicating number type, and Clock Extraction and timing again receive signaling data, and a module card has 4 E1 basic interface circuit, 4 monitored signaling links of alignment processing; Data acquisition unit is connected between information exchanging channel and the E1 basic interface circuit, receive the signaling data that E1 basic interface circuit transmits, control E1 basic interface circuit is finished transmitting-receiving, filtration, the buffer memory of signaling data and the signaling data that receives by the information exchanging channel transmission to the PC main frame; Information exchanging channel is used for PC main frame and data acquisition unit exchange of control information and large-scale data and transmits, and is made up of push-up storage FIFO, Double Port Random Memory DPRAM; Described push-up storage FIFO is used for large-scale data transmission between PC main frame and digital processing unit, and described Double Port Random Memory DPRAM is used for PC main frame and data acquisition unit exchange of control information; Programmable logic controller (PLC) is made up of programmable logic device EPLD, for each working cell provides needed control signal; Clock power provides data acquisition unit and required clock and the required power supply of module of basic interface circuit.

Development along with the Signaling System Number 7 centralized monitoring system, a kind of like this demand appears, in being connected to the E1 signaling link of acquisition module, only need the data of part of links to be gathered, and the data link of being gathered can be according to circumstances, therefore change in real time must seek the signal collecting module that possesses the link exchanging convergence function; Because the signaling link that some Engineering Bureau wish to insert except giving this centralized monitoring system, also needs signaling link is copied to other monitoring systems or makes other purposes, so link duplicates the necessary function that output function also becomes signal collecting module.And in the prior art of existing disclosed signal collecting module, have only the signal collecting function and do not possess link convergence and link duplicates output function.

Therefore, prior art has yet to be improved and developed.

Summary of the invention

Technical problem to be solved by this invention provides a kind of signal collecting module with exchanging convergence function, for satisfying the needs of Signaling System Number 7 centralized monitoring system development, except that possessing basic signaling link acquisition function, possesses link convergence simultaneously and link duplicates output function, can finish the exchanging convergence of 8 E1 basic interface circuit, any time slot of reproducible any 8 E1 input link signals outputs to 2 E1 link output ports.

Technical scheme of the present invention comprises:

A kind of signal collecting module with exchanging convergence function, it comprises logic control element, power supply clock unit; Described logic control element is realized by programmable logic device EPLD, is used to each unit of described signal collecting module that sheet choosing and read-write control signal are provided; Described power supply clock unit is used to each unit of described signal collecting module that power supply and clock synchronizing function are provided, and wherein, described signal collecting module also comprises:

E1 interface unit, signaling data extraction unit, communication unit and switching matrix unit;

Described E1 interface unit is used to realize the E1 signal link code conversion of input and output, and extracts the line synchronization signal as this plate reference clock;

Described switching matrix unit is used to finish convergence exchange and copy function, be input to this switching matrix unit from described E1 interface unit, through its exchange chip convergence exchange, two paths of signals is transferred to described signaling data extraction unit and is handled, two paths of signals is passed described E1 interface unit back as being replicated link output, and any time slot of the signal link of switching matrix unit output is from any time slot of the E1 basic interface circuit of input.

Described module, wherein, described signaling data extraction unit includes the HDLC framer, and its Multi Channel Controller is used to realize the data extract of 2 2Mbit/s or 64 64Kbit/s channel Signaling System Number 7 source codes, and will be temporarily stored in onboard memory after the effective signaling data packing.

Described module, wherein, described communication unit is the interface of this signal collecting module and Signaling System Number 7 analytical system, form by Double Port Random Memory, when in the onboard memory signaling data being arranged, processor can be moved communication unit with packet, is used in the primary processor card taking turn of described Signaling System Number 7 analytical system when communication unit has the signaling data bag, packet is taken away through the backboard isa bus analyzed or data are write file operation.

Described module, wherein, described E1 interface unit is converted to the NRZ nonreturn to zero code to HDB3 three rank high density polar codes at input direction, outbound course then is converted to HDB3 three rank high density polar codes to the NRZ nonreturn to zero code, and is input to described switching matrix unit from the NRZ nonreturn to zero code that described E1 interface unit comes out.

A kind of signal collecting module provided by the present invention with exchanging convergence function, compared with prior art, except that possessing basic signaling link acquisition function, possesses link convergence simultaneously and link duplicates output function, can finish the exchanging convergence of E1 basic interface circuit, and any time slot of reproducible any 8 E1 input link signals outputs to 2 E1 link output ports, satisfied the needs of centralized monitoring system.

Description of drawings

Fig. 1 is the position view of signal collecting module in the Signaling System Number 7 acquisition system of prior art;

Fig. 2 is the Signaling Analyzer block diagram of prior art;

Fig. 3 has the signaling link data flow block diagram of the signal collecting module of exchanging convergence function for the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in further detail.

Signal collecting module with exchanging convergence function of the present invention as shown in Figure 3, mainly comprises following components: E1 interface unit, switching matrix unit, signaling data extraction unit, communication unit, logic control element, power supply clock unit etc.

Wherein, described E1 interface unit is used to realize the E1 signal link code conversion of input and output, input direction is converted to the NRZ nonreturn to zero code to HDB3 three rank high density polar codes, outbound course then is converted to HDB3 three rank high density polar codes to the NRZ nonreturn to zero code, and extracts the line synchronization signal as this plate reference clock.

Convergence exchange and copy function are finished in described switching matrix unit, from the NRZ nonreturn to zero code input switching matrix unit that described E1 interface unit comes out, through exchange chip convergence exchange, two paths of signals is transferred to described signaling data extraction unit and is handled, two paths of signals is passed described E1 interface unit back as being replicated link output, and any time slot of the signal link of switching matrix unit output can be from any time slot of eight E1 basic interface circuit importing.

Described signaling data extraction unit includes the HDLC framer, its distinctive QMC (Multi Channel Controller) can realize 2 2Mbit/s or the data extract of 64 64Kbit/s channel Signaling System Number 7 source codes, this unit effective signaling data is packed (adding time label etc.) be temporarily stored in the onboard memory.

Described communication unit is the interface of this module and Signaling System Number 7 analytical system, DPRAM forms by Double Port Random Memory, when in the onboard memory signaling data being arranged, processor can be moved communication unit with packet, the primary processor card taking turn of Signaling System Number 7 analytical system has the signaling data bag in communication unit, can take packet operations such as away analyzing or data are write file through the backboard isa bus.

Described logic control element is realized by programmable logic device EPLD, for each E1 interface unit, exchange matrix unit and communication unit provide sheet choosing and read-write control signal.

Described power supply clock unit provides power supply and clock synchronizing function for each unit of module.

Shown in Figure 1 identical with prior art, signaling link between SP1 and the SP2 generally is the E1 link, for avoiding influencing the transmission of messages of normal signaling link, by the high resistant spacer assembly E1 signal is coupled to described signal collecting module, because the signal that the high resistant spacer assembly gets off is very weak, so the E1 interface unit should have high resistant receiving ability preferably.

The core of described E1 interface unit is the E1 interface chip, also comprise transformer and lightning protection anti electrostatic device etc., the E1 interface chip is realized HDB3 three rank high density polar codes are converted to NRZ nonreturn to zero code HW, then signal is delivered to the switching matrix unit, extract frame synchronizing signal in the circuit simultaneously as the frame synchronization of whole module, this module provides 8 tunnel input e1 ports, realizes the conversion of 8 road E1 signals, as shown in Figure 3.

8 road E1 input link signals converge to 2 road output links through the switching matrix unit and deliver to the signaling data extraction module, also reproduciblely export to 2 road output ports, through the physical form output of E1 interface unit, gather or duplicate any time gas exchange of 8 road E1 input link signals that all time slots of the output signal of output all can be by input or duplicate with the E1 interface.

In the modular device of the present invention, 2 road HW that are used to gather are input to the Multi Channel Controller of signaling data extraction unit can be by the mode configuration logic passage of appointment, both can be configured to the high-speed digital logic channel of 2Mbit/s, also can be configured to the ordinary numbers logic channel of 64Kbit/s.After configuring this controller with the link form of reality, each logic channel just has a flag bit, this flag bit is used for identifying this logic channel and whether receives the signaling frame data, each logic channel has one section application heap separately to be used for depositing the data of oneself, CPU only needs the flag bit of each logic channel of taking turn, find that certain logic channel received data, just data are copied out and remove check code from the application heap of this logic channel, add in the internal memory ring that is temporarily stored in oneself definition after the additional information such as time tag, finish the extraction and the package process of signaling frame data.

Described signaling data extraction unit is when extracting frame data, processor writes communication unit to the data of internal memory ring, communication unit is established a flag bit, after data write communication unit with this flag bit set, after the primary processor card taking turn of Signaling System Number 7 analytical system is found to be set to flag bit, then take the signaling data bag in the communication unit away, fall the flag bit in the communication unit then clearly, the efficient signaling data just are delivered in the Signaling System Number 7 analytical system in real time like this.

In specific implementation module of the present invention, what described E1 interface chip was selected for use is the DS21Q50 chip, and this chip has outstanding high resistant receiving ability, and single-chip can be handled 4 road E1 signals, and module uses 2 DS21Q50 can handle 8 road E1 signals; The exchange chip that described switching matrix unit uses is MT90820, this chip can be realized the switching network of 2048*2048 64Kbit/s size, this part be exactly module of the present invention the unit of exclusive design, just because of the existence of this element makes module of the present invention have convergence exchange and link copy function.

That described data extracting unit is selected for use is the XPC860T of Motolola company, and this chip has abundant communication interface and powerful internal communication coprocessor, and dominant frequency is operated in 66MHZ, has to support the nearly Multi Channel Controller of 64 logical channels.The chip that described communication unit adopts is the CY7C0241 of Cypress company, and this chip capacity size is the 4K byte; Described logical block adopts the programmable logic device EPM7128 of altera corp.This realization module can be gathered the nearly data of 32 signaling links, can supply output for any time slot to 2 E1 link of gathering and duplicate wherein from importing the HW output of 8 E1 signaling link exchanging convergences to 2.

This Module Design thought and implementation method also can be applicable to the other types data collecting field except that being applied to signaling data collection field.Simultaneously, should be pointed out that in the above-mentioned specific embodiment comparatively detailed to each unit specific implementation, but can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.

Claims

1, a kind of signal collecting module with exchanging convergence function, it comprises logic control element, power supply clock unit; Described logic control element is realized by programmable logic device EPLD, is used to each unit of described signal collecting module that sheet choosing and read-write control signal are provided; Described power supply clock unit is used to each unit of described signal collecting module that power supply and clock synchronizing function are provided, and it is characterized in that described signal collecting module also comprises:

2, module according to claim 1, it is characterized in that, described signaling data extraction unit includes the HDLC framer, its Multi Channel Controller is used to realize the data extract of 2 2Mbit/s or 64 64Kbit/s channel Signaling System Number 7 source codes, and will be temporarily stored in onboard memory after the effective signaling data packing.

3, module according to claim 2, it is characterized in that, described communication unit is the interface of this signal collecting module and Signaling System Number 7 analytical system, form by Double Port Random Memory, when in the onboard memory signaling data being arranged, processor can be moved communication unit with packet, is used in the primary processor card taking turn of described Signaling System Number 7 analytical system when communication unit has the signaling data bag, packet is taken away through the backboard isa bus analyzed or data are write file operation.

4, module according to claim 1, it is characterized in that, described E1 interface unit is converted to the NRZ nonreturn to zero code to HDB3 three rank high density polar codes at input direction, outbound course then is converted to HDB3 three rank high density polar codes to the NRZ nonreturn to zero code, and is input to described switching matrix unit from the NRZ nonreturn to zero code that described E1 interface unit comes out.