Background technology
Composite crystal structure is now used the base material as semiconductor technology or micro electronmechanical technology widely, for example, and silicon on the insulating barrier (Silicon-on-insulator, SOI) structure.Be example promptly below, composite crystal structure normal edge damage that takes place in manufacture process is described thus with a typical soi structure.
Please refer to Fig. 1, the cross sectional view of typical soi structure 1 is depicted among Fig. 1.Soi structure 1 comprises device wafer (Device wafer) 12 and submount wafer (Base wafer) 14 basically.
As shown in Figure 1, device wafer 12 has composition surface (Bond surface) 122 and basal surface (Bottom surface) 124.About the technology of soi structure 1, device wafer 12 engages with the top surface (Top surface) 142 of submount wafer 14 with the composition surface 122 of itself.Especially, on the composition surface 122 of device wafer 12, and/or on the top surface 142 of submount wafer 14, form silicon oxide layer 16 in advance.In Fig. 1, be formed at silicon oxide layer 16 on the top surface 142 of submount wafer 14 as illustrative examples.In addition, also can carry out annealing in process (Annealing treatment), to improve the bond strength (Bonding strength) between device wafer 12 and the submount wafer 14 to the device wafer 12 and the submount wafer 14 that have engaged.Generally speaking, the basal surface 124 of device wafer 12 all can impose chemico-mechanical polishing again (Chemical mechanical polishing, CMP) technology are thinned to an expectation thickness until the original depth of device wafer 12.
Yet, because the restriction on technology board itself is proofreaied and correct, at device wafer 12 with after submount wafer 14 engages, more or less, the composition surface 122 of device wafer 12 can leave the zone that does not engage with the top surface 142 of submount wafer 14, and causes device wafer 12 corresponding edge parts to be divided into vacant state.In the process of subsequently basal surface 124 of device wafer 12 being ground with the thickness of attenuate device wafer 12, the load (Load) that the marginal portion of above-mentioned device wafer 12 applies because of bearing grinder station, and then the fracture do not expect, just so-called edge damage (shown in label among Fig. 1 126) take place.Above-mentioned edge damage is to the influence of soi structure, and the lighter then allows the utilized area of soi structure in follow-up semiconductor integrated circuit technique reduce, and causes waste of material; Weight person then allows the decrease in yield of soi structure on volume production.It should be noted that the problem of above-mentioned edge damage, on the similarly as easy as rolling off a log composite crystal structure that betides other type.
Single with regard to soi structure, about reduce the research aspect the probability that edge damage takes place soi structure in manufacture process, have document quite a lot and be disclosed.Now case is listed below before will being correlated with: United States Patent (USP) the 5th, 823, No. 325; United States Patent (USP) the 6th, 541, No. the 6th, 717,217, No. 356 and United States Patent (USP).
Yet, by understanding, can be clear that prior art all from passive Fracture Control (Passive fracture control) viewpoint to prior art, that is to say and avoid the generation of rupturing as far as possible.But use prior art composite crystal structure is carried out volume production, edge damage is not to guarantee can not take place.In addition, some prior aries have also increased technologic complexity.
Be different from prior art, the manufacture method of the disclosed composite crystal structure of the present invention, it is from Fracture Control (Active fracture control) viewpoint initiatively, that is to say that fracture (being different from the fracture that causes edge damage) must take place, and can Be Controlled and help the integrated artistic of composite crystal structure.
Embodiment
The present invention is providing a kind of method of making composite crystal structure, and especially, rupturing in this composite crystal manufacture process is actively controlled, and then avoids composite crystal structure generation edge damage.Several preferred specific embodiments according to the present invention disclose as follows.
Please refer to shown in Fig. 2 A to Fig. 2 H, Fig. 2 A to Fig. 2 H is a cross sectional view, is used to describe the manufacture method according to the of the present invention first preferred specific embodiment.
At first, shown in Fig. 2 A, fabricate devices wafer 22.Device wafer 22 has first circumference (Circumference) 221, composition surface 222 and basal surface 224.
Then, on the composition surface 222 of device wafer 22,, form groove (Groove) 226, shown in Fig. 2 B along first circumference 221 of this device wafer 22.Be noted that between first circumference 221 of groove 226 and device wafer 22, to have a border (Margin) 228.The width on border 228 is d1.
In fact, the cross section of groove 226 can become the V font, maybe can improve other shape of the fatiguestrength reduction factor of itself tip (Tip) locating (Stress concentration factor).
In one embodiment, groove 226 can form by mechanical processing technique, laser cutting parameter, etch process or water cutter cutting technique.
Subsequently, preparation submount wafer 24 is shown in Fig. 2 C.Submount wafer 24 has second circumference 241 and top surface 242.
In addition, can look actual demand, on the top surface 242 of submount wafer 24, and/or on the composition surface 222 of device wafer 22, form oxide layer (Oxidized layer) in advance.At this, only on the top surface 242 of submount wafer 24, to form oxide layer 26 as illustrative examples, shown in Fig. 2 D.
Subsequently, device wafer 22 engages with the top surface 242 of submount wafer 24 with the composition surface 222 of itself, shown in Fig. 2 E.In addition, also can carry out annealing in process, to improve the bond strength between device wafer 22 and the submount wafer 24 to the device wafer 22 and the submount wafer 24 that have engaged.Before the composition surface 222 of this device wafer 22 was engaged to the top surface 242 of submount wafer 24, a plasma surface treatment can put on the composition surface 222 of device wafer 22 and the top surface 242 of submount wafer 24 in advance.Thus, the bond strength between device wafer 22 and the submount wafer 24 can improve, and the temperature that subsequent anneal is handled is also unlikely too high.
Be noted that because the restriction in technology board itself correction, with after submount wafer 24 engages, the composition surface 222 of device wafer 22 can leave the zone that does not engage with the top surface 242 of this submount wafer 24 at device wafer 22.Shown in Fig. 2 E, the maximum radial distance on the not engaging zones of the top surface 242 of submount wafer 24 (Maximum radial distance) is defined as one and does not mate spacing (Mismatch gap) d2.In actual applications, the width d1 on border 228 must be equal to or greater than and not mate spacing d2.That is to say,, depend on that its associated process conditions of technology board cooperates following the maximum of not mating spacing that may cause for the design of the width on this border.The width on this border must be equal to or greater than the maximum of not mating spacing, to guarantee that at device wafer 22 with after submount wafer 24 engages, groove 226 integral body all can be positioned on the submount wafer 24.
Then, the basal surface 224 of device wafer 22 is carried out grinding, glossing, for example, CMP technology is until the original depth T of device wafer 22
IniBe thinned to the expectation thickness T
Exp, and then finish composite crystal structure 2, shown in Fig. 2 H.
Especially, shown in Fig. 2 F, during grinding and polishing the basal surface 224 of device wafer 22, because place, the tip of groove 226 has the high stress concentrations factor, crackle (Cracks) must cause in place, tip at groove 226, crackle can grow up, transmit substantially towards the direction of vertical basal surface 224, and then causes the fracture on border 228.At this moment, the residual thickness T of device wafer 22
rBetween original depth T
IniWith the expectation thickness T
ExpBetween.During the grinding that continues, be not thinned to the expectation thickness T as yet at the thickness of device wafer 22
ExpBefore, the border 228 of having ruptured promptly can break away from device wafer 22, and is removed, shown in Fig. 2 G.
In addition,, further can carry out grinding technics or laser cutting parameter, equal the diameter of device wafer 22 until the diameter reduction of submount wafer 24 second circumference 241 of submount wafer 24 according to the manufacture method of the of the present invention first preferred specific embodiment.
In one embodiment, device wafer 22 is all made by semi-conducting material with submount wafer 24, to form so-called homojunction combined chip architecture.For example, when application was made soi structure according to the manufacture method of the of the present invention first preferred specific embodiment, device wafer and submount wafer all were fabricated from a silicon.
In another specific embodiment, device wafer 22 is made by first semi-conducting material, and submount wafer 24 made by second semi-conducting material that is different from first semi-conducting material, to form so-called Heterogeneous Composite chip architecture.For example, second semi-conducting material is silicon (Si) material, and first semi-conducting material can be SiGe (SiGe) material, lithium niobate (LiNbO3) material, sapphire (Sapphire) material or oxide (Oxide) material.
Please refer to shown in Fig. 3 A to Fig. 3 I, it is a cross sectional view, is used to describe the manufacture method according to the of the present invention second preferred specific embodiment.
At first, as shown in Figure 3A, fabricate devices wafer 32.Device wafer 32 has first circumference 321, composition surface 322 and basal surface 324.
Then, shown in Fig. 3 B, carry out hydrogen ion injection (Hydrogen ion implantation) technology at a distance of the zone on border 328 along first circumference 321 of device wafer 32 and with first circumference 321, make that in this location hydrogen ion flows into device wafer 32 certainly nearly composition surfaces 322 to composition surface 322 next desired depth d
PreIn.The width on border 328 is d1.
Subsequently, preparation submount wafer 34 is shown in Fig. 3 C.Submount wafer 34 has second circumference 341 and top surface 342.
In addition, can look actual demand, on top surface 342, and/or on the composition surface 322 of this device wafer 32, form an oxide layer in advance in submount wafer 34.At this, only on the top surface 342 of submount wafer 34, to form oxide layer 36 as illustrative examples, shown in Fig. 3 D.
Subsequently, device wafer 32 engages with the top surface 342 of submount wafer 34 with the composition surface 322 of itself, shown in Fig. 3 E.
Be noted that because the restriction in technology board itself correction, with after submount wafer 34 engages, the composition surface 322 of device wafer 32 can leave the zone that does not engage with the top surface 342 of submount wafer 34 at device wafer 32.Shown in Fig. 3 E, the maximum radial distance on the not engaging zones of the top surface 342 of submount wafer 34 is defined as one and does not mate spacing d2.In actual applications, the width d1 on border 328 must be equal to or greater than and not mate spacing d2.That is to say,, depend on that its associated process conditions of technology board cooperates following the maximum of not mating spacing that may cause for the design of the width on this border.The width on this border must be equal to or greater than the maximum of not mating spacing, to guarantee that at device wafer 32 with after submount wafer 34 engages, device wafer 32 has the hydrionic regional integration of injection and all can be positioned on the submount wafer 34.
Subsequently, to device wafer 32 and the submount wafer 34 that has engaged, carry out annealing in process, cause the hydrogen ion that has injected to be gathered into little pore (Micro voids) 326, and be distributed in these device wafer 32 certainly nearly composition surfaces 322 to 322 times desired depth d of composition surface
PreIn, shown in Fig. 3 F.At this moment, also can be by the control on the temperature, and then improve bond strength between device wafer 32 and the submount wafer 34.Before the composition surface 322 of device wafer 32 was engaged to the top surface 342 of submount wafer 34, plasma surface treatment can put on the composition surface 322 of device wafer 32 and the top surface 342 of submount wafer 34 in advance.Thus, the bond strength between device wafer 32 and the submount wafer 34 can improve, and the temperature that subsequent anneal is handled is also unlikely too high.
Then, the basal surface 324 of device wafer 32 is carried out grinding, glossing, for example, CMP technology is until the original depth T of device wafer 32
IniBe thinned to the expectation thickness T
Exp, and then finish this composite crystal structure 3, shown in Fig. 3 I.
Especially, shown in Fig. 3 G, during grinding and polishing the basal surface 324 of device wafer 32, because little pore 326 can't bear the load that grinder station imposes, around little pore 326, must cause crackle, and because the distribution of little pore, crackle can grow up, transmit substantially towards the direction of vertical basal surface 324, and then causes the fracture on border 328.At this moment, the residual thickness T of device wafer 32
rBetween original depth T
IniWith the expectation thickness T
ExpBetween.During the grinding that continues, be not thinned to the expectation thickness T as yet at the thickness of device wafer 32
ExpBefore, the border 328 of having ruptured promptly can break away from this device wafer 32, and is removed, shown in Fig. 3 H.
In addition,, further can carry out grinding technics or laser cutting parameter, equal the diameter of device wafer 32 until the diameter reduction of submount wafer 34 second circumference 341 of submount wafer 34 according to the manufacture method of the of the present invention second preferred specific embodiment.
In one embodiment, device wafer 32 is all made by a kind of semi-conducting material with submount wafer 34, to form so-called homojunction combined chip architecture.For example, when application was made soi structure according to the manufacture method of the of the present invention second preferred specific embodiment, device wafer and submount wafer all were fabricated from a silicon.
In another specific embodiment, device wafer 32 is made by first semi-conducting material, and submount wafer 34 made by second semi-conducting material that is different from first semi-conducting material, to form so-called Heterogeneous Composite chip architecture.For example, second semi-conducting material is silicon (Si) material, and first semi-conducting material can be SiGe (SiGe) material, lithium niobate (LiNbO
3) material, sapphire (Sapphire) material or oxide (Oxide) material.
Significantly, be different from prior art, the manufacture method of composite crystal structure disclosed in this invention, it controls fracture (being different from the fracture that causes edge damage) on one's own initiative and effectively, thus, this composite crystal structure edge damage that after finishing, can not take place not expect.Also therefore, manufacturing method according to the invention helps to improve the rate of finished products of composite crystal structure on industrial production.
By the detailed description of above preferred specific embodiment, hope can be known description feature of the present invention and spirit more, and is not to come scope of the present invention is limited with above-mentioned disclosed preferred specific embodiment.On the contrary, its objective is that hope can contain in the scope that is arranged in claim of the present invention that various changes and tool be equal to.