CN1921572A - XY address type solid-state imaging device - Google Patents
XY address type solid-state imaging device Download PDFInfo
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- 238000003384 imaging method Methods 0.000 title claims description 22
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- 239000003990 capacitor Substances 0.000 description 51
- 238000012546 transfer Methods 0.000 description 37
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- 101100042610 Arabidopsis thaliana SIGB gene Proteins 0.000 description 20
- 101100294408 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MOT2 gene Proteins 0.000 description 15
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- 101100042613 Arabidopsis thaliana SIGC gene Proteins 0.000 description 6
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- 101100428771 Arabidopsis thaliana VSR3 gene Proteins 0.000 description 6
- 101100421503 Arabidopsis thaliana SIGA gene Proteins 0.000 description 5
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Abstract
A plurality of pixels that are arranged two-dimensionally, a horizontal scanning circuit and a vertical scanning circuit that output a signal for reading out an accumulated charge in the pixel, and a multiplexer circuit that supplies a control signal to elements constituting each of the pixels based on the signal outputted from the vertical scanning circuit are provided. The vertical scanning circuit is used singly to output a scanning signal for reading out the accumulated charge and a scanning signal for clearing the accumulated charge in the pixel, and the multiplexer circuit is used singly to supply an accumulated charge readout signal and an accumulated charge clearing signal as the control signal based on the scanning signal for reading out the accumulated charge and the scanning signal for clearing the accumulated charge. One vertical scanning circuit is used for both scanning for reading out an accumulated charge and scanning for clearing the accumulated charge, and one multiplexer is used for outputting both an accumulated charge readout signal and an accumulated charge clearing signal, thus allowing a reduction of a chip area and an improvement in an operation yield.
Description
Technical field
The present invention relates to a kind of a plurality of pixels and the level of the stored charge that is used for read pixel and the XY address type solid-state imaging device of vertical scanning circuit that possess two-dimensional arrangements.Especially, the present invention relates to realize the improvement of circuit miniaturization, 1 vertical scanning circuit can be used for stored charge reads with scanning and stored charge removing scanning, and, 1 multiplexer can be used for stored charge and read the output of using signal with signal and stored charge removing.
Background technology
In solid photographic device, for the circuit of MOS type imageing sensor, known for example have a special structure shown in Figure 5 of opening the 2003-46864 communique.In Figure 16, show the circuit block diagram of MOS type image sensor circuit identical with the content put down in writing in the document, the existing example of expression.
In Figure 16, each pixel that is arranged in pixel portions 1 comprises photodiode PD, transmission transistor TRa, reset transistor TRb, amplifier transistor TRc and row selecting transistor TRd.Read multi-channel conversion circuit 2, electronics shutoff multi-channel conversion circuit 3, vertical row scanning circuit 4 and electronics from electric charge and turn-off scanning circuit 5 to each pixel portions 1 supply control impuls, the electric charge of controlling the photodiode PD generation of each pixel 1 reads.The electric charge that reads is supplied with output amplifier 8 based on the work of horizontal line scanning circuit 7 after being handled by noise canceller circuit 6.Timing generation circuit 9 generation source electrode power supply power supply voltage signal SCEL, load signal LGCEL and sampling keep pulse SHNC and supply with to pixel portions 1, and the reset pulse ERESET that control transmits pulse TRAN, reset pulse RESET, the transmission pulse ETRAN when electronics turn-offs and electronics when turn-offing, and the generation of row selection signal VSEL regularly.
Read work owing to read the stored charge that multi-channel conversion circuit 2 etc. carries out pixel by vertical row scanning circuit 4, electric charge, therefore, reset pulse RESET outputs to reset transistor TRb, transmit pulse TRAN and output to transmission transistor TRa, row selection signal VSEL outputs to row selecting transistor TRd.In addition, carry out the stored charge elimination work of pixel in order to turn-off scanning circuit 5, electronics shutoff multi-channel conversion circuit 3 etc. through electronics, reset pulse EREST when electronics turn-offs outputs to reset transistor TRb, and the transmission pulse ETRAN when electronics turn-offs outputs to transmission transistor TRa.
Figure 17 shows the work schedule of the solid photographic device of Figure 16.At moment TO, apply the fixed voltage of regulation as load signal LGCEL.At moment T1, connect row selection signal VSEL and reset pulse RESET, remove the electric charge of photodiode PD.At moment T2, when reset pulse RESET turn-offs, the reference voltage of output pixel signal, the reset level clamp of execution picture element signal V0.At moment T3, conducting transmits pulse TRAN, the stored charge of transmission photodiode PD; When moment T4 turn-offed, output was by the current potential of the stored charge signal deciding of pixel.(T1～T5) signal with these current potentials transmits to the noise canceller circuit 6 of Figure 16 during sampling keeps pulse SHNC to connect.
Then, under the state of row selection signal VSEL for shutoff, at moment T7, the reset pulse ERESET when electronics is turn-offed connects; At moment T8, turn-off; At moment T9, connect and transmit pulse ETRAN; T10 turn-offs in the moment, thus, with the stored charge signal removal of pixel to power vd D (with reference to Figure 16).
So, the combination of reading multi-channel conversion circuit 2 by vertical row scanning circuit 4 and electric charge, the stored charge that generates pixel reads each signal of usefulness, and by the combination that electronics turn-offs scanning circuit 5 and electronics shutoff multi-channel conversion circuit 3, the stored charge that generates pixel is removed each signal of usefulness.
Describe the circuit working of the MOS type imageing sensor of Figure 16 in detail.Figure 18 is an example that constitutes the shift register of vertical row scanning circuit 4 or electronics shutoff scanning circuit 5.Its work schedule shown in Figure 19.At first, at moment T0, conducting the 2nd scanning impulse V2; Turn-off at moment T1.Thus, the capacitor C01 of Figure 18 charges to power vd D with the GND benchmark through transistor T R01, TR02.At moment T2, conducting the 1st scanning impulse V1 and displacement starting impulse ST.Thus, because capacitor C01 boosts, displacement starting impulse ST just is not subjected to the influence of the decay that the threshold voltage of transistor T R1 causes, C02 charges to capacitor.At the moment T3 displacement starting impulse ST is closed and have no progeny,,, just the 1st scanning impulse 1 is exported as the SIG1 pulse so be not subjected to the influence of the decay that the threshold voltage of transistor T R2 causes because capacitor C02 boosts.At moment T4, before the 1st scanning impulse V1 turn-offs, output SIG1 pulse.Have again, owing to boost,, just the capacitor C03 of subordinate is charged by power vd D so be not subjected to the influence of the decay that the threshold voltage of transistor 3 causes at moment T3 Container C02.
When moment T5 conducting the 2nd scanning impulse V2, be not subjected to the influence of the decay that the threshold voltage of transistor T R4 causes, just the 2nd scanning impulse 2 is exported as the SIG2 pulse.The SIG2 pulse supplies to elementary transistor T R04, and the electric charge of capacitor C02 is released.Below, similarly, be synchronized with the 1st scanning impulse V1 and the 2nd scanning impulse V2, export the SIG pulse successively from shift register.
Figure 20 represent in the MOS type image sensor circuit of Figure 16, constitute that each shift register, electric charge that vertical row scanning circuit 4 and electronics turn-off scanning circuit 5 read multi-channel conversion circuit 2 and electronics turn-offs multi-channel conversion circuit 3.With regard to shift register, show the vertical transfer register 4a～4c at different levels of vertical row scanning circuit 4 and shutoff shift register 5a～5c at different levels that electronics turn-offs scanning circuit 5.Through transistor T R5, the output at different levels of shift register supplied to electric charge reads multi-channel conversion circuit 2 and electronics turn-offs multi-channel conversion circuit 3.
Combination by reading multi-channel conversion circuit 2 by the SIG1～SIG3 pulse of output such as vertical transfer register 4a～4c etc. successively etc. and electric charge generates reset pulse RESET, transmits pulse TRAN and row selection signal VSEL, transmits to pixel.Similarly,, generate reset pulse ERESET and transmit pulse ETRAN, transmit to pixel by by turn-offing the ESIG1～ESIG3 pulse etc. of output and the combination that electronics turn-offs multi-channel conversion circuit 3 successively such as shift register 5a～5c.
Figure 21 A, Figure 21 B show the circuit working sequential of Figure 20.Figure 21 A represents the work schedule of shift register, and Figure 21 B represents the work schedule of multi-channel conversion circuit.Have again, though be marked with identical moment symbol among Figure 21 A and Figure 21 B, and do not mean that synchronization.During shown in Figure 21 B, the SIG/ESIG waveform shown in its higher level is equivalent to 1 SIG/ESIG impulse duration among Figure 21 A.In Figure 21 A, VST is that the electric charge that is input to vertical transfer register 4 reads with the displacement starting impulse, and SHTST is input to the electric charge removing starting impulse that electronics turn-offs scanning circuit 5.In Figure 21 B, VDRV is a vertical drive pulse.The work schedule of the shift register shown in Figure 21 A identical with shown in Figure 19 is so omit its explanation.
At first, illustrate that in the work schedule of multi-channel conversion circuit, vertical transfer register 4a～4c and electric charge read the combination of multi-channel conversion circuit 2.At moment TO, conducting SIG1 pulse and vertical drive pulse VDRV, the current potential by the SIG1 pulse charges to capacitor C10, C11, C12.At moment T1, vertical drive pulse VDRV is closed have no progeny, at moment T2, conducting reset pulse RESET and row selection signal VSEL.Thus, because capacitor C10 and capacitor C12 boost,, just transmit reset pulse RESET and row selection signal VSEL to pixel portions so be not subjected to the influence of the decay that the threshold voltage of transistor T R10 and transistor T R12 causes.After moment T3 turn-offs reset pulse RESET, the reference potential of the signal of output pixel.When moment T4 conducting transmits pulse TRAN, be not subjected to the influence of the decay that the threshold voltage of transistor T R11 causes, just to pixel portions transmission transmission pulse TRAN.Make the moment of transmitting pulse TRAN shutoff at moment T5, output is by the current potential of the stored charge signal deciding of pixel.During sampling maintenance pulse SHNC connection (constantly from T2 to T6), with of noise canceller circuit 6 transmission of these signals to Figure 16.So far, the storage signal that is configured in the pixel of first row reads end-of-job.For other row, also be identical.
The work of the combination of turn-offing shift register 5a～5c and electronics shutoff multi-channel conversion circuit 3 then, is described.At moment TO, ESIGI1 pulse and vertical drive pulse VDRV connect, to the current potential of capacitor C13, C14 charging RESIG1 pulse.At moment T1, vertical drive pulse VDRV is closed have no progeny, when when moment T8 connects reset pulse ERESET, then capacitor C 13 is boosted.Thus, be not subjected to the influence of the decay that the threshold voltage of transistor T R13 causes, just to pixel portions transmission reset pulse ERESET.Make after reset pulse ERESET turn-offs at moment T9,, be not subjected to the influence of the decay that the threshold voltage of transistor T R14 causes, just to pixel portions transmission transmission pulse ETRAN when connecting at moment T10 when transmitting pulse ETRAN.So far, be configured in the elimination end-of-job of the stored charge signal of first pixel of going to power supply.For other row, also be identical.
Other structure of existing MOS type image sensor circuit then, is described with reference to Figure 22.The structure of this circuit is that the transistor that constitutes each pixel of pixel portions 1a is 3 transistorized situations, to the drain line of pixel portions 1a supply power not, but supplies with common source potential pulse VDDCEL.Thus, do not use the row selection signal VSEL of Figure 16, stored charge that just can read pixel.For the inscape identical, pay identical Reference numeral, and the repetitive description thereof will be omitted with Figure 16.
The work schedule of the MOS type image sensor circuit of Figure 22 has been shown among Figure 23.At moment T0, connect common source potential pulse VDDCEL, load signal LGCEL and reset pulse RESET.At the moment T1 that turn-offs reset pulse RESET, the reference potential of output pixel signal.Connect transmission pulse TRAN at moment T2, when moment T3 turn-offed, output was by the current potential of the stored charge signal deciding of pixel.During sampling maintenance pulse SHN connection, the signal of these current potentials is transferred to the noise canceller circuit 6 of Figure 22.
Then, load signal LGCEL is turn-offed, and common source potential pulse VDDCEL is turn-offed at moment T4; Make reset pulse RESET connect, turn-off at moment T5, T6, make row be selected to nonselection mode.After this, under the state that load signal LGCEL still turn-offs, the reset pulse ERESET when moment T7, T8 turn-off electronics connects, turn-offs; Make transmission pulse ETRAN connect, turn-off at moment T9, T10, remove the stored charge signal of pixel thus.
So, the combination of reading multi-channel conversion circuit 2a by vertical row scanning circuit 4 and electric charge, the stored charge that generates pixel reads each signal of usefulness, and by the combination that electronics turn-offs scanning circuit 5 and electronics shutoff multi-channel conversion circuit 3, the stored charge that generates pixel is removed each signal of usefulness.
Figure 24 represents that each shift register, electric charge that formation vertical row scanning circuit 4 in the MOS type image sensor circuit of Figure 22 and electronics turn-off scanning circuit 5 read multi-channel conversion circuit 2a and electronics turn-offs multi-channel conversion circuit 3.Pay identical Reference numeral for the key element identical with multi-channel conversion circuit, and the repetitive description thereof will be omitted with the shift register shown in Figure 20.
By the combination of SIG1～3 pulses of exporting in proper order etc. and multi-channel conversion circuit 2a, to pixel transmission reset pulse RESET with transmit pulse TRAN from vertical transfer register 4a～4c.Similarly, by from the combination of turn-offing ESIG1～ESIG3 pulse that shift register 5a～5c exports in proper order etc. and electronics turn-offs multi-channel conversion circuit 3, to pixel transmission reset pulse ERESET with transmit pulse ETRAN.
The work schedule of the circuit of Figure 24 has been shown among Figure 25 A, Figure 25 B.Figure 25 A represents the work schedule of shift register, and Figure 25 B represents the work schedule of multi-channel conversion circuit.The work schedule of the shift register of Figure 25 A is with shown in Figure 19 identical, and the repetitive description thereof will be omitted.
In the work schedule of the multiplexer shown in Figure 25 B, illustrate that at first vertical transfer register 4a～4c and electric charge read the work of the combination of multi-channel conversion circuit 2a.At moment TO, connect SIG1 pulse and vertical drive pulse VDRV, to the current potential of capacitor C20, C21 charging SIG1 pulse.At moment T1, vertical drive pulse VDRV is closed have no progeny, when reset pulse RESET and common source potential pulse VDDCEL were connected, capacitor C20 boosted.Thus, be not subjected to the influence of the decay that the threshold voltage of transistor T R20 causes, to pixel portions transmission reset pulse RESET.At the moment T3 reset pulse pulse RESET is closed and have no progeny the reference potential of the signal of output pixel.When connect transmitting pulse TRAN at moment T4, because capacitor C21 boosts, thus be not subjected to the influence of the decay that the threshold voltage of transistor T R21 causes, just to pixel portions transmission transmission pulse TRAN.When moment T5 turn-offed transmission pulse TRAN, output was by the current potential of the stored charge signal deciding of pixel.Sampling keep that pulse SHNC connects during (from moment T2 to T6), the signal of these current potentials is sent to the noise canceller circuit 6 of Figure 22.When moment T8 makes common source potential pulse VDDCEL be in off-state, connect, turn-off by making reset pulse RESET, finish the selection work of this row.So far, be configured in first row pixel storage signal read end-of-job.For other row, also be identical.
The work of the combination of turn-offing shift register 5a～5c and electronics shutoff multi-channel conversion circuit 3 then, is described.At moment T0, connect ESIG1 pulse and vertical drive pulse VDRV, to the current potential of capacitor C22, C23 charging ESIG1 pulse.At the moment T1 vertical drive pulse VDRV is closed and have no progeny, when moment T9 connected reset pulse ERESET, capacitor C22 boosted.Thus, be not subjected to the influence of the decay that the threshold voltage of transistor T R22 causes, to pixel portions transmission reset pulse ERESET.After moment T10 turn-offs reset pulse ERESET, when connecting at moment T11 when transmitting pulse ETRAN, be not subjected to the influence of the decay that the threshold voltage of transistor T R23 causes, transmit pulse ETRAN to the pixel portions transmission.At moment T14, when common source potential pulse VDDCEL is in off state, make reset pulse ERESET connect, turn-off, finish the selection work of this row.So far, be configured in the removing end-of-job of the stored charge signal of first pixel of going to power supply.For other row, also be identical.
Even under the situation of above-mentioned circuit structure arbitrarily, existing solid photographic device also need to be used for read pixel stored charge vertical transfer register and be used to remove these 2 shift registers of shutoff shift register of stored charge; In addition, the multi-channel conversion circuit and these 2 multi-channel conversion circuits of electronics shutoff multi-channel conversion circuit that are used to remove stored charge that need be used for the stored charge of read pixel, need bigger circuit area, thus become that the bad qualification rate that causes of work of shift register or multi-channel conversion circuit descends reason.
Summary of the invention
The present invention puts in view of the above problems and makes, its purpose is to provide a kind of solid photographic device of XY address type, this XY address type solid-state imaging device can be used for 1 shift register stored charge and read with scanning and stored charge removing scanning, and, 1 multiplexer can also be used for stored charge and read the output of using signal with signal and stored charge removing, can dwindle chip area and improve the work qualification rate.
To achieve these goals, XY address type solid-state imaging device of the present invention comprises: a plurality of pixels are arranged in two-dimensional shapes; Level and vertical scanning circuit, output are used to carry out the signal that the stored charge of above-mentioned pixel reads; And multi-channel conversion circuit, according to the output signal of above-mentioned vertical scanning circuit to the component feeding control signal that constitutes above-mentioned each pixel, and, using 1 above-mentioned vertical scanning circuit, the stored charge of exporting above-mentioned pixel reads with sweep signal and stored charge removing sweep signal; Use 1 above-mentioned multi-channel conversion circuit, read with sweep signal and above-mentioned stored charge removing sweep signal, supply with stored charge as above-mentioned control signal and read with signal and stored charge removing signal according to above-mentioned stored charge.
Description of drawings
Fig. 1 is the block diagram of the MOS type image sensor circuit of expression first execution mode of the present invention.
Fig. 2 is that expression constitutes the shutoff dual-purpose vertical row scanning circuit of this MOS type image sensor circuit and the circuit diagram of the concrete structure that turn-offs the dual-purpose multi-channel conversion circuit.
Fig. 3 A and Fig. 3 B are this shutoff dual-purpose vertical row scanning circuit of expression and the figure that turn-offs the work schedule of dual-purpose multi-channel conversion circuit.
Fig. 4 is the shutoff dual-purpose vertical row scanning circuit of the expression MOS type image sensor circuit that constitutes second execution mode of the present invention and the circuit diagram that turn-offs the concrete structure of dual-purpose multi-channel conversion circuit.
Fig. 5 is the figure of the work schedule of this shutoff dual-purpose vertical row scanning circuit of expression.
Fig. 6 is the shutoff dual-purpose vertical row scanning circuit of the expression MOS type image sensor circuit that constitutes the 3rd execution mode of the present invention and the circuit diagram that turn-offs the concrete structure of dual-purpose multi-channel conversion circuit.
Fig. 7 is the figure of the work schedule of this shutoff dual-purpose multi-channel conversion circuit of expression.
Fig. 8 is the shutoff dual-purpose vertical row scanning circuit of the expression MOS type image sensor circuit that constitutes the 4th execution mode of the present invention and the circuit diagram that turn-offs the concrete structure of dual-purpose multi-channel conversion circuit.
Fig. 9 is the figure of the work schedule of this shutoff dual-purpose multi-channel conversion circuit of expression.
Figure 10 is the block diagram of the MOS type image sensor circuit of expression the 5th execution mode of the present invention.
Figure 11 is that expression constitutes the shutoff dual-purpose vertical row scanning circuit of this MOS type image sensor circuit and the circuit diagram of the concrete structure that turn-offs the dual-purpose multi-channel conversion circuit.
Figure 12 is the figure of the work schedule of this shutoff dual-purpose multi-channel conversion circuit of expression.
Figure 13 is the shutoff dual-purpose vertical row scanning circuit of the expression MOS type image sensor circuit that constitutes the 6th execution mode of the present invention and the circuit diagram that turn-offs the concrete structure of dual-purpose multi-channel conversion circuit.
Figure 14 is the figure of the work schedule of this shutoff dual-purpose multi-channel conversion circuit of expression.
Figure 15 is the frame circuit diagram of the camera system of expression the 7th execution mode of the present invention.
Figure 16 is the frame circuit diagram of the MOS type image sensor circuit of expression conventional example.
Figure 17 is the figure of the work schedule of this mos image sensor circuit of expression.
Figure 18 is the circuit diagram of the concrete structure of the expression shift register that constitutes this MOS type image sensor circuit.
Figure 19 represents the figure of the work schedule of this shift register.
Figure 20 is the circuit diagram that expression constitutes the concrete structure of the shift register of this MOS type image sensor circuit and multi-channel conversion circuit.
Figure 21 A, 21B are the figure of the work schedule of this shift register of expression and multi-channel conversion circuit.
Figure 22 is the frame circuit diagram of the MOS type image sensor circuit of other conventional example of expression.
Figure 23 is the figure of the work schedule of this MOS type imageing sensor of expression.
Figure 24 is the circuit diagram that expression constitutes the concrete structure of the shift register of this MOS type image sensor circuit and multi-channel conversion circuit.
Figure 25 A, 25B are the figure of the work schedule of this shift register of expression and multi-channel conversion circuit.
Embodiment
Structure according to XY address type solid-state imaging device of the present invention, the stored charge that 1 vertical scanning circuit is used for pixel can be read with the stored charge of scanning and above-mentioned pixel and remove with scanning, and, 1 multi-channel conversion circuit can also be used for stored charge and read the output of using signal with signal and stored charge removing, can dwindle chip area and improve qualification rate.
In solid photographic device of the present invention, can also comprise: the scanning purposes is selected circuit, per 1 scanning stage setting of corresponding above-mentioned vertical scanning circuit, read with the stored charge of scanning or above-mentioned pixel according to the stored charge of above-mentioned pixel and to remove, will read with sweep signal or stored charge as stored charge from the signal of above-mentioned vertical scanning circuit output and remove some output selectively with sweep signal with one selection in the scanning; And sweep signal time division circuit, each scanning stage of corresponding above-mentioned vertical scanning circuit is provided with, read with sweep signal and above-mentioned stored charge removing sweep signal according to the above-mentioned stored charge of selecting circuit output from above-mentioned scanning purposes, to the stored charge of above-mentioned pixel read with signal and stored charge remove cut apart with the signal time of carrying out after, to above-mentioned multi-channel conversion circuit output.
Preferred structure in this structure is that above-mentioned scanning purposes is selected the scanning commencing signal of circuit by the above-mentioned vertical scanning circuit of input, begins its work.Thus, do not need newly to be provided with control and just can constitute scanning purposes selection circuit with pulse.
In addition, preferred structure is that above-mentioned scanning purposes selection circuit will be read with sweep signal or the removing of above-mentioned stored charge by the above-mentioned stored charge that preceding 1 scanning stage of this scanning stage is exported uses sweep signal as starting impulse, scans successively.Thus, do not need newly to be provided with control and use pulse, just can constitute the scanning purposes and select circuit.
In addition, preferred structure is that above-mentioned scanning purposes selection circuit will be read with sweep signal or the removing of above-mentioned stored charge by the above-mentioned stored charge that back 1 scanning stage of this scanning stage is exported uses sweep signal as stop pulse, scans successively.Thus, do not need newly to be provided with control and use pulse, just can constitute the scanning purposes and select circuit.
In addition, preferred structure is, the above-mentioned scanning purposes corresponding with the 2nd grade of later scanning stage of above-mentioned vertical scanning circuit selected circuit, built-inly be used for not making above-mentioned stored charge to read removing boostrap circuit, will be in above-mentioned stored charge before 1 scanning stage of this scanning stage and read with signal or above-mentioned stored charge and remove with the input signal of signal as above-mentioned boostrap circuit with signal attenuation with signal and above-mentioned stored charge.Thus, the applied signal voltage to pixel portions is transmitted damply.
In addition, preferred structure is, select also built-in above-mentioned boostrap circuit in the circuit in the above-mentioned scanning purposes corresponding with the elementary scanning stage of above-mentioned vertical scanning circuit, as above-mentioned boostrap circuit input signal, supply with in addition with above-mentioned stored charge and read with signal or the above-mentioned stored charge removing different signal of signal.Thus, can suppress the generation that the some voltages in scanning circuit elementary descend, the applied signal voltage to pixel portions is transmitted damply.
In solid photographic device of the present invention, also can have following structure: will supply with above-mentioned multi-channel conversion circuit and the row selection signal that is used for the pixel of the regulation row of the arrangement of above-mentioned a plurality of pixels is selected to drive to the input of said scanning signals time division circuit, select the time of signal controlling said scanning signals time division circuit to cut apart work according to above line.Thus, do not need newly to be provided with the control pulse, 1 multi-channel conversion circuit dual-purpose can be read with signal and stored charge at stored charge and remove the output of using signal.
In addition, can also have following structure: the noise canceller circuit that possesses the noise of the output signal that is used to remove above-mentioned pixel; Keep pulse to the input of said scanning signals time division circuit the sampling of above-mentioned noise canceller circuit, keep the time of pulse control said scanning signals time division circuit to cut apart work according to above-mentioned sampling.Thus, do not need newly to be provided with control and use pulse, just 1 multi-channel conversion circuit can be used for stored charge and read the output of using signal with signal and stored charge removing.
In addition, also can have following structure: the above-mentioned structure that is arranged in a plurality of pixels of two-dimensional shapes is that each pixel comprises by transmitting 4 transistors that transistor, reset transistor, amplifier transistor and row selecting transistor constitute; For the stored charge that carries out each pixel reads, from 3 signals of above-mentioned multi-channel conversion circuit output reset signal, transmission signal and row selection signal; For the stored charge that carries out each pixel is removed, from above-mentioned multi-channel conversion circuit output reset signal and transmission signal.Thus, even the pixel that is made of 4 transistors also can only be provided with 1 multi-channel conversion circuit and hold, carry out electronics shutoff work.
Perhaps, also can have following structure: the above-mentioned structure that is arranged in a plurality of pixels of two-dimensional shapes is that each pixel comprises by transmitting 3 transistors that transistor, reset transistor and amplifier transistor constitute; For the stored charge that carries out each pixel reads and the stored charge removing, from above-mentioned multi-channel conversion circuit output reset signal and transmission signal.Thus, even the pixel that is made of 3 transistors also can only be provided with 1 multi-channel conversion circuit, carry out electronics shutoff work.
In addition, also can be that all circuit are made of N type MOS transistor and N type mos capacitance device.Thus, just can shorten manufacturing process, and reduce cost.
Can constitute the video camera or the camera system of the XY address type solid-state imaging device that possesses above any structure.
Below, be described more specifically embodiments of the present invention with reference to accompanying drawing.
(first execution mode)
Fig. 1 is the block diagram of the MOS type image sensor circuit of expression first execution mode of the present invention.The basic structure of this circuit is identical with the circuit of conventional example shown in Figure 16, is with the circuit difference of Figure 16, and comprehensive electric charge reads multi-channel conversion circuit 2 and electronics turn-offs multi-channel conversion circuit 3, is provided with to turn-off dual-purpose multi-channel conversion circuit 10; Comprehensive vertical row scanning circuit 4 and electronics turn-off scanning circuit 5, are provided with to turn-off dual-purpose vertical row scanning circuit 11.
Promptly, the feature of present embodiment is, 1 vertical scanning circuit is used for stored charge reads with sweep signal and stored charge and remove output with sweep signal, and, 1 multi-channel conversion circuit is used for stored charge reads with signal and stored charge and remove output with signal.Thus, dwindled chip area, the decline of the work qualification rate in the time of can having suppressed to load 2 vertical scanning circuit and 2 multi-channel conversion circuits.Other structure is identical with circuit shown in Figure 16, and identical key element is paid identical Reference numeral, and omits repeat specification.The overall work of this circuit also sequential with shown in Figure 17 is identical, omits the diagram and the explanation that repeat.
In Fig. 2, show particular circuit configurations MOS type image sensor circuit, that comprise shutoff dual-purpose multi-channel conversion circuit 10 and turn-off dual-purpose vertical row scanning circuit 11 of pie graph 1.
Show the vertical transfer register 11a～11c that constitutes the 1st grade～3rd level that turn-offs dual-purpose vertical row scanning circuit 11 at Fig. 2.In the circuit of Fig. 2, select circuit 12 to constitute by vertical transfer register 11a～11c and scanning purposes and turn-off dual-purpose vertical row scanning circuit 11.In addition, constitute shutoff dual-purpose multi-channel conversion circuit 10 by sweep signal time division circuit 13 and multi-channel conversion circuit 14.
The output signal of vertical transfer register 11a～11c at different levels selects circuit 12 and sweep signal time division circuit 13 to be provided to multi-channel conversion circuit 14 through the scanning purposes.It is the stored charge that 1 vertical transfer register is used for pixel can be read with the stored charge of scanning and pixel to remove with scanning that the scanning purposes is selected the structure of circuit 12.As vertical transfer register 11a～11c, can use the structure identical with the circuit of conventional example shown in Figure 180.
Scanning purposes selection circuit 12 comprises and is used for selecting transistor T R51, TR53 work, work when the stored charge of pixel reads, TR57 and the transistor T R52, the TR55 that work, TR59 etc. accordingly with vertical transfer register 11a～11c at different levels when stored charge is removed.In addition, in the scanning purposes corresponding with the 2nd grade of later vertical transfer register 11b～11c selected circuit 12 at different levels, be provided with bootstrap capacitor C2, C3, C4, C5 etc.
It is identical that the structure of multi-channel conversion circuit 14 and the electric charge of conventional example shown in Figure 20 read multi-channel conversion circuit 2.Sweep signal time division circuit 13 is included in switch SW, the switch SW E that the scanning purposes is selected insertion between circuit 12 and the multi-channel conversion circuit 14.The output at different levels of vertical transfer register 11a～11c is selected by sweep signal time division circuit 13, to be transmitted for 14 corresponding at different levels cutting apart by the time with multi-channel conversion circuit after circuit 12 switches by the scanning purposes.Therefore, utilize sweep signal time division circuit 13, just can constitute multi-channel conversion circuit 14 and be used for stored charge and read with signal and stored charge and remove structure with the output of signal.
The work schedule of circuit shown in Figure 2 is described with reference to Fig. 3 A, Fig. 3 B.Fig. 3 A represents the work schedule of vertical transfer register 11a～11c, and Fig. 3 B represents the work schedule of multi-channel conversion circuit 14 and sweep signal time division circuit 13.Have again, though in Fig. 3 A and Fig. 3 B, be marked with identical moment mark, and do not mean that the identical moment.Corresponding during for example SIG1/ESIG1 pulse among SIG/ESIG impulse duration shown in Fig. 3 B and Fig. 3 A.
In moment T1 starting impulse VST disconnection, in moment T2 the 1st scanning impulse V1 disconnection, when moment T3 connects the 2nd scanning impulse V2, select the 2nd grade of input VSR2 pulse of circuit 12 to the scanning purposes from the 2nd grade vertical transfer register 11b.Because this moment, the electrode N-S2 of bootstrap capacitor C2 was recharged, so transistor T R53 conducting, further the electrode N-S2 of bootstrap capacitor C2 boosts, thereby be not subjected to the influence of the threshold value of transistor T R53, pulse is transferred to the switch SW of sweep signal time division circuit 13 as SIG2 in the VSR2 pulse.This SIG2 pulse also is input to the electrode N-S3 of the bootstrap capacitor C4 of the 3rd level that scans purposes selection circuit 12, the charging of beginning bootstrap capacitor C4.
In moment T4 the 2nd scanning impulse V2 disconnection, when moment T5 the 1st scanning impulse V1 connects, select the 3rd level input VSR3 pulse of circuit 12 to the scanning purposes from the vertical transfer register 11c of 3rd level.Because this moment, the electrode N-S3 of bootstrap capacitor C4 was recharged, so transistor T R57 conducting, the electrode N-S3 of bootstrap capacitor C4 is boosted, be not subjected to the influence of the threshold value of transistor T R57, pulse is transferred to the switch SW of sweep signal time division circuit 13 as SIG3 in the VSR3 pulse.At this moment, because the SIG3 pulse is imported into the 2nd grade the transistor T R54 that the scanning purposes is selected circuit 12, the scanning purposes is selected the current potential of the electrode N-S2 of the bootstrap capacitor C2 in the 2nd grade of circuit 12, is reset to GND.That is, the SIG3 pulse is selected the 2nd grade stop pulse of circuit 12 as the scanning purposes and is acted on.
After, by repeating same work, each VSR pulse can not produce decay, is transferred to the switch SW of sweep signal time division circuit 13 as the order SIG pulse of following scanning.
In moment T1 starting impulse SHTST disconnection, in moment T2 the 1st scanning impulse V1 disconnection, when moment T3 connects the 2nd scanning impulse V2, select the 2nd grade of input VSR2 pulse of circuit 12 to the scanning purposes from the 2nd grade vertical transfer register 11b.Because this moment, the electrode N-ES2 of bootstrap capacitor C3 was recharged, so transistor T R55 connects, the electrode N-ES2 of bootstrap capacitor C3 is boosted, be not subjected to the influence of the threshold value of transistor T R55, pulse is transferred to the switch SW E of sweep signal time division circuit 13 as ESIG2 in the VSR2 pulse.This ESIG2 pulse also is imported into the electrode N-E3 of the bootstrap capacitor C5 of the 3rd level that scans purposes selection circuit 12, the charging of beginning bootstrap capacitor C5.
In moment T4 the 2nd scanning impulse V2 disconnection, when moment T5 the 1st scanning impulse V1 connects, select the 3rd level input VSR3 pulse of circuit 12 to the scanning purposes from the vertical transfer register 11c of 3rd level.Because this moment, the electrode N-ES3 of bootstrap capacitor C5 was recharged, so transistor T R59 conducting, further the electrode N-ES3 of bootstrap capacitor C5 boosts, be not subjected to the influence of the threshold value of transistor T R59, pulse is transferred to the switch SW E of sweep signal time division circuit 13 as ESIG3 in the VSR3 pulse.Because ESIG3 pulse this moment is imported into the 2nd grade the transistor T R56 that the scanning purposes is selected circuit 12, so the scanning purposes selects the electrode N-ES2 current potential of the bootstrap capacitor C3 in the 2nd grade of circuit 12 just to be reset to GND.
After, by repeating same work, each VSR pulse is unattenuated, as the order ESIG pulse of following scanning, is transferred to the switch SW E of sweep signal time division circuit 13.
As mentioned above, utilize the scanning purposes to select circuit 12, selection offers stored charge with the output pulse of vertical transfer register 11a～11c and reads generation with signal, still offers stored charge and remove generation with signal, and is transferred to the switch SW or the switch SW E of sweep signal time division circuit 13.
The work schedule of the multi-channel conversion circuit 14 shown in Fig. 3 B and electric charge with reference to Figure 20 and Figure 21 B explanation read multi-channel conversion circuit 2 and electronics, and to turn-off the work of multi-channel conversion circuit 3 identical in fact.Wherein, according to the work of sweep signal time division circuit 13, work inequality is as described below.
That is, in the work shown in Figure 21 B, at moment T0～moment T7, by the work that electric charge reads multi-channel conversion circuit 2, the output stored charge reads uses signal; At moment T8～moment T12, by the work that electronics turn-offs multi-channel conversion circuit 3, the output stored charge is removed and is used signal.In contrast to this, in the work shown in Fig. 3 B, the work of multi-channel conversion circuit 14 arbitrarily is identical with the work of two multi-channel conversion circuits 2,3 shown in Figure 21 B, and the output stored charge reads with signal and stored charge removing signal.Therefore, omit the repeat specification of detailed operation.
Make the work of the sweep signal time division circuit 13 that multi-channel conversion circuit 14 works like this with reference to Fig. 3 B explanation.
According to sweep signal VSR, and utilize the scanning purposes to select circuit 12, during the SIGSW pulse-on, read and use signal SIG to the stored charge of the switch SW output pixel of sweep signal time division circuit 13 from vertical transfer register 11a～11c.On the other hand, during the ESIGSW pulse-on, to the switch SW E of sweep signal time division circuit 13 output stored charge removing signal ESIG.
Moment T2～moment T7 in during the SIG pulse-on, from multi-channel conversion circuit 14 output be used for the stored charge of read pixel reset signal RESET, transmit signal TRAN and these 3 signals of row selection signal VSEL.Moment T8～moment T11 in during the ESIG pulse-on, be used to remove from multi-channel conversion circuit 14 output pixel stored charge reset signal ERESET and transmit defeated signal ETRAN.
According to present embodiment, by being set, simple scanning purposes selects circuit 12 and sweep signal time division circuit 13, just energy enough 1 shutoff dual-purpose vertical row scanning circuits 11 execution vertical row scannings and electronics turn-off and scan, enough 1 the shutoff dual-purpose multi-channel conversion circuits 10 of energy are carried out stored charges and are read the output of using signal with signal and stored charge removing, can dwindle chip area, suppress because of loading the decline of the work qualification rate that 2 shift registers and multi-channel conversion circuit cause.
(second execution mode)
The MOS type image sensor circuit of second execution mode of the present invention has the overall structure identical with Fig. 1, compares with the circuit of first execution mode shown in Figure 2, and the scanning purposes selects the structure of circuit 12 inequality.Fig. 4 illustrates the concrete structure that the scanning purposes that comprises present embodiment is selected circuit 15, sweep signal time division circuit 13 and multi-channel conversion circuit 14.
The scanning purposes of present embodiment is selected circuit 15 to improve in the scanning purposes of first execution mode and select in the circuit 12 this point that occurs as SIG1 after the threshold value of the VSR1 impulse attenuation transistor T R51 of the 1st grade of input.Though the scanning purposes is selected circuit 15 to have with scanning purposes shown in Figure 2 and selected the identical basic structure of circuit 12, and is different with the 1st grade structure.That is, be provided with bootstrap capacitor CO, C1 at the 1st grade, the input bootstrapping forms booster circuit with starting impulse PREVST, PRESHTST, has suppressed the decay as the voltage of SIG1, ESIG1 appearance thus.
With reference to Fig. 5 work schedule is described.Vertical transfer register 11a～11c when at first, the stored charge of pixels illustrated reads and scanning purposes are selected the work of circuit 15.At moment T0, bootstrapping is connected with starting impulse PREVST; At moment T1, PREVST disconnects.Pulse PREVST is fed into the electrode N-S1 of the 1st grade bootstrap capacitor C0 of scanning purposes circuit 15, the charging of beginning capacitor C0.When moment T2 connection stored charge reads starting impulse VST and the 1st scanning impulse V1, select the 1st grade of input VSR1 pulse of circuit 15 to the scanning purposes from the 1st grade vertical transfer register 11a.Because this moment, the electrode N-S1 of bootstrap capacitor C0 was recharged, so transistor T R51 conducting, further the electrode N-S1 of bootstrap capacitor C0 boosts, and is not subjected to the influence of the threshold value of transistor T R51, and the VSR1 pulse occurs as SIG1.This SIG1 also is imported into the electrode N-S2 of the 2nd grade bootstrap capacitor C2 of scanning purposes circuit 15, the charging of beginning capacitor C2.
At moment T3, starting impulse VST disconnects; At moment T4, scanning impulse V1 disconnects.When moment T5 the 2nd scanning impulse V2 connects, select the 2nd grade of input VSR2 pulse of circuit 15 to the scanning purposes from the 2nd grade vertical transfer register 11b.Because this moment, the electrode N-S2 of bootstrap capacitor C2 was recharged, so transistor T R53 conducting, further the electrode N-S2 of bootstrap capacitor C2 boosts, and is not subjected to the influence of the threshold value of transistor T R53, and the VSR2 pulse occurs as SIG2.
When moment T7 the 1st scanning impulse V1 connects, select the 3rd level input VSR3 pulse of circuit 15 to the scanning purposes from the vertical transfer register 11c of 3rd level.Because this moment, the electrode N-S3 of bootstrap capacitor C4 was recharged, so transistor T R57 conducting, further the electrode N-S3 of bootstrap capacitor C4 boosts, and is not subjected to the influence of transistor T R57 threshold value, and the VSR3 pulse occurs as SIG3.SIG3 is input to the 2nd grade the transistor T R54 that the scanning purposes is selected circuit 15 owing to this moment, and the current potential of the electrode N-S2 of the 2nd grade bootstrap capacitor C2 of scanning purposes selection circuit 15 is reset to GND.
After, by repeating same work, the VSR pulse is unattenuated, on one side occur as SIG pulse sequential scanning on one side.
Scanning purposes when the stored charge of pixel is removed selects the work of circuit 15 also identical.That is, in Fig. 5, connect PRESHTST, PRESHTST disconnected, select the electrode N-ES1 of the 1st grade bootstrap capacitor C1 of circuit 15 to begin charging by the scanning purposes thus capacitor C1 at moment T1 at moment TO.When the stored charge of connecting pixel at moment T2 is removed starting impulse SHTST and the 1st scanning impulse V1, select the 1st grade of input VSR1 pulse of circuit 15 to the scanning purposes from the 1st grade vertical transfer register 11a.Because this moment, the electrode N-ES1 of bootstrap capacitor C1 was recharged, so transistor T R52 conducting, further the electrode N-ES1 of bootstrap capacitor C1 boosts, and is not subjected to the influence of the threshold value of transistor T R52, and the VSR1 pulse (T4a constantly) occur as ESIG1.After, by repeating identical work, the VSR pulse is unattenuated, on one side occur as ESIG pulse sequential scanning on one side.
As mentioned above, utilize the scanning purposes to select circuit 15 to select output pulse with vertical transfer register 11a～11c to offer stored charge and read generation, still offer stored charge and remove the generation of using signal, and be transferred to the switch SW or the switch SW E of sweep signal time division circuit 13 with signal.
The work of turn-offing dual-purpose multi-channel conversion circuit 10 is identical with first execution mode, and omits diagram and explanation.
According to present embodiment, by being set, simple scanning purposes selects circuit 15, utilize 1 to turn-off dual-purpose vertical row scanning circuit 11, just can carry out vertical row scanning and electronics and turn-off scanning, can dwindle chip area, and suppress because of loading the decline of the work qualification rate that 2 shift registers and multi-channel conversion circuit cause.
(the 3rd execution mode)
The overall structure of the MOS type image sensor circuit of the 3rd execution mode of the present invention is identical with the structure of second execution mode shown in Figure 4.In the present embodiment, the structure of sweep signal time division circuit is different with second execution mode.Fig. 6 shows the vertical transfer register 11a～11c that comprises in the present embodiment, the concrete structure that the scanning purposes is selected circuit 15, sweep signal time division circuit 16 and multi-channel conversion circuit 14.
Compare with the sweep signal time division circuit 13 in first execution mode, the sweep signal time division circuit 16 of present embodiment has the structure of having added inverter 17, and, substitute SIGS pulse, ESIGSW pulse, supply with to switch SW, switch SW E and utilize the signal of inverter 17 VSEL pulse and VSEL inversion pulse.
The work schedule that turn-offs dual-purpose vertical row scanning circuit 11 is identical with the work of the circuit shown in Figure 4 that illustrates with reference to Fig. 5, and omits diagram and the explanation that repeats.Fig. 7 represents the work schedule of multi-channel conversion circuit 14 and sweep signal time division circuit 16.The work of multi-channel conversion circuit 14 is identical with the work shown in Fig. 3 B, and the repetitive description thereof will be omitted.
The work of sweep signal time division circuit 16 is described with reference to Fig. 7.According to sweep signal VSR from vertical transfer register 11a～11c, utilize sweep signal time division circuit 16 during row selection signal VSEL pulse-on, the stored charge of pixel read with signal SIG output to multi-channel conversion circuit 14, on the other hand, during the inversion pulse of VSEL pulse is to connect, the stored charge removing is outputed to multi-channel conversion circuit 14 with signal ESIG.
Moment T2～moment T7 in during the SIG pulse-on, from multi-channel conversion circuit 14 output be used for the stored charge of read pixel reset signal RESET, transmit signal TRAN and these three signals of row selection signal VSEL.Moment T8～moment T11 in during the ESIG pulse-on, be used to remove from multi-channel conversion circuit 14 output pixel stored charge reset signal ERESET and transmit signal ETRAN.
As mentioned above, by simple sweep signal time division circuit 16, just can turn-off dual-purpose multi-channel conversion circuit 10 and be used for stored charge and read with signal and stored charge and remove output, and can suppress the decline of loading the work qualification rate that causes with multiplexer of dwindling because of chip area with signal with 1.
(the 4th execution mode)
The overall structure of the MOS type image sensor circuit of the 4th execution mode of the present invention is identical with the structure of the 3rd execution mode shown in Figure 6.In the present embodiment, the structure of sweep signal time division circuit is different with the 3rd execution mode.Fig. 8 shows the vertical transfer register 11a～11c that comprises present embodiment, the concrete structure that the scanning purposes is selected circuit 15, sweep signal time division circuit 18 and multi-channel conversion circuit 14.
Sweep signal time division circuit 16 exists following different in the sweep signal time division circuit 18 of present embodiment and the 3rd execution mode.That is, substitute the VSEL pulse, the sampling of supplying with noise canceller circuit 6 to switch SW, switch SW E respectively keeps pulse SHNC and utilizes inverter 17 to take a sample keeping the signal of pulse SHNC counter-rotating.
The work schedule that turn-offs dual-purpose vertical row scanning circuit 11 is identical with the work of the circuit of the Fig. 4 that illustrates with reference to Fig. 5, omits the diagram and the explanation that repeat.Fig. 9 represents the work schedule of multi-channel conversion circuit 14 and sweep signal time division circuit 18.The work of multi-channel conversion circuit 14 is identical with the work shown in Fig. 3 B, and the repetitive description thereof will be omitted.
The work of sweep signal time division circuit 18 is described with reference to Fig. 9.According to sweep signal VSR from vertical transfer register 11a～11c, utilize sweep signal time division circuit 18 to keep pulse SHNC for during connecting in sampling, read to the stored charge of multi-channel conversion circuit 14 output pixels and to use signal SIG, on the other hand, during the inversion pulse of the maintenance pulse SHNC that takes a sample is to connect, to multi-channel conversion circuit 14 output stored charges removing signal ESIG.
Moment T2～moment T7 in during the SIG pulse-on, from multi-channel conversion circuit 14 output be used for the stored charge of read pixel reset signal RESET, transmit signal TRAN and these three signals of row selection signal VSEL.Moment T8～moment T11 in during the ESIG pulse-on, be used to remove from multi-channel conversion circuit 14 output pixel stored charge reset signal ERESET and transmit signal ETRAN.
As mentioned above, by simple sweep signal time division circuit 18, just can turn-off dual-purpose multi-channel conversion circuit 10 and be used for stored charge and read with signal and stored charge and remove output, and can suppress the decline of loading the work qualification rate that causes with multiplexer of dwindling because of chip area with signal with 1.
(the 5th execution mode)
Figure 10 is the block diagram of the MOS type image sensor circuit of expression the 5th execution mode of the present invention.Compare with conventional example shown in Figure 22, structure when promptly not using row selection signal VSEL, this circuit has been suitable for the structure identical with second execution mode shown in Figure 4.Therefore, electric charge in the structure of comprehensive Figure 22 reads multi-channel conversion circuit 2a and electronics turn-offs multi-channel conversion circuit 3, be provided with to turn-off dual-purpose multi-channel conversion circuit 10a, and, replace vertical row scanning circuit 4 and electronics to turn-off scanning circuit 5, be provided with and turn-off dual-purpose vertical row scanning circuit 11.Other basic structure is identical with circuit shown in Figure 22, drives with this work schedule shown in Figure 23, so omit diagram and the explanation that repeats.
Figure 11 shows the shutoff dual-purpose multi-channel conversion circuit 10a that comprises the MOS type image sensor circuit that constitutes Figure 10 and turn-offs the concrete structure of dual-purpose vertical row scanning circuit 11.The circuit of Figure 11 structure with second execution mode shown in Figure 4 basically is identical, still, and the structure difference of multi-channel conversion circuit 14a.Multi-channel conversion circuit 14a reads the structure of multi-channel conversion circuit 2a corresponding to the electric charge of conventional example shown in Figure 24.
The sequential of the shift register work of circuit shown in Figure 11 is with identical with reference to the situation of 5 second execution modes that illustrate, and the diagram and the explanation of omission repetition.
The work schedule of multi-channel conversion circuit 14a and sweep signal time division circuit 13 has been shown among Figure 12.The work schedule of multi-channel conversion circuit 14a and the work of reading multi-channel conversion circuit 2a and electronics shutoff multi-channel conversion circuit 3 with reference to the electric charge of Figure 25 B explanation, identical in fact.And, by the work of sweep signal time division circuit 13, with second execution mode in the same manner, 1 multi-channel conversion circuit 14a output stored charge reads with signal and stored charge removing signal.Therefore, omit the repeat specification of detailed operation.
Be used to make the work of the sweep signal time division circuit 13 that multi-channel conversion circuit 14a works like this, the work during with first execution mode of reference Fig. 3 B explanation is identical.
As mentioned above, by being set, simple scanning purposes selects circuit 15 and sweep signal time division circuit 13, just can turn-off dual-purpose vertical row scanning circuit 11 and carry out vertical row scanning and electronics shutoff scanning with 1, and, utilize 1 shutoff dual-purpose multi-channel conversion circuit 10a can carry out stored charge and read the output of using signal with signal and stored charge removing, can dwindle chip area, and suppress because of loading the decline of the work qualification rate that 2 shift registers and multi-channel conversion circuit cause.
(the 6th execution mode)
The structure of the overall structure of the MOS type image sensor circuit of the 6th execution mode of the present invention and Figure 10, the 5th execution mode shown in Figure 11 is identical.In the present embodiment, the structure of sweep signal time division circuit is different with the 5th execution mode, has the structure identical with the sweep signal time division circuit 18 of the 4th execution mode.Figure 13 shows comprise vertical transfer register 11a～11c, the scanning purposes of present embodiment and selects the concrete structure of circuit 15, sweep signal time division circuit 18 and multi-channel conversion circuit 14a.
The work schedule that turn-offs dual-purpose vertical row scanning circuit 11 is identical with the work of the circuit shown in Figure 4 that illustrates with reference to Fig. 5, and omits diagram and the explanation that repeats.Figure 14 represents the work schedule of multi-channel conversion circuit 14a and sweep signal time division circuit 18.The work of multi-channel conversion circuit 14a is identical with the work shown in Fig. 3 B, and the repetitive description thereof will be omitted.In addition, the work of sweep signal time division circuit 18, identical with the work of reference Fig. 9 explanation with regard to the sweep signal time division circuit 18 shown in Figure 8 of the 4th execution mode, and the repetitive description thereof will be omitted.
As mentioned above, by being set, simple scanning purposes selects circuit 15 and sweep signal time division circuit 18, just can carry out vertical row scanning and electronics shutoff scanning by enough 1 shutoff dual-purpose vertical row scanning circuits 11, utilize 1 shutoff dual-purpose multi-channel conversion circuit 10a to carry out stored charge and read the output of using signal with signal and stored charge removing, can dwindle chip area, and suppress because of loading the decline of the work qualification rate that 2 shift registers and multi-channel conversion circuit cause.
In the above embodiment, to show vertical scanning circuit and multi-channel conversion circuit all comprehensively be one circuit structure and it is used for stored charge reads and stored charge is removed the example of (electronics shutoff).With respect to this, also can constitute the only structure of comprehensive some circuit.For example, for the vertical scanning circuit, 1 circuit can be used for vertical row scanner uni electronics and turn-off scanning; For multi-channel conversion circuit, used electric charge to read the structure of multi-channel conversion circuit and electronics shutoff multi-channel conversion circuit respectively.Perhaps, for the vertical scanning circuit, use vertical row scanning circuit and electronics to turn-off scanning circuit respectively, for multi-channel conversion circuit, 1 circuit can be used for the structure that electric charge reads multipath conversion and electronics shutoff multipath conversion.
(the 7th execution mode)
With reference to frame circuit diagram shown in Figure 15, the camera system of the 7th execution mode of the present invention is described.
The XY address type solid-state imaging device 20 that use has the structure of above-mentioned arbitrary execution mode constitutes this camera system.By the pixel portions 1 beam incident optical image of imaging lens system 21 to solid photographic device 20.Utilization is controlled the work of solid photographic device 20 from the control signal of signal processing chip 22 inputs.Handle the output signal of solid photographic devices 20 by signal processing chip 22, as the TV display with or the picture signal of numeral output usefulness and exporting.
Signal processing chip 22 comprises the 22a of brightness processed portion, look handling part 22b and AD converter section 22c, carries out work according to the control signal from microcontroller 23.Supply with the required information of signal processing chip 22 work that makes from EEPROM 24 to microcontroller 23.
Claims (13)
1, a kind of XY address type solid-state imaging device, comprising: a plurality of pixels are arranged in two-dimensional shapes; Level and vertical scanning circuit, output are used to carry out the signal that the stored charge of above-mentioned pixel reads; And multi-channel conversion circuit,, it is characterized in that to the component feeding control signal that constitutes above-mentioned each pixel according to the output signal of above-mentioned vertical scanning circuit,
Use 1 above-mentioned vertical scanning circuit, the stored charge of exporting above-mentioned pixel reads with sweep signal and stored charge removing sweep signal;
Use 1 above-mentioned multi-channel conversion circuit, read with sweep signal and above-mentioned stored charge removing sweep signal, supply with stored charge as above-mentioned control signal and read with signal and stored charge removing signal according to above-mentioned stored charge.
2, XY address type solid-state imaging device according to claim 1 is characterized in that, comprising:
The scanning purposes is selected circuit, per 1 scanning stage setting of corresponding above-mentioned vertical scanning circuit, read with the stored charge of scanning or above-mentioned pixel according to the stored charge of above-mentioned pixel and to remove, will read with sweep signal or stored charge as stored charge from the signal of above-mentioned vertical scanning circuit output and remove some output selectively with sweep signal with one selection in the scanning; And
The sweep signal time division circuit, each scanning stage of corresponding above-mentioned vertical scanning circuit is provided with, read with sweep signal and above-mentioned stored charge removing sweep signal according to the above-mentioned stored charge of selecting circuit output from above-mentioned scanning purposes, to the stored charge of above-mentioned pixel read with signal and stored charge remove cut apart with the signal time of carrying out after, to above-mentioned multi-channel conversion circuit output.
3, XY address type solid-state imaging device according to claim 2 is characterized in that,
Above-mentioned scanning purposes is selected the scanning commencing signal of circuit by the above-mentioned vertical scanning circuit of input, begins its work.
4, XY address type solid-state imaging device according to claim 2 is characterized in that,
Above-mentioned scanning purposes selection circuit will be read with sweep signal or the removing of above-mentioned stored charge by the above-mentioned stored charge that preceding 1 scanning stage of this scanning stage is exported uses sweep signal as starting impulse, scans successively.
5, XY address type solid-state imaging device according to claim 2 is characterized in that,
Above-mentioned scanning purposes selection circuit will be read with sweep signal or the removing of above-mentioned stored charge by the above-mentioned stored charge that back 1 scanning stage of this scanning stage is exported uses sweep signal as stop pulse, scans successively.
6, XY address type solid-state imaging device according to claim 2 is characterized in that,
The above-mentioned scanning purposes corresponding with the 2nd grade of later scanning stage of above-mentioned vertical scanning circuit selected circuit, built-inly be used for not making above-mentioned stored charge to read removing boostrap circuit, will be in above-mentioned stored charge before 1 scanning stage of this scanning stage and read with signal or above-mentioned stored charge and remove with the input signal of signal as above-mentioned boostrap circuit with signal attenuation with signal and above-mentioned stored charge.
7, XY address type solid-state imaging device according to claim 6 is characterized in that,
Select also built-in above-mentioned boostrap circuit in the circuit in the above-mentioned scanning purposes corresponding with the elementary scanning stage of above-mentioned vertical scanning circuit, as above-mentioned boostrap circuit input signal, supply with in addition with above-mentioned stored charge and read with signal or the above-mentioned stored charge removing different signal of signal.
8, XY address type solid-state imaging device according to claim 2 is characterized in that,
To the input of said scanning signals time division circuit, select the time of signal controlling said scanning signals time division circuit to cut apart work the row selection signal supplying with above-mentioned multi-channel conversion circuit and be used for the pixel of the regulation row of the arrangement of above-mentioned a plurality of pixels is selected to drive according to above line.
9, XY address type solid-state imaging device according to claim 2 is characterized in that,
The noise canceller circuit that possesses the noise of the output signal that is used to remove above-mentioned pixel;
Keep pulse to the input of said scanning signals time division circuit the sampling of above-mentioned noise canceller circuit, keep the time of pulse control said scanning signals time division circuit to cut apart work according to above-mentioned sampling.
10, XY address type solid-state imaging device according to claim 1 is characterized in that,
The above-mentioned structure that is arranged in a plurality of pixels of two-dimensional shapes is that each pixel comprises by transmitting 4 transistors that transistor, reset transistor, amplifier transistor and row selecting transistor constitute;
For the stored charge that carries out each pixel reads, from 3 signals of above-mentioned multi-channel conversion circuit output reset signal, transmission signal and row selection signal;
For the stored charge that carries out each pixel is removed, from above-mentioned multi-channel conversion circuit output reset signal and transmission signal.
11, XY address type solid-state imaging device according to claim 1 is characterized in that,
The above-mentioned structure that is arranged in a plurality of pixels of two-dimensional shapes is that each pixel comprises by transmitting 3 transistors that transistor, reset transistor and amplifier transistor constitute;
For the stored charge that carries out each pixel reads and the stored charge removing, from above-mentioned multi-channel conversion circuit output reset signal and transmission signal.
12, XY address type solid-state imaging device according to claim 1 is characterized in that,
All circuit are made of N type MOS transistor and N type mos capacitance device.
13, a kind of camera system comprises the described XY address type solid-state imaging device of claim 1 and constitutes.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP241420/2005 | 2005-08-23 | ||
| JP2005241419A JP2007060136A (en) | 2005-08-23 | 2005-08-23 | Solid-state imaging device |
| JP241419/2005 | 2005-08-23 | ||
| JP284940/2005 | 2005-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1921572A true CN1921572A (en) | 2007-02-28 |
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ID=37779112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101216403A Pending CN1921572A (en) | 2005-08-23 | 2006-08-23 | XY address type solid-state imaging device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2007060136A (en) |
| CN (1) | CN1921572A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521757B (en) * | 2008-02-26 | 2012-11-28 | 精工电子有限公司 | Image sensor |
-
2005
- 2005-08-23 JP JP2005241419A patent/JP2007060136A/en not_active Withdrawn
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2006
- 2006-08-23 CN CNA2006101216403A patent/CN1921572A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521757B (en) * | 2008-02-26 | 2012-11-28 | 精工电子有限公司 | Image sensor |
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| Publication number | Publication date |
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| JP2007060136A (en) | 2007-03-08 |
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