CN1909366A - Direct conversion receiver architecture - Google Patents

Abstract

A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Description

The Direct Conversion Receiver structure

The present invention is that international filing date is on February 15th, 2002, Chinese patent application number 02807924.8, is entitled as the dividing an application of patent application of " Direct Conversion Receiver structure ".

Background

The field

The present invention relates generally to electronic circuit, more specifically relate to the direct down-conversion receiver structure that is used for wireless (for example CDMA) communication system.

Background

In cdma system, the data that send are initial treatedly to be more suitable for radio frequency (RF) modulated signal in communicated upon radio communication channels with generation.The RF modulated signal is sent to one or more predetermined receivers then on communication channel, these receivers may be the terminals in the cdma system.The signal that is launched is subjected to the influence of different transport phenomenas, such as decline and multipath.These phenomenons have caused being positioned at bigger signal power level scope in the RF modulated signal that end receives, and this scope may be 100dB or more.

In given end, the signal of emission is received, adjusts and is down-converted to base band by the receiver front end unit.Generally, the frequency downconverted from RF to the base band is the heterodyne receiver realization of a plurality of by comprising (for example two) frequency downconverted level.In the first order, the signal that receives is down converted to intermediate frequency (IF) from RF, wherein generally will realize filtering and amplification.In the second level, the IF signal downconverts to base band from IF, wherein will realize the data of processing to recover to be launched of adding.

The heterodyne receiver structure provides several benefits.The first, can select the IF frequency make by be used for realizing to the received signal adjusting with the RF of down conversion and analog circuit in the non-linear intermodulation of not expecting (IM) product that causes can be more easily by elimination.The second, can provide multiple filter and variable gain amplifier (VGA) so that filtering and the amplification to receiving signal necessity to be provided at RF and IF place.For example, the RF amplifier may be designed to provide the gain ranging of 40dB, and the IF amplifier may be designed to provide the gain ranging of 60dB, these two dynamic ranges that can cover together the 100dB that receives signal.

To some application,, preferably can design to reduce size and expense by simplified receiver such as cell phone.And, to such as cellular mobile application, preferably can reduce power consumption to prolong the life-span of the battery between time charging.To these application, directly down-conversion receiver (being called homodyne radio receiver or zero-IF receivers again) may provide the benefit of these expectations, and this is because it only uses one-level to be down-converted to base band with the signal that will receive from RF.

In the direct down-conversion receiver of design, run into several challenges.For example, owing to directly do not having the IF signal in the down-conversion receiver, generally provide the gain ranging of (for example 60dB) just need to provide at RF or the base band place in the direct down-conversion receiver by the IF amplifier in the heterodyne receiver.For avoiding that the RF circuit is had additional requirement and is minimizing expense and circuit complexity, this IF gain ranging may provide at the base band place.Yet if provide the baseband gain scope with digital form after analog-to-digital conversion, owing to provide gain with digital form behind ADC, the baseband signal that offers analog to digital converter (ADC) has less amplitude.Because the amplitude of baseband signal is less, and the DC biasing may account for the bigger percentage of signal amplitude, and the DC biasing in the baseband signal is more crucial Consideration of direct down-conversion receiver.

Therefore in the field, need one the signal gain of needs and the direct down-conversion receiver structure that the DC biasing is corrected can be provided.

Summary

Each side of the present invention provides direct down-conversion receiver structure, has the DC loop to use small-sized serial line interface that control to the RF/ analog circuit is provided to remove DC biasing, digital variable gain amplifier (DVGA) before and after the analog-to-digital conversion from signal component so that gain ranging, automatic gain control (AGC) loop gain controlling and serial bus interface (SBI) unit so that DVGA and RF/ analog circuit to be provided to be provided.

On the one hand, provide DVGA to be used for direct down-conversion receiver.This DVGA can provide need in order to all of the dynamic range of considering the whole signal that receives or the gain ranging (promptly not considering that part of of RF/ analog circuit) of a part.The design of DVGA and DVGA may realize as mode described here the position in direct down-conversion receiver structure.

On the other hand, the operator scheme of VGA loop part is according to the operator scheme of DC loop and selected.Because these two loops are operated (directly or indirectly) to same signal component, and reciprocation is arranged between them.Provide loop technology may influence the incident of other loop performances at this with notice, make other loop suitably processing events to minimize the deterioration of performance.For example, if the DC loop is setovered to remove big DC fast in the acquisition mode operation, then the big DC spiking of Chan Shenging may produce deleterious effects to the AGC loop, so can trigger this incident, the AGC loop may be operated to minimize the influence of DC spiking to the AGC line loop with low gain mode or together with freezing mode then.

On the other hand, DC loop duration of being in acquisition mode operation is inversely proportional to the bandwidth that is in the DC loop of acquisition mode.The DC loop bandwidth is designed to wideer when acquisition mode so that the DC loop can respond and remove the DC biasing in the signal component quickly.Yet wideer loop bandwidth also causes the more loop noise that is generated by the DC loop.Be restriction overall noise amount (this comprises DC spiking and the loop noise that will correct) but allow the DC loop to operate on high bandwidth simultaneously, duration and loop bandwidth that the DC loop is in the acquisition mode operation are inversely proportional to.Because wideer loop bandwidth can be corrected the DC biasing quickly, so can improve performance in acquisition mode flower less time.

In another embodiment, provide by the control of universal serial bus some or all of RF/ analog circuits.Use standard serial bus to provide many benefits, such as the plate face layout of the lead-in wire that reduces, simplification, minimizing expense or the like with control RF/ analog functuion.Universal serial bus may also be designed to different characteristic so that control more effectively to be provided.For example, may support a plurality of hardware requests channels (for example, channel of each circuit is with controlled separately), each channel may be relevant with relevant priority, and may use a plurality of possible data-transmission modes to launch message on each channel.

Different aspect of the present invention and embodiment will describe in detail following.The present invention also provides the device and the element of method, digital signal processor, receiver unit and other realization different aspect of the present invention, embodiment and features, as will be described in detail.

Brief description of the drawings

By the detailed description with the accompanying drawing that proposes below, it is more obvious that feature of the present invention, character and advantage will become, and identical symbol has identical sign in the accompanying drawing, wherein:

Fig. 1 is the module map of embodiment that can realize the receiver unit of different aspect of the present invention and embodiment;

Fig. 2 A is the embodiment module map of direct down-converter;

Fig. 2 B is the embodiment module map of DC biasing canceller;

Fig. 3 is the embodiment module map of digital variable gain amplifier (DVGA);

Fig. 4 A is the module map of AGC loop unit;

Fig. 4 B is the module map of AGC control unit; And

Fig. 4 C is the instance graph of the gain transfer function of RF/ analog circuit.

Describe in detail

Fig. 1 is the embodiment chart that can realize the receiver unit 100 of different aspect of the present invention and embodiment.Receiver unit 100 may be realized in the terminal of wireless (for example CDMA) communication system or in the base station.For for purpose of brevity, be used in the interior receiver of terminal and realize having described different aspect of the present invention and embodiment.For for purpose of brevity, provide the particular design value at this, but can also use other design loads in the scope of the invention.

In Fig. 1, one or more RF modulated signals of coming from one or more transmitters (for example base station, gps satellite, broadcasting station etc.) receive and offer amplifier (Amp) 114 by antenna 112.Amplifier 114 is realized amplifying so that the RF signal through amplifying to be provided with certain gain to the received signal.Amplifier 114 may comprise one or more low noise amplifiers (LNA) levels, so that gain in the particular range and/or decay (for example 40dB from maximum gain to decay) to be provided.The certain gain of amplifier 114 may be determined by the gain controlling message that serial bus interface (SBI) unit 150 provides by universal serial bus 152.RF signal through amplifying then by receiving filter 116 filtering to remove noise and parasitic signal, the RF signal after will filtering then offers direct low-converter 120.

Directly low-converter 120 is realized the direct quadrature frequency conversion of RF signal from RF to the base band after filtering.This can multiply each other with local oscillator (LO) complex signal by the RF signal after will filtering (or mixing mutually) is to provide complex baseband signal.Particularly, the RF signal after the filtration may with homophase LO signal mixing with provide homophase (I) base band component and with quadrature LO signal mixing so that quadrature (Q) base band component to be provided.Be used for realizing that the frequency mixer of direct down-conversion may divide multistage realization, these grades are controlled so that different gains to be provided, and are as described below.In this case, the specific gain that frequency mixer provides also may be definite by another gain controlling message that universal serial bus 152 provides by SBI unit 150, as shown in Figure 1.Provide I and Q base band component to one or more analog to digital converters (ADCs) 122 then.

ADCs 122 samples I and the digitlization of Q base band component so that corresponding I and Q to be provided.ADCs 122 may realize with different ADC design, all if can filtering then can be at several times of sigma-delta modulators of locating (is 1.2288Mcps to IS-95) to I and Q base band component over-sampling of spreading rate of base band component.Over-sampling makes ADCs that bigger dynamic range can be provided, and offers the sample bit number still less of certain given accuracy of I and Q.In a particular embodiment, ADCs 122 provides 2 bit I and Q sampling with 16 times (being chipx16) of spreading rate.The ADCs of other type also may be used within the scope of the present invention.I and Q sampling offer digital filter 124 from ADCs 122.

Digital filter 124 elimination I and Q sampling I and Q sampling so that corresponding elimination to be provided.Digital filter 124 may realize that any amount of function such as mirror image suppresses filtering, base band pulse matched filtering, extraction, sample rate conversion or the like.In a particular embodiment, I and Q sampling after digital filter 124 will filter at 18 bits at chipx8 place offer DC biasing canceller 130.

DC biasing canceller 130 after filtration I and the Q sampling in remove the DC biasing and correct I and Q sampling so that corresponding D C biasing to be provided.In a particular embodiment, DC biasing canceller 130 realizes that two DC biasings correct loops, attempt different two places on the received signal path remove DC biasing-be in realize frequency downconverted by direct down-conversion 120 after after base band place and another are in by filter 124 digital filterings.The DC biasing is corrected will be at following detailed description.

Digital variable gain amplifier (DVGA) 140 amplifies to digitlization DC biasing correction I and Q sampling then to be handled to digital demodulator 144 works in succession so that I and Q data to be provided.In a particular embodiment, DVGA 140 provides 4 bit I and the Q data of chipx8.

144 couples of I of digital demodulator and Q data demodulates are to provide modulated data, and this may be provided for decoder (not shown in Figure 1) in succession.Demodulator 144 may be embodied as the rake receiver, and it can handle a plurality of signal examples with bursting out in the signal that receives.For CDMA, each coefficient of rake receiver can be designed to (1) and with multiple sinusoidal signal I and Q data be realized that rotation is to remove the frequency offset in I and the Q data, (2) multiple pseudo noise (PN) sequence of using with the transmitter place realizes de-spread to I and Q data through rotation, (3) chnnel coding (for example Walsh sign indicating number) used of transmitter place is topped to separating through the I of de-spread and Q data, and (4) use the pilot tone recovered from received signal to through separating topped I and Q data data demodulates.Digital filter 124, DC biasing canceller 130, DVGA 140 and digital demodulator 144 may be realized in one or more integrated circuits (ICs), for example in single digital signal processor.

Automatic gain control (AGC) loop unit 142 receives I and Q data and receives the DC_loop_mode signals from DC biasing canceller 130 from DVGA 140, and the gain to different variable gain element is provided in receiver unit 100.In one embodiment, the gain of amplifier 114 and direct low-converter 120 is provided for SBI unit 150, and it offers these elements by universal serial bus 152 with suitable gain controlling message then.Considered from the RF signal be input to DVGA input the time delay, the gain of DVGA 140 directly is provided for DVGA.AGC loop unit 142 provide amplifier 114, directly low-converter 120 and DVGA suitable gain make the expectation amplitude that can obtain I and Q data.The AGC loop is in following detailed description.

The different operating of controller 160 directing receiver unit 100.For example, controller 160 may guide that the DC biasing generation disappears, the operation of AGC loop, DVGA, SBI etc.Internal memory 162 provides the storage of controller 160 data and program code.

In general receiver design, the conditioning of received signal may be by one or more levels realization of amplifier, filter, frequency mixer etc.For example, the signal that receives may be amplified by one or more LNA levels.And, may be before the LAN level and/or filtering is provided afterwards, and generally after frequency downconverted, carry out.Be succinct event, these unlike signal adjustment levels concentrate in together the composition module in Fig. 1.Can also use other RF receiver design within the scope of the present invention.Amplifier 114, directly down-conversion 120 and ADCs 122 form the RF front end unit of direct down-conversion receiver.

The resolution of the I of the unlike signal processing module that Fig. 1 provides and Q sampling is used for explanation.Sampling can be adopted the bit resolution and different sampling rates of different numbers to I and Q, and this is within the scope of the invention.

The DC correction of setovering

Fig. 2 A is the module map of direct down-conversion 120a, and it is the specific embodiment of the direct low-converter 120 among Fig. 1.In direct low-converter 120a, the RF signal after the filtration of receiving filter 116 is provided for frequency mixer 212, and it also receives (plural number) LO signal from local oscillator 218.The frequency of LO signal may be controlled (this may provide by other holding wire of universal serial bus 152 or some) by frequency control signal and be set to the centre frequency of the RF modulated signal that is resumed.Frequency mixer 212 realizes that to the RF signal after filtering quadrature frequency conversion so that homophase and quadrature component to be provided, offers this adder 214 then with multiple LO signal then.

Transducer 220 receives digital DC biasing control, and it may provide and be designated SBI DC by the DC canceller 130 of setovering in Fig. 2 by universal serial bus 152.Transducer 220 realizes that then numerically controlled digital to analogy conversion is to generate the biasing controlling value of homophase and quadrature component corresponding D C1I and DC1Q.In one embodiment, these values bias current of being used to control frequency mixer 212 makes the DC biasing in the signal component to be adjusted indirectly.

Analog circuit 222 receives analog D C biasing control, and this may provide and be expressed as thick DC biasing by the DC canceller 130 of setovering in Fig. 2 A by dedicated signal lines.Analog circuit 222 realizes that then filtering and possible level shift and proportional zoom are with the DC2I that generates corresponding homophase and quadrature component and the DC bias of DC2Q.The output component of adder 214 also amplifies so that I and Q base band component to be provided through 216 filtering of low pass filter/amplifier then.

Fig. 2 B is the module map of DC biasing canceller 130a, and this is the specific embodiment of DC biasing canceller 130 among Fig. 1.DC biasing canceller 130a comprises adder 232a and 232b, DC loop control unit 234a and 234b, SBI DC offset controller 240 and DC loop control unit 242.In one embodiment, the DC biasing is corrected I and Q sampling is separately implemented.Therefore adder 232a and 232b and DC loop control unit 234a and 234b each comprise two elements, handle I for one and sample that another handles the Q sampling.

I and Q sampling after the filtration of digital filter 124 are provided for adder 232a, and it is correspondingly removed the fixedly DC bias of DC3I and DC3Q from I and Q sampling.Adder 232a may be used to remove static DC biasing (for example do not matched etc. by circuit and cause).The I and the Q output that come from adder 232a are provided for adder 232b then, and it is further removed the DC biasing of DC4I and DC4Q (234b provides by DC loop control unit) so that DC I that biasing is corrected and Q sampling to be provided from corresponding these I and Q output.

DC loop control unit 234a receives I and Q output from adder 232a, determines the DC biasing in these output, and directly among the low-converter 120a thick DC control is being offered analog circuit 222.DC loop control unit 234b receives I and Q output from adder 232b similarly, determines the DC biasing in these output and the DC bias of DC4I and DC4Q offered adder 234b.Each DC loop control unit 234 usefulness is coupled to booster element 236 realizations of accumulator 238.The certain gain that booster element 236 usefulness are selected for this loop (the DC gain I of unit 234a and the DC gain 2 of unit 234b) multiply by input I or Q sampling.Accumulator 238 adds up then and controls with the DC biasing that this loop is provided through the I of proportional zoom and Q sampling.

Directly adder 214 in the low-converter 120a and DC loop control unit 234a realize thick gain DC loop, and it removes the DC biasing in the base band component behind the direct down conversion of frequency mixer 212.Adder 232b and DC loop control unit 234b realize thin gain DC loop, and it removes still residual DC biasing after thick gain DC loop.Disclose as call, the DC loop ratio that carefully the gains DC loop that slightly gains has higher resolution.

SBI DC offset controller 240 is periodically according to the different factors, such as definite SBI DC biasing controls such as the gain of temperature, amplifier 114 and frequency mixer 212, time, drifts.SBI DC biasing control is provided for transducer 220 by universal serial bus 152 then, and this generates the DC biasing controlling value of the DC1I and the DC1Q of corresponding frequency mixer 212.

The directly realization of the DC of down-conversion receiver biasing correction, all as shown in Figure 1, in Application No. [Attorney Docket No.010118], have a detailed description, be entitled as " using the direct current biasing of the mobile station modems of direct down-conversion to offset ", submission time xxx is incorporated into this by reference.

Four groups of DC biases (DC1I and DC1Q, DC2I and DC2Q, DC3I and DC3Q, DC4I and DC4Q) are represented four kinds of different mechanism, and may be used for alone or in combination provides the DC biasing of needs to correct to direct down-conversion receiver.Thick gain DC loop (it provides the value of DC2I and DC2Q) and the DC loop that carefully gains (it provides the value of DC4I and DC4Q) may be used for dynamically removing the DC biasing in I and the Q signal component.Adder 232a (deducting DC3I and DC3Q value) may be used to remove static DC biasing.And SBI DC offset controller 240 (it provides DC1I and DC1Q value) may be used for removing dynamic and/or static DC biasing from signal component.

In an embodiment, slightly gain and carefully gain DC loop two operator scheme-acquisition modes of each support and tracing mode.Acquisition mode is used for removing quickly bigger DC biasing, this may introduce in signal component, reason has (1) step in the gain of RF/ analog circuit to change such as amplifier 114 and/or frequency mixer 212, or total DC loop of (2) property performance period DC renewal, this may cause the DC1 and/or the DC3 that offer frequency mixer 212 and/or adder 232a that new value is arranged, or (3) corresponding other reasons.Tracing mode is used to realize that the DC biasing under the normal mode corrects, and the response of its response ratio acquisition mode comes slowly.Also support difference or additional operations pattern in the scope of the invention.Catch with tracing mode may be to the DC 1 corresponding two kinds of different DC loop gain values that gain, to DC gain 2 corresponding two kinds of different DC loop gain values.

For simplifying event, thick gain and the thin DC loop that gains are called " DC loop " together simply.The DC_loop_mode control signal indicates the current pattern of DC loop.For example, the DC_loop_mode control signal may be set to logic high and be in acquisition mode to indicate the DC loop, and logic low indicates it and is in the tracing mode operation.

Numeral VGA

An aspect of of the present present invention is provided for the DVGA in the direct down-conversion receiver.DVGA can be provided for considering all or the gain ranging that a part (being that the RF/ analog circuit is irrespective that part of) needs of total dynamic range of the signal that receives.Therefore the gain that provides previous intermediate frequency (IF) in heterodyne receiver to locate to provide may be provided the gain ranging of DVGA.The design of DVGA and the DVGA position in direct down-conversion receiver structure may preferably be embodied as following description.

Fig. 3 is the module map of DVGA 140a that the digital baseband gain of I and Q sampling can be provided.DVGA 140a is the specific embodiment of the DVGA 140 of Fig. 1.

In DVGA 140a, I and Q sampling after the DC biasing correction of previous DC biasing canceller 130 are provided for multiplexer (MUX) 312 and block unit 320.For minimizing hardware, have only a digital multiplier 316 to be used for realizing the gain multiplied of I and Q sampling in the Time Division Multiplexing mode.Therefore, perhaps multiplexer 312 alternately offers multiplier 316 with Q sampling (determining if any the IQ_sel control signal) with the I sampling then by AND door 314.The IQ-sel control signal is just simply with I and Q sampling rate (for example chipx8) and the square wave (for example I being sampled as logic low) of suitable phase place is arranged.Sampling realizes the AND operation to AND door 314 usefulness DVGA_enb control signals to I or Q, and this control signal is made as logic high when DVGA enables, and is made as logic low during by bypass at DVGA.For example, if when the gain ranging that does not need DVGA or analog circuit provide gain ranging (for example variable gain amplifier), then DVGA can be by bypass.If DVGA is activated and otherwise provide zero, then therefore AND door 314 delivers to multiplier 316 with sampling.Should zero have reduced power consumption in the circuit in succession by the transfer of removing cmos circuit internal consumption power consumption.

Multiplier 316 will from the I of AND door 314 or Q sampling with multiply each other from the gain of register 344 and will offer and block unit 318 through proportional zoom (or amplification) sampling.In a particular embodiment, multiplier 316 is in the operation of the sampling rate place of twice, and promptly the sampling rate to the I/Q of chipx8 is chipx16.In a particular embodiment, for CDMA and GPS, input I and Q sampling have 18 bit resolutions, wherein 10 bit resolutions are on the right of binary point (being 18Q10), gain has 19 bit resolutions, wherein 12 bits are binary point the right (being 19Q12), and the resolution that 37 bits is arranged through the sampling of proportional zoom wherein 22 bit resolutions be positioned at binary point the right (being 37Q22).In a particular embodiment, to digital FM or DFM, input I and Q sampling have the resolution of 18Q6, and gain has the resolution of 19Q12, and the resolution of 37Q18 is arranged through the sampling of proportional zoom.Block unit 318 and block each through (for example 18) Least significant bit (LSBs) of convergent-divergent sampling and sampling through the blocking input that (CDMA/GPS is had the resolution of 18Q4, DFM is had the resolution of 18Q0) gives multiplexer 322 is provided.

To certain operator scheme of receiver, do not need the numerical scale convergent-divergent of DVGA 140a, and I and Q sampling may be sent to DVGA output and without any proportional zoom (after suitable processing is with the dateout form that obtains expectation).Block unit 320 block (for example 6) LSBs of each input sample and will block after sampling offer other input of multiplexer 322.Blocking unit 320 assurances has identical resolution no matter DVGA exports I when enabling still bypass with the Q data.

Multiplexer 322 then according to the DVGA that determines by the DVGA_enb control signal be enable or by bypass provide block accordingly unit 318 or 320 through blocking sampling.Sampling through selecting is provided for saturation unit 324 then, and it is filled sampling and makes its dateout form that meets expectation, the resolution of 8Q4 during for example to CDMA/GPS, 8Q0 during to DFM.The input that the operated in saturation post-sampling offers retardation element 326 then and arrives register 328.Half sampling period that retardation element 326 provides time delay samples to other input of register 328 with the I that arranges I and Q data (owing to realizing the distortion that half sampling period in the time division multiplexing of multiplier 316 causes) and delay when providing.Register 328 provides I and Q data then, regularly is to aim at the IQ_sel control signal.To CDMA/GPS, four most significant bits (MSBs) of I and Q data (promptly to 4Q0 resolution) are sent next processing module back to.To DFM, I and Q data (promptly to 8Q0 resolution) are directly sent back to the FM processing module.

Receiver unit 100 may be used for different application such as receiving data from cdma system, gps system, digital FM (DFM) system etc.Each this application may with have special characteristic and the signal corrections that receive some certain gain of needs accordingly.As shown in Figure 3, offer three different gains that multiplexer 332 is used for CDMA, GPS and DFM.In the gain one is selected according to the MODE_sel control signal then, and selecteed gain is provided for gain proportional zoom and bias unit 334 then, its also receiving gain biasing.

(CDMA, GPS or DFM) gain of gain proportional zoom and 334 pairs of selections of bias unit is carried out convergent-divergent to obtain the gain resolution of expectation with suitable zoom factor.For example, the AD HOC CDMA gain of using according to CDMA may provide with the bit (for example 10 bits) of a fixed number, interior a kind of (for example gain is 102.4dB and 85.3dB gain ranging to 10 bit CDMA) of several possibility gain rangings that it is topped.The selection of zoom factor will make to have identical gain resolution (for example 0.13dB) and the AD HOC used with CDMA is irrelevant through the CDMA of proportional zoom gain.Gain proportional zoom and bias unit 334 are also from deducting the gain biasing through the gain of convergent-divergent.This gain biasing is determined according to the set point of selecting for ADCs 122, otherwise this point has determined to offer the I of ADCs and the average power of Q base band component.The gain biasing may be and the programmable value that equal resolution is arranged through scalar gain, and may be provided by controller 160.

Multiplexer 336 receptions gain after the biasing of unit 334 and cross gain and one (according to Gain override control signal) these gains offered saturation unit 338.If expectation bypass VGA loop, then gain may replace the gain of VGA loop and be used excessively.Saturation unit 338 makes the gain saturation (for example to 9 bits) that receives with the scope (for example to 9 bits 68.13dB to overall gain scope, the resolution of every bit 0.133dB) of restriction through saturation gain then.AND door 340 then with the DVGA_enb control signal to realizing the AND operation through saturated gain, and if DVGA is activated or otherwise when being zero (same, for reducing the power consumption of next circuit), then will deliver to dB to linear query table (LUT) 342 through saturation gain.

In one embodiment, the AGC loop provides the yield value (for example CDMA gain) of logarithm (dB) form.The DB yield value may be used to imitate the feature of RF/ analogue variable gain circuit, and to ratio of gains controlling value, it generally has logarithm (or similar logarithm) transfer function.The second, receiving gain is used as the estimation of the transmitting power that needs in the CDMA call, and is used for when being requested received power being reported to the base station.Providing under the great dynamic range situation that receives signal, these estimations generally realize with dB.Yet owing to used linear digital multiplier 316 so that the baseband gain multiplication to be provided, the dB yield value is converted into the linear gain value.Question blank 342 is realized dB to linear transformation according to formula, and this formula is

Y (linear)=10 ^X/20Formula (1)

Wherein Y is the linear gain value of coming from question blank, and X is a pad value, may be defined as:

X=-(Z (dB)+offset) formula (2)

Wherein Z provides to the biasing in the dB yield value of question blank and the equation (2) and may be used for block (for example 4 bits being blocked offset=0.067dB) of carrying out in the compensating unit 334.May use other dB yield value to be changed into the technology of linear gain value.From the linear gain value of LUT 342 then by register 344 regularly so that the sequential of yield value is alignd with the sequential that I that offers multiplier 316 and Q sample.

The AGC loop may also be designed to according to linear (rather than dB) yield value operation, and this within the scope of the present invention.

Refer back to Fig. 1, DVGA 140 is positioned at after the DC biasing canceller 130, and outside the DC loop of direct down-conversion receiver 100.This DVGA position provides several benefits and has avoided several disadvantages.The first, if DVGA is positioned at the DC loop, then any DC biasing can be amplified by the gain of DVGA, and this can increase the weight of the deterioration that caused by the DC biasing.The second, the loop gain of DC loop also comprises the gain of DVGA, and this changes according to the energy intensity that receives signal.Because the bandwidth of DC loop that this DC loop gain has directly influenced (or determining), the DC loop bandwidth can change with the DVGA gain, and this is not desired.The DC loop bandwidth may roughly be kept constant (being the DC gain 1 and 2 in DC loop unit 234a and the 234b) in the mode that is inversely proportional to any variation in the DVGA gain by the DC loop gain of dynamic change, makes total DC loop gain maintain constant.Yet it is machine-processed complicated that this can make the DC biasing correct.And during with reference to actual signal power, residual DC biasing is variable.

By preferably DVGA 140 is placed on after the DC biasing canceller 130 with the DC loop outside, the DC biasing of DC loop is corrected and may be disengaged coupling from the proportional zoom by the signal gain of DVGA.And, in digital field, realize that in ADCs 122 backs DVGA has also simplified the RF/ Design of Simulating Circuits, this may cause the expense of direct down-conversion receiver to reduce.Owing to behind ADCs 122, provide digital gain, the amplitude that offers the signal component of ADCs may be smaller value potentially, the more great dynamic range that this may need the analog to digital conversion process makes that the ADC noise can the I of severe exacerbation through quantizing and the SNR of Q sampling.Known in the field, the ADCs that has great dynamic range may be provided by over-sampling sigma-delta demodulator.

Automatic gain control

Fig. 4 A is the module map of AGC loop unit 142a, and it is the specific embodiment of the AGC loop unit 142 of Fig. 1.In AGC loop unit 142a, I and Q data are provided for the S meter (RSSI) 412 that receives, and it estimates to receive the signal strength signal intensity of signal.The signal strength signal intensity RSS that receives may be estimated as follows:

$\mathrm{RSS}=\underset{i}{\overset{N_E}{\mathrm{\Σ}}}\{I^2\left(i\right)+Q^2\left(i\right)\}$ Formula (3)

Wherein I (i) and Q (i) represent I and the Q data of i sampling period, N _EBe to add up to derive the number of samples that received signal intensity is estimated.Can also use other technology with the signal strength signal intensity estimating to receive (RSS=∑ for example | I _F(i) |+| Q _F(i) |).The signal strength signal intensity that receives estimates to offer then AGC control unit 414.

Fig. 4 B is the module map of AGC control unit 414a, and it is the specific embodiment of the AGC control unit 414 in Fig. 4 A band.The signal strength signal intensity that AGC control unit 414a receives from RSSI 412 estimates RSS, from the DC_loop_mode control signal of DC biasing canceller 130, from the non-bypass/retentive control signal of the control unit 418 progressively of gaining, from time the gain step judgement delayed and the Freeze_enb control signal of time delay able to programme unit 420 (for example slave controller 160), all these will be described in detail following.According to control signal that receives and RSS, the AGC control unit 414a provide the output gain value, and it indicates the overall gain (G that is applied to receive signal _Total).

In one embodiment, the AGC loop is supported three kinds of loop pattern-normal modes, low gain mode and freezing modes.Normal mode is used to provide specified AGC loop bandwidth, and low gain mode is used to provide less AGC loop bandwidth and freezing mode to be used to freeze the AGC loop.Low gain and normal mode are relevant with the AGC loop gain value of corresponding AGC gain 1 and AGC gain 2.Freezing mode is by offering the value vanishing realization that the AGC loop accumulator adds up.In one embodiment, the additional AGC loop gain value of AGC gain 3 is used for Interference Detection.AGC gain 3 generally under normal mode less than AGC gain 2, but under low gain mode greater than AGC gain 1, and as described belowly be used to detect the interference that in signal component, exists.The difference or the additional modes that also have the AGC loop to support in the scope of the invention.

As mentioned above, the performance of DC loop affects AGC loop.Therefore, on the one hand, the specific AGC loop pattern of use depends on the specific DC loop pattern of (promptly optionally based on) current use.Particularly, the AGC loop uses normal mode when the DC loop is operated with tracing mode, and the AGC loop uses gain or freezing mode when the DC loop is operated with acquisition mode.

Shown in Fig. 4 B, the AGC gain 3 of the AGC of general mode gain 2 and Interference Detection offers multiplexer 446, and it also receives non-bypass/retentive control signal.Non-bypass/retentive control signal may be used to provide the time lag (it is preceding promptly to be allowed to switch to another gain step size (higher or lower) at it, and the AGC loop maintains preset time (time 1 or time 2) on certain given gain stage step-length) between the gain step.

When selecting normal mode, multiplexer 446 provides AGC gain 2 then, and this indicates by non-bypass/retentive control is set at logic low.Perhaps, when realizing Interference Detection, multiplexer 446 provides AGC gain 3, and this indicates by non-bypass/retentive control is set at logic high.Multiplexer 448 receives the AGC gain 1 of low gain modes, and in the output of the multiplexer 448 of two input, and receive the DC_loop_mode control signal.When the AGC loop was selected low gain mode when the DC loop is in acquisition mode, this was set at logic high by DC_loop_mode control and indicates, and multiplexer 448 offers multiplier 442 with AGC gain 1 then.Perhaps, multiplexer 448 offers multiplier 442 with AGC gain 2 or AGC gain 3 during tracing mode, and this is made as logic low by DC_loop_mode control and indicates.

The signal strength signal intensity that AND door 440 receives is estimated RSS and Freeze_enb control.AND door 440 offers RSS multiplier 442 then, and this occurs in when (1) DC loop and operates with acquisition mode as DC with tracing mode operation or (2), when the AGC loop uses the low gain mode operation.Perhaps, when the DC loop is in freezing mode with acquisition mode operation and AGC loop, AND door 440 provides zero to multiplier 442.Cause when the AGC loop is frozen, adding up from zero of AND door 440 by zero of AGC loop accumulator 444.

Multiplier 442 will receive signal strength signal intensity and estimate that RSS and the AGC gain from the selection of multiplexer 448 multiply each other, and the result is offered AGC loop accumulator 444.Accumulator 444 adds up the result with value for storage then and provides one to be indicated as being overall gain G _TotalThe output gain value to be used for received signal to obtain the signal level of expectation, this is to be determined by the gain biasing of gain proportional zoom that offers Fig. 3 and bias unit 334.This overall gain may be divided into the thick gain G of two parts (1) RF/ analog circuit (for example amplifier 114 and frequency mixer 212) _CoarseAnd the thin gain G of (2) DVGA 140 _FineTherefore the overall gain that receives signal may be expressed as:

G _Total=G _Coarse+ G _FineFormula (4)

Wherein, G _Total, G _CoarseAnd G _FineAll show out with dB.

Shown in Fig. 4 B, accumulator 444 is gone back gain step judgement behind the receive time delay, as described below it indicated the specific discrete gain that is used for the RF/ analog circuit.The discrete gain of each RF/ analog circuit may be relevant with the corresponding one group of minimum and maximum value that adds up, and this has guaranteed the stability of AGC loop.To the specific discrete gain of using, as the time indicate in the gain step judgement delayed, accumulator 444 uses one group of suitable minimum and maximum value group to be used to add up.

Refer back to Fig. 4 A, the thick gain controlling of RF/ analog circuit is that (1) that obtains in the following manner is with overall gain G _TotalBe mapped to the judgement of gain step by gain step control unit 418, (2) become suitable gain step control by the scope encoder 424 step judgement coding that will gain, (3) turn to suitable message by the SBI unit 150 step control format that will gain, (4) send a message to RF/ analog circuit (for example amplifier 114 and/or frequency mixer 212) by universal serial bus 152, (5) adjust the gain of RF/ analog circuit according to message.Thin gain controlling obtains (1) to DVGA by following mode, by from overall gain G _TotalIn deduct thick gain G _CoarseDetermine thin gain G _FineAnd (2) are according to the gain of thin gain-adjusted DVGA.Below describe according to overall gain and derive thick and thin gain.

The frequency mixer 212 that receiver unit 100 may be designed to have the amplifier 114 of multistage (for example level Four) and multistage (for example two-stage) arranged.Every grade may be relevant with the specific discrete gain.Be in ON/OFF according to any level, may obtain different discrete gains.The gain of RF/ analog circuit is controlled in thick gain then with thick discrete steps.The specific discrete gain that is used for the RF/ analog circuit is according to the design that receives signal level, specific these circuit etc.

Fig. 4 C is the chart of gain transfer function one example of RF/ analog circuit (for example amplifier 114 and frequency mixer 212).Transverse axis is represented overall gain, this with receive signal strength signal intensity be inversely proportional to relevant (high-gain corresponding low received signal intensity).The gain step judgement that longitudinal axis representative gain step control unit 418 is made according to overall gain.In this particular case design, the judgement of gain step may be got in five probable values, is defined by table 1.

Table 1

The judgement of gain step	The RF/ analog circuit state	Definition
			000	First kind	Lowest gain-all LNA levels are in OFF, and frequency mixer is in low gain
001	Second kind	Second lowest gain-all LNA levels are in OFF, and frequency mixer is in high-gain
			010	The third	The 3rd highest-gain-one a LNA level is in ON, and frequency mixer is in high-gain
011	The 4th kind	Second highest-gain-two a LNA level is in OFF, and frequency mixer is in low gain
			100	The 5th kind	Highest-gain-all three grades of LNA are in ON, and frequency mixer is in high-gain

Shown in Fig. 4 C, provide slow when between adjacent states, shifting.When for example being in second state (" 001 "), the one LNA does not become ON (transferring to the third state " 010 ") and surpasses L2 rising threshold values up to overall gain, and this LNA does not become OFF (shifting back first state from second) and drops under the L2 decline threshold values up to overall gain.Slow (L2 rising-L2 decline) if prevented overall gain L2 rise and L2 decline threshold values between or near the time LNA be in OFF and ON continuously.

Gain step control unit 418 be determined the judgement of gain step according to overall gain, transfer function such as Fig. 4 C shown (by the threshold values definition) and timing, interference and other possibility message.Gain step judgement is to indicate a specific order that amplifier 114 and frequency mixer 212 will become ON/OFF.Refer back to Fig. 4 A, gain step control unit 418 offers retardation element 420 able to programme and the 424 gain step judgements of scope encoder.

In an embodiment and Fig. 1 illustrate, offer every grade ON of these circuit pair amplifiers 114 and frequency mixer 212 and the control of OFF by universal serial bus 152.The judgement of scope encoder 424 receiving gain steps also provides the gain step of the particular electrical circuit correspondence that will control each to control (for example gain step of a pair amplifier 114 control, another is to gain step control of frequency mixer 212).Mapping between judgement of gain step and the control of gain step may be according to question blank and/or logic.Each gain step control comprises one or more bits, and the assigned stages in the circuit of being controlled by this gain step control realizes ON/OFF.For example, amplifier 114 may design with level Four, and the control of its (2 bit) gain step may be relevant with four probable values (" 00 ", " 01 ", " 10 ", " 11 ") of four of amplifier possible discrete gains.Frequency mixer 212 may be designed to two-stage, and the control of its (1 bit) gain step may with two of frequency mixer may discrete gains two probable values (" 0 " and " 1 ") relevant.The gain step control of amplifier 114 and frequency mixer 212 is formatted as suitable message by SBI unit 150, and these message are sent to circuit by universal serial bus 152 then.Scope encoder 424 also offers DC biasing canceller 130 1 gain step variable signals, and it indicates the gain of RF/ analog circuit and whether changes into a new value or new step-length.

As mentioned above, receive the overall gain G of signal _TotalMay be divided into thick gain G _CoarseAnd thin gain G _FineAnd shown in Fig. 4 A, thin gain deducts thick gain by adder 416 and generates from overall gain.Because thick gain (with gain step control forms) is provided for amplifier 114 and frequency mixer 212 by SBI unit 150, determines by gain step control unit 418 and should thick gain actually introduce a time delay between by the RF/ analogue circuit applications in thick gain.And, receive signal from the RF circuit to DVGA and can run into processing delay (for example particularly digital filter 124).Therefore, for guaranteeing slightly to gain and from DVGA, removing (promptly making thick gain only any given data sampling be used once) simultaneously by the RF circuit application, before it was applied to DVGA 140, time delay able to programme was used to delay time and slightly gains (as being pointed out by the judgement of gain step).

Retardation element 420 able to programme provides the specific delay volume of gain step judgement.This delay compensation the time delay introduced by SBI unit 150 and the time delay that receives signal processing path from the RF circuit to DVGA.This time delay may be programmed by time delay value is write register.Retardation element 420 provides the gain step judgement through time delay then.

Thick gain conversions unit 422 receives the gain step judgement through time delay, and it indicates the specific discrete gain of RF/ analog circuit, and the corresponding thick gain G that has OK range and resolution is provided _Coarse(for example with from the overall gain of AGC control unit 414 same scope and resolution).Therefore thick gain is equivalent to the judgement of gain step but is provided (promptly thick gain be high resolution value and the step that gains judgement be numeral (ON/OFF) control) with different forms.The conversion that the gain step is adjudicated thick gain may obtain by question blank and/or logic.Adder 416 deducts thick gain so that the thin gain of DVGA to be provided from overall gain then.

Whenever when changing the RF/ analog circuit by stage of switches ON and OFF and gain certain thick value, the phase place of signal component is generally rotated certain particular step size value.The amount of phase rotation depend on which level transfers ON and OFF (as what determined by the judgement of gain step) to but be the fixed value that is used for this specific setting or configuration.This phase place rotation may cause the deterioration in the data demodulates processing, up to there being frequency control loop can correct this phase place rotation.

In an embodiment, gain step judgement is mapped to corresponding circulator phase place, and this has indicated because the gain that the control of gain step indicates and the amount of phase rotation in receiving signal component.This circulator phase place is provided for the circulator in digital demodulator 144 then, and is used to adjust the phase place of I and Q data with the phase place rotation of compensation by the introducing of the gain stage in the RF/ analog circuit of enabling.Mapping at judgement of gain step and circulator phasetophase may obtain by question blank and/or logic.And, may obtain the thin resolution (for example may obtain the resolution of 5.6 degree) of circulator phase place with 6 bits to the circulator phase place.

DC and AGC line loop

As shown in Figure 1, the DC loop to the I after the filtration of digital filter 124 and Q sampling operation removing the DC biasing, and AGC loop (by DVGA 140) after biasing is corrected to DC I and the Q sampling operation so that the I and the Q data that will offer digital demodulator 144 to be provided.The AGC loop is also controlled the gain of RF/ analog circuit, otherwise this influence is by the I of DC line loop and the amplitude of Q sampling.Therefore the DC loop may be regarded as being embedded in the AGC loop.The operation of the operating influence AGC loop of DC loop.

In direct down-conversion receiver, owing to littler signal amplitude reason, DC biasing (static and time change) has more influence to signal component.Bigger DC biasing (or DC spiking) may be introduced signal component in a different manner.The first, when the gain (for example amplifier 114 and frequency mixer 212) of RF/ analog circuit changes with discrete steps by changing the ON/OFF level, may in signal component, introduce bigger DC biasing owing to switch interior not the matching not at the same level of ON/OFF level.The second, when the DC loop realizes that the DC biasing is upgraded, offer the different DC biases of the DC3I of adder 232a and DC3Q by universal serial bus and/or offer the DC1Q DC bias different of frequency mixer 212 with DC1Q, this may introduce big DC biasing.

Big DC biasing may use the different mechanisms of DC loop to remove (for example, thick gain and thin gain loop DC loop).And big DC biasing may be in the DC loop of acquisition mode and is removed quickly by operation.Yet, being removed up to them, big DC biasing has deleterious effects and may make performance degradation signal component.

The first, the de-spread operation back that any DC that does not remove in the signal component is biased in digital demodulator 144 (its power equals the DC biasing) occur as noise.This noise can make mis-behave.

The second, the performance of AGC loop is disturbed in big DC biasing in several modes.The DC biasing adds signal component, has caused combination (DC biasing and the signal) component that has by a relatively large margin.Then this causes that the AGC loop reduces overall gain and makes the power of combination component maintain AGC set point (I for example ²+ Q ²=AGC set point).The gain of this minimizing can cause the compression to desired signal components, and decrement is directly proportional with the amplitude of DC biasing.Desired signal components cause more by a small margin degraded signal to quantizing noise than (SNR _Q), it also can cause deterioration to performance.And if the DC loop can not be removed big DC biasing fully before it enters tracing mode, then residual DC is biased in the tracing mode and will be removed more slowly.The AGC loop can be followed the slow indicial response of this DC loop, and this deterioration period that can cause prolonging reaches stable state up to DC and AGC loop.

The 3rd, big DC biasing influences and accurately detects interference capability, disturbs in the desired signal frequency band signal is produced interference.Interference may be by the non-linear generation in the circuit that receives on the signal path.Since in amplifier 114 and the frequency mixer 212 non-linear when these circuit during with high gain operation (have and more be in ON) more remarkable, detect interference after any one that receiver may be in these circuit switches to high-gain.Interference Detection may realize that the power that will measure and threshold values compare by the power with RSSI 412 measuring-signal component after switching to high-gain after specific Measuring Time section, the existence of announcing to disturb if measurement power surpasses threshold value.If detect interference, the gain that then may reduce one or more circuit is to remove or to slow down interference.Yet, having under the DC bias conditions of introducing by switching to high-gain, may not distinguish that the increase of measuring power is owing to disturb or because the cause of overall noise, this comprises the DC biasing of not removing and the DC loop noise of the increase that generated to remove the DC biasing sooner by the DC loop that operates in acquisition mode.Therefore, the existence of DC biasing may influence accurate detection interference capability, if the RF/ analog circuit is because wrong Interference Detection and may degrade performance during with the gain operation of mistake.

Big DC biasing may be owing to above-mentioned different deleterious effects cause long burst error.Because the time that removing the DC spiking needs may be the particular design decision of DC loop (for example by) of fixing, the deterioration that is caused by the DC biasing causes bigger problem when high data rate place more, and this can cause in the more error in high data rate place more.

According to a further aspect in the invention, the DC loop was inversely proportional to the bandwidth that is in the DC loop of acquisition mode with the duration of acquisition mode operation.The DC loop bandwidth is designed to when acquisition mode bigger to allow the DC loop to respond and remove the DC biasing quickly.The loop response progressively accelerated of the loop bandwidth correspondence of Zeng Daing progressively.As mentioned above, the DC error in the signal component of expectation is shown as noise after the de-spread operation of digital demodulator 144.This noise should be removed as quickly as possible, and this can realize by the bandwidth that increases the DC loop under the acquisition mode.Yet bigger DC loop bandwidth has also caused the DC loop noise of the increase of possibility degrade performance.

Be optimize performance, acquisition mode is compromise between the DC loop noise of the DC loop noise that will correct of (introducing) and (self-generating).For restriction DC loop noise amount but still allow the DC loop with high bandwidth operation, the DC loop may be set to loop bandwidth in the time of acquisition mode operation and be inversely proportional to.Because bigger loop can be made response faster, the general corresponding shorter DC biasing capture time of bigger DC loop bandwidth.Therefore, be to have utilized this fact in the short time of acquisition mode internalization expense that has big DC loop bandwidth, and the DC loop can operate the time that surpasses necessity in acquisition mode, this also can improve performance.

Operation be in the special time period of the DC loop of acquisition mode may be also according to different other factors and selected, such as, for example amplitude, the modulation scheme of the expectation amplitude of DC biasing, DC loop noise, receive the bandwidth of signal etc.Generally, it is relevant that acquisition mode duration and the DC loop bandwidth that is in acquisition mode are inversely proportional to, and function depends on the above-mentioned factor accurately.

According to a further aspect in the invention, DC line loop pattern is depended in the operation of AGC loop.As mentioned above, any DC that does not remove general bigger when the DC loop becomes acquisition mode setovers, and can influence the operation of AGC loop.Therefore, DC biasing canceller 130 provides the DC_loop_mode control signal to AGC loop unit 142, and this has indicated the current operator scheme of DC loop.Setover with the big DC that removes (potential) quickly when the DC loop switches to acquisition mode, the AGC loop may switch to low gain mode simultaneously or freezing mode makes when the DC loop is in acquisition mode, and the AGC loop responds or do not respond the DC biasing more slowly.The AGC loop may switch back normal mode after the DC loop is transferred to tracing mode.

Little or the zero AGC gain of using when the DC loop is in acquisition mode has guaranteed that the AGC loop keeps its control signal when the DC acquisition phase.In case the AGC control signal is operated with normal mode after the DC loop enters tracing mode.AGC gain less or zero also hinders or stops the AGC loop that desired signal components power is removed from the AGC set point, and further reduces the influence of DC biasing in Interference Detection is handled, and this can reduce the possibility of wrong Interference Detection.

The specific normal and less AGC gain of using may be determined by emulation, empirical value measurement or some other methods.These gains may be programmable (for example by controllers 160).

Serial bus interface (SBI)

According to invention on the other hand, of RF/ analog circuit or all control are provided by universal serial bus 512.Use standard serial bus to provide many benefits so that control RF/ analog function is as described below.And universal serial bus may as described belowly be designed to have different characteristic so that the control of needs more effectively to be provided.

Generally, use to want controlled circuit and provide special signal between the controller of control that control to RF/ analog circuit (for example amplifier 114 and frequency mixer 212) is provided.On the controller of each circuit that will control separately, specify one or more lead-in wires.For example, may on controller and RF/ analog chip, specify three lead-in wires to control the Pyatyi of above-mentioned amplifier/frequency mixer.Using the lead-in wire of appointment for specific function has increased pin count and has made plate face layout more complicated, and this may cause the receiver expense to increase.

Use universal serial bus can improve many in traditional design, run into unfavorable and additional benefit can also be provided with the control that the RF/ analog circuit is provided.The first, universal serial bus can realize that (for example two or three) and these same lead-in wires can be used to provide to being implemented in the control of a plurality of circuit in one or more integrated circuits (ICs) with seldom lead-in wire.For example, single universal serial bus can be used to the gain of control amplifier 114, the gain of frequency mixer 212, the DC biasing of frequency mixer 212, the frequency of oscillator 218 etc.By the connect number of RF/ analog IC and the needed lead-in wire of controller of minimizing, the expense of RF/ analog IC, controller and circuit board face all can reduce.The second, because it is with the hardware interface standardization between RF/ analog IC and controller, use standard serial bus to increase the flexibility of chip setting in the future.This makes manufacturer to realize different RF/analog IC s and/or controller on same plate face layout under the situation that does not change or do not increase the control line number that needs.

In one embodiment, SBI unit 150 is designed to support many hardware requests (HW_REQ) channel, and each can be used to support specific function.For example, a channel may be used for the VGA loop and gain with the step of setting amplifier 114 and frequency mixer 212, and another channel may be used for the DC loop to set the DC biasing controlling value (DCI) of frequency mixer 212.Generally, the SBI unit may be designed to support the hardware requests channel of any number.

Separately the circuit of control may be relevant with corresponding address for each.Each message that sends by the SBI unit comprises the address of the circuit that this message will send to.Each circuit that is coupled to universal serial bus will check that then being included in each sends address in message determining whether message sends to this circuit, and is to handle this message when sending to this circuit at it only.

In one embodiment, each hardware requests channel may be designed to have the ability of supporting many data-transmission modes.This can comprise quick transmission mode (FTM), interrupt transmission mode (ITM) and burst or a large amount of transmission mode (BTM).This quick transmission mode may according to following modes be used for a plurality of bytes send to a plurality of circuit: ID, ADDR, DATA, ADDR, DATA... wherein ID be the ID of hardware requests channel, ADDR is the address of receiving circuit, DATA is the data of receiving circuit.The interruption transmission mode can be used for launching single byte and is used to be broadcast to one or more circuit that are coupled to universal serial bus.And the burst transfer pattern can be used for a plurality of bytes are sent to particular electrical circuit with following modes: ID, ADDR, DATA1, DATA2... may realize difference and/or additional transmission mode within the scope of the present invention.

In one embodiment, the hardware requests channel may be assigned with particular priority (for example by controller).The priority of channel may be incorporated into the register in the SBI unit 150.If a plurality of message that will be sent on universal serial bus by the SBI unit are arranged, the order that can decision message sends of the priority of channel then.The channel that may distribute to the control loop that is used for the quick response of needs is with higher priority (for example gain step of amplifier 114 and frequency mixer 212), (for example may distribute to the lower priority of the channel that is used for how static function, the receiving mode of direct low-converter 120, for example DFM and GPS).

Each hardware requests channel may be also with indicate accordingly whether channel be activated to enable mark relevant.May keep the mark of enabling of all channels by SBI unit 150.

In an embodiment, universal serial bus comprises three signal-data-signals, clock signal and signal strobes.Data-signal is used to send message.The data that clock signal provides (for example controller) by the sender and is used for by receiver providing on the latch data signal.And signal strobe is used to indicate the beginning of message/stop.Can also realize having the universal serial bus of unlike signal design and/or unlike signal quantity within the scope of the present invention.

Direct down-conversion receiver described here may be realized in different wireless communication systems, such as cdma system, CPS system, digital FM (DFM) system etc.Directly the down-conversion receiver may also be used for forward link or the reverse link in these communication systems.

Direct down-conversion receiver described here may be realized by different way.For example, directly all or part of down-conversion receiver may realize with hardware, software or both combinations.Hardware is realized DVGA, DC biasing correction, gain controlling, SBI etc. can be implemented in one or more application-specific integrated circuit (ASIC)s (ASICs), digital signal processor (DSPs), digital signal processing appts (DSPDs), programmable logic device (PLDs), field programmable gate array (FPGAs), processor, controller, microprocessor, microcontroller, be used to realize other electronic unit or other above any combination of the function described.

Software is realized the element that is used for gain controlling and/or DC biasing correction may be realized (for example, process, function etc.) with the module that realizes function described here.Software code may be stored in internal storage location interior (for example internal memory 162 of Fig. 1) and be that processor is carried out (for example controller 160).Internal storage location may realize in processor or outside the processor that under the external circumstances, it can be communicated by letter with going up and be coupled to processor by distinct methods known in the field.

Title is used herein to the material that generally indicates announcement, is not meant to limit the present invention scope.

The description of above preferred embodiment makes those skilled in the art can make or use the present invention.The various modifications of these embodiment are conspicuous for a person skilled in the art, and Ding Yi General Principle can be applied among other embodiment and not use creativity here.Therefore, the embodiment that the present invention is not limited to illustrate here, and will meet and the principle and the novel feature the most wide in range consistent scope that disclose here.

Claims (8)

1. method of handling desired signal in wireless communication system is characterized in that comprising:

Amplify desired signal with first gain that has coarse resolution;

Through the single frequency down conversion stage amplifying signal is down-converted to base band from radio frequency (RF);

Will be through the down signals digitlization so that sampling to be provided; And

With second gain that has high-resolution sampling is amplified the dateout that has the desired signal amplitude to provide with digital form.

2. the method for claim 1 is characterized in that also comprising:

The DC that corrects in sampling with the DC loop setovers, and wherein the DC biasing is corrected to sample and is exaggerated with digital form.

3. direct down-conversion receiver is characterized in that comprising:

The RF front end unit is used for amplifying to the received signal, down-conversion and digitlization to be to provide sampling;

Digital variable gain amplifier (DVGA) is used for amplifying sampling so that the dateout that has the desired signal amplitude to be provided with first gain; And

Automatic gain control (AGC) loop is used for part provides DVGA according to dateout first gain.

4. down-conversion receiver as claimed in claim 2 is characterized in that also comprising:

DC biasing canceller is used to correct the DC biasing in the sampling, and wherein DVGA is used to amplify the sampling of correcting through the DC biasing.

5. down-conversion receiver as claimed in claim 2 is characterized in that the AGC loop also is used to provide second gain of RF front end unit.

6. the device of a wireless communication system is characterized in that comprising:

Amplify first device of received signal;

Offset the device of the DC biasing in the amplifying signal;

Second device of the signal that digital amplification offsets through DC biasing; And

Measurement is through the device of digital amplifying signal, to control the gain of first and second amplifying devices.

7. receiver unit is characterized in that comprising:

The analogue variable gain amplifier;

Be coupled to the DC biasing canceller of analogue variable gain amplifier;

Gain controller is used to measure the gain of exporting and control analog-and digital-variable gain amplifier from the next signal of digital variable gain amplifier; And

Serial bus interface (SBI) unit is used for providing the analogue variable gain Amplifier Gain by universal serial bus.

8. receiver unit is characterized in that comprising:

The RF front end unit is used for amplifying to the received signal, down-conversion and digitlization to be to provide sampling;

The DC loop is used to offset the DC biasing in the sampling;

Digital variable gain amplifier (DVGA) is used for first gain dateout that has the desired signal amplitude to provide being amplified in the sampling that offsets through the DC biasing;

Automatic gain control (AGC) loop, being used for part provides first gain and provides second gain to the RF front end unit to DVGA according to dateout; And

Serial bus interface (SBI) unit is used for providing second gain to the RF front end unit.

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