CN1901344A - Voltage reference circuit of pulse width modulation - Google Patents

Abstract

This invention discloses a voltage primary circuit for a pulse width modulator including a soft start-up circuit, a band-gap primary circuit and a small current charge circuit, in which, the soft start up circuit provides suitable offset to the band-gap primary circuit to start it up smoothly, the output end of the primary signal VREFO is connected with the small current charge circuit, which uses the obtained small current to charge a rather big capacitor to rise the output signal VREF of the entire primary circuit steadily.

Description

The voltage reference circuit of pulse width modulator

One, technical field

The DC/DC pulse width modulator belongs to the class in the power management chip, the present invention relates to a kind of voltage reference circuit that is applicable to this pulse width modulator.

Two, background technology

The DC/DC pulse width modulator occupies very big proportion in power management chip, and portable product particularly consumer electronics field obtained widely using.

Fig. 1 has provided a kind of basic circuit structure of pulse width modulator (PWM) commonly used, by error amplifier, start-up circuit and reference circuit, phase compensation, PDM keyer, comparator, slope generator and oscillator, buffering drives these several modules and constitutes, and reference voltage module wherein is common band-gap reference circuit.

Fig. 2 is based on the Organization Chart of the step-up DC/DC transducer of pulse length modulation principle, and chip wherein partly is exactly a content shown in Figure 1.

Below we are that example is introduced the reason that the system output voltage produces overshoot with step-up DC/DC pulse width modulator.

When system started working, reference voltage moment startup or delay a period of time started, and promptly in a short period of time, reference voltage just reaches about 1.2V.Because this moment, circuit was just started working, VOUT voltage also reaches normal voltage value Vo far away, and input voltage V+, the V-of error amplifier are respectively

V ₊＝β*(V _IN-V _L-V _D)

V-＝VREF＝β*V _O＝β*V _IN/1-D

$\mathrm{\&beta;}=\frac{\mathrm{Rb}}{\mathrm{Ra}+\mathrm{Rb}}<1,$ V _INBe input voltage, V _LAnd V _DBe respectively the pressure drop of inductance and diode, D＜1 is the duty ratio of pulse width modulator output square-wave signal EXT.

By top formula as can be seen, when system just started working, the voltage difference that is input to error amplifier was very big, makes error amplifier be output as minimum, and comparator is output as height like this, drove back output (EXT) output high level through buffering.

In V+, V-differed bigger a period of time, EXT output was high level, and the power tube in the control chart 2 is held open state, like this power supply V _INTo induction charging, VOUT voltage is risen rapidly, and, make VOUT surpass normal output voltage V because the inductance energy stored is not in time emitted ₀, produced overshoot phenomenon thus.

More than be to have the reason that produces overshoot phenomenon when the pulse width modulator system has just started now, the most basic is that the startup of band gap voltage and the foundation of output voltage V o exist a time difference.

Three, summary of the invention

For solving above-mentioned technical problem, the invention provides a kind of voltage reference circuit towards the DC/DC pulse width modulator, the output voltage of this voltage reference circuit by making band-gap reference slowly rises and eliminates or the overshoot when reducing the DC/DC pulse width modulator and starting, and the Power Supply Rejection Ratio of band-gap reference circuit (PSRR) performance increases substantially.

A common band-gap reference circuit (2) and soft starting circuit (1) at first to be arranged, as shown in Figure 3.Reference voltage V REF0 about this band-gap reference output 1.2V.

Fig. 4 is a kind of pattern of charging to big electric capacity by big resistance limits electric current that we tentatively imagine, VREF0 is the band-gap reference of reference circuit output, VREF is the V-signal that finally outputs to error amplifier, and the difference of these two signals and the ratio of resistance have determined the size of the charging current of electric capacity.

But if will obtain the suitable charging interval (as 1ms), we need one several million resistance and the electric capacity of pF up to a hundred, and huge resistance and electric capacity (particularly electric capacity) can be wasted the very big area of chip, are unfavorable on the sheet integrated.

Fig. 5 is the circuit solution that the present invention adopts.Gate pmos utmost point ground connection, source end are connected the reference signal VREF0 that is produced by band-gap reference circuit with substrate terminal, drain terminal connects a capacitor C, the other end ground connection of electric capacity.The output signal VREF of entire circuit is drawn by the drain terminal of PMOS.Reference voltage V REF0 is about 1.2V, just greater than but relatively near the threshold voltage of PMOS pipe under the common process, and the breadth length ratio that makes this PMOS pipe can be regarded it as a big resistance like this much smaller than 1, and its integrated area can be far smaller than the resistance of similar resistance.Even under electric capacity was not very big situation, the breadth length ratio that also can regulate the PMOS pipe reduced charging current, the rise time that prolongs VREF is to a millisecond magnitude.

The present invention uses a band gap voltage module that can slowly start, the band-gap reference of output slowly rises, and can rise synchronously with VOUT voltage, so just can not exist V+, V-to differ bigger phenomenon, error amplifier and comparator are operated in non-extremity among Fig. 1 like this, and buffering drives the output square-wave signal, thereby the switch of power controlling pipe slowly rises the output voltage of circuit, up to arriving normal output voltage V o, when starting, can not produce or very little overshoot phenomenon only arranged.

In addition,, be equivalent between supply voltage VDD and output band gap voltage VREF, add a limit again, can improve the Power Supply Rejection Ratio (PSRR) of reference circuit so to a great extent with circuit structure output shown in Figure 5.

Four, description of drawings

Fig. 1 is a kind of basic circuit structure of pulse width modulator (PWM) commonly used.

Fig. 2 is based on the Organization Chart of the step-up DC/DC transducer of pulse width modulator.

Fig. 3 is a structural representation of the present invention.

Fig. 4 be a kind of by big resistance current limliting to big capacitor charging circuit.

Fig. 5 makes VREF slowly rise to the circuit of VREF0 by PMOS pipe current limliting to the electric capacity charging among the present invention.

Fig. 6 is the reference voltage transient state startup figure that adopts the low current charge circuit and do not adopt this circuit to obtain.

Fig. 7 is the system start-up transient state analogous diagram that adopts the low current charge circuit and do not adopt this circuit to obtain.

Fig. 8 is the Power Supply Rejection Ratio analogous diagram that adopts the low current charge circuit and do not adopt the reference voltage that this circuit obtains.

Five, embodiment

For structure and principle to circuit of the present invention have further understanding, describe in detail below in conjunction with accompanying drawing.

Fig. 3 is an example of band-gap reference circuit of the present invention.It comprises soft starting circuit 1, band-gap reference circuit 2 and low current charge circuit 3,

Band-gap reference circuit 2 is the common band gap that obtain by temperature compensation principle, adopts the common-source common-gate current mirror structure can improve Power Supply Rejection Ratio (PSRR).

Soft starting circuit 1 is simple start-up circuit commonly used, is made of an inverter and a NMOS pipe.

Low current charge circuit 3 is the core circuits that slowly started reference voltage.The breadth length ratio of PMOS pipe P13 is very little, and capacitor C 2 is bigger, and the charging interval is longer relatively, and its process is as follows:

A: when VREF0 just set up, VREF voltage was less, as VREF≤V _THPThe time, the PMOS pipe is in the saturation region, and this moment, charging current was

$I=\frac{1}{2}{\mathrm{\&mu;}}_P{C}_{\mathrm{OX}}\frac{W}{L}{(\mathrm{VREF}0-V_{\mathrm{THP}})}^2$

By following formula as seen, electric current remains unchanged substantially, and VREF is linear to rise.

B: as VREF 〉=V _THPThe time, PMOS pipe P13 is in linear zone, and this moment, charging current began to reduce, and the VREF rate of voltage rise reduces.

C: as VREF 〉=2V _THPDuring-VREF0, the PMOS pipe is in dark linear zone, and charging current is

$I={\mathrm{\&mu;}}_P{C}_{\mathrm{OX}}\frac{W}{L}(\mathrm{VREF}0-V_{\mathrm{THP}})(\mathrm{VREF}0-\mathrm{VREF})$

Electric current is along with the rising of VREF reduces rapidly, and VREF slowly rises up to VREF=VREF0.

For common process, the threshold voltage of PMOS is mostly 0.8---between the 1.0V, so the charging interval also will have than big-difference because technology is different, generally between the hundreds of microsecond is to several milliseconds.Suitably regulate the breadth length ratio of PMOS pipe With the size of electric capacity, can obtain the appropriate charging interval.

Fig. 6 is the startup figure that adopts the VREF of low current charge circuit voltage benchmark and do not adopt the VREF0 of low current charge circuit, and as seen, the startup of VREF has the slope of about 1ms clearly to postpone.

This circuit application can reduce even the overshoot of the output voltage when powering on of elimination system fully to a great extent to the DC/DC pulse width modulator, and the Power Supply Rejection Ratio (PSRR) of reference voltage is improved greatly in middle and high frequency range.

Fig. 7, Fig. 8 adopt low current charge circuit 3 and do not adopt system start-up transient state analogous diagram that this circuit obtains and the Power Supply Rejection Ratio of reference voltage.VOUT1 is system's output waveform of not using circuit of the present invention among Fig. 7, and VOUT2 is the system's output waveform that adopts circuit of the present invention, the about 1ms of benchmark delay start as seen from the figure, and the VOUT2 signal does not just have overshoot phenomenon fully.The power supply rejection performance that obtains of VRFE signal will exceed the VREF0 signal far away in middle and high frequency range as can be seen from Figure 8.

Claims (3)

1, a kind of voltage reference circuit of pulse width modulator, it is characterized in that: it comprises soft starting circuit (1), band-gap reference circuit (2) and low current charge circuit (3), described soft starting circuit (1) provides suitable biasing for band-gap reference circuit (2), and makes its smooth startup; The reference signal VREF0 output of band-gap reference circuit (2) is connected with low current charge circuit (3); Low current charge circuit (3) to big electric capacity charging, slowly rises the output signal VREF of whole reference circuit with the little electric current that obtains.The overshoot of output voltage when this circuit can reduce even eliminate fully the DC/DC pulse width modulator to a great extent and powers on, and the PSRR of reference voltage is improved greatly in middle and high frequency range.

2, the voltage reference circuit of pulse width modulator according to claim 1 is characterized in that: described low current charge circuit (3) comprises a PMOS pipe and an electric capacity; Described PMOS pipe P13 grounded-grid, the source end is connected with the reference signal VREF0 output of substrate terminal with band-gap reference circuit (2), and drain terminal connects a capacitor C 2, the other end ground connection of capacitor C 2, the output signal VREF of whole reference circuit is drawn by the drain terminal of P13.

3, the voltage reference circuit of pulse width modulator according to claim 2 is characterized in that: the breadth length ratio of described PMOS pipe P13 is very little, and capacitor C 2 is bigger, and the charging interval is longer, and its process is as follows:

A: when VREF0 just set up, VREF voltage was less, as VREF≤V _THPThe time, the PMOS pipe is in the saturation region, and this moment, charging current was

$I=\frac{1}{2}{\mathrm{\&mu;}}_P{C}_{\mathrm{OX}}\frac{W}{L}{(\mathrm{VREF}0-V_{\mathrm{THP}})}^2$

In the formula, V _THPBe the threshold voltage of PMOS pipe, μ _PBe the mobility in hole, C _OXBe the gate oxide electric capacity of unit are, It is the breadth length ratio of PMOS pipe.This stage electric current remains unchanged substantially, and VREF is linear to rise;

B: as VREF 〉=V _THPThe time, PMOS pipe P13 is in linear zone, and this moment, charging current began to reduce, and the VREF rate of voltage rise reduces;

C: when VREF＜＜2V _THPDuring-VREF0, the PMOS pipe is in dark linear zone, and charging current is

$I={\mathrm{\&mu;}}_P{C}_{\mathrm{OX}}\frac{W}{L}(\mathrm{VREF}0-V_{\mathrm{THP}})(\mathrm{VREF}0-\mathrm{VREF})$

Electric current is along with the rising of VREF reduces rapidly, and VREF slowly rises up to VREF=VREF0.

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