CN1901230A - Thin film transistor, method for manufacturing thin-film transistor, and display using thin-film transistor - Google Patents

Abstract

The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin film with a crystal grown in a horizontal direction, the thin-film transistor having a gate insulating film and a gate electrode over the channel region, wherein a drain edge of the drain region which is adjacent to the channel region is formed in the vicinity of a crystal growth end position.

Description

Thin-film transistor and manufacture method thereof and the display that uses thin-film transistor

Technical field

The present invention relates to n-or p-channel-type thin-film transistor structure, be used to make the method for n-or p-type thin-film transistor and the display that uses this thin-film transistor.

Background technology

Amorphous silicon membrane and polysilicon membrane have been used as semiconductive thin film, and this film is used to form the thin-film transistor that for example is used as the thin-film transistor (TFT) of the switch element of controlling the voltage that is applied to the pixel in the LCD (LCD) or is used for the control circuit of LCD.

In using the TFT of polysilicon membrane as semiconductive thin film, migration is passed the mobility in the electronics of channel region or hole usually above using amorphous silicon membrane as the mobility among the TFT of semiconductive thin film.Therefore, compare, use the transistor of polysilicon membrane to have higher switching speed, therefore can operate faster with the transistor that uses amorphous silicon membrane.

This makes the TFT that will be used to form LCD pixel selection circuit and peripheral drive circuit can be formed on the identical substrate, on this substrate, forms the pixel control TFT; Peripheral drive circuit drives LCD.In addition, can advantageously increase the design margin of other parts.By merging in the display part that comprises the pixel control TFT, can also realize the definition that reduces and improve of cost and size such as peripheral drive circuits such as drive circuit or DAC.

The applicant has developed the stable mass production techniques of making the crystal region of big crystallite dimension of non-single crystal semiconductor film that is used for being formed on the dielectric substrate.Method as the crystal region that is used to form big crystallite dimension, for example at Masakiyo MATSUMURA, SurfaceScience, Vol.21, No.5, pp.278 to 287, in " Method for FormingGiant Crystal Grain Si Film Using Excimer Laser " in 2000 and MasakiyoMATSUMURA, Applied Physics, Vol.71, No.5, pp.543 to 547 has proposed this method for crystallising in " Method for Forming Giant Crystal Grain Si Film UsingExcimer Laser Light Irradiation " in 2000.The successful production in enormous quantities of the crystal region of big crystallite dimension not only makes the LCD part and is used for the switching transistor of pixel, also makes such as memory circuits such as DRAM or SRAM, computing and logical circuit etc. to be formed on the glass substrate.This make whole LCD desired power amount with and size reduce.

People such as present inventor have developed the manufacturing technology that is used to form more high performance TFT, and this TFT provides practical and optimized transistor characteristic.For example, surface and the silicon single crystal wafer that forms of cutting into slices by the monocrystal rod that the method for peeling off (lift-off method) by routine is formed surperficial different that have the monocrystalline silicon of the crystal by on amorphous silicon membrane, carrying out the big crystallite dimension that heat treatment grows.Especially, at microscopically, preceding a kind of monocrystalline silicon has uneven film, and it has the complicated crystal boundary that produces during crystal growth.

Therefore, have been found that only forming TFT by the arbitrary portion place in crystal region can not obtain desirable cutoff current characteristic.Also find to obtain desirable mobility transistor.

The present invention is intended to solve the problem that transistor characteristic is degenerated, the TFT structure that presents optimized cut-off current and mobility characteristics to be provided, to be used to the display making the method for this TFT and use this TFT.

Summary of the invention

The purpose of this invention is to provide a kind of thin-film transistor structure that presents optimized transistor characteristic, be used to the display making the method for this thin-film transistor and use this thin-film transistor.

Thin-film transistor described in the embodiment of the invention is a n-channel-type thin-film transistor, this thin-film transistor has source area in semiconductive thin film, channel region and drain region, this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, this thin-film transistor has gate insulating film and the gate electrode that is positioned at channel region top, and this thin-film transistor is characterised in that: the channel region lateral edges of drain electrode or source area is arranged in the crystal region in distance crystal growth original position or the about 1.0 μ m of vertical-growth original position or away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m.

Thin-film transistor described in the embodiment of the invention is a n-channel-type thin-film transistor, this thin-film transistor has source area in semiconductive thin film, channel region and drain region, this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, and this crystal region has the inclined surface that raises on crystal growth direction, this thin-film transistor has gate insulating film and the gate electrode that is positioned at channel region top, and this thin-film transistor is characterised in that: the channel region lateral edges of drain electrode or source area is arranged in the crystal region in the about 1.0 μ m of distance crystal growth original position or away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m.

Thin-film transistor described in the embodiment of the invention is a p-channel-type thin-film transistor, this thin-film transistor has source area, channel region and drain region in semiconductive thin film, this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, this thin-film transistor has gate insulating film and the gate electrode that is positioned at the channel region top, and this thin-film transistor is characterised in that: the channel region lateral edges of drain electrode or source area is arranged in the crystal region away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m.

Thin-film transistor described in the embodiment of the invention is a p-channel-type thin-film transistor, this thin-film transistor has source area in semiconductive thin film, channel region and drain region, this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, and this crystal region has the inclined surface that raises on crystal growth direction, this thin-film transistor has gate insulating film and the gate electrode that is positioned at the channel region top, and this thin-film transistor is characterised in that: the channel region lateral edges of drain electrode or source area is arranged in the crystal region away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m.

The method that is used to make thin-film transistor according to the embodiment of the invention is the method that is used to make n-channel-type thin-film transistor, the method is characterized in that to comprise: use laser emission non-single crystal semiconductor film with reverse peak shape light intensity distributions so that by the regional crystallization of radiation to form the step of crystal region; And the lateral edges of drain electrode by will be adjacent with channel region or source area is arranged in the crystal region in distance crystal growth original position or the about 1.0 μ m of vertical-growth original position or form the step of thin-film transistor away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m.

The method that is used to make thin-film transistor according to the embodiment of the invention is the method that is used to make p-channel-type thin-film transistor, the method is characterized in that to comprise: use laser emission non-single crystal semiconductor film with reverse peak shape light intensity distributions so that by the regional crystallization of radiation to form the step of crystal region; And the lateral edges of drain electrode by will be adjacent with channel region or source area is arranged in the crystal region step that forms thin-film transistor away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m.

Display described in the embodiment of the invention has the above-mentioned thin-film transistor that is arranged in the peripheral circuit part, and this peripheral circuit portion branch comprises signal and scan line drive circuit and need operate under high speed.

The invention provides the n-channel-type TFT that presents the optimization cutoff current characteristic, be used to the display making the method for n-channel-type TFT and use this n-channel-type TFT.The present invention also provides the p-channel-type TFT that presents optimized hole mobility, be used to the display making the method for p-channel-type TFT and use this p-channel-type TFT.

The accompanying drawing summary

Fig. 1 is the cut-away section view that illustrates according to the structure of n-of the present invention or p-channel-type thin-film transistor;

Fig. 2 is the process chart that the technology of making TFT shown in Figure 1 is shown according to sequence of steps;

Fig. 3 illustrates the mobility characteristics in the n-channel-type thin-film transistor shown in Figure 1 and the performance plot of the relation between cutoff current characteristic and the drain edge position;

Fig. 4 illustrates the mobility characteristics in the p-channel-type thin-film transistor shown in Figure 1 and the performance plot of the relation between the drain edge position;

Fig. 5 is the figure of structure that the crystallizer of crystallization processes shown in Figure 2 is shown;

Fig. 6 is the figure that lamp optical system shown in Figure 5 is shown in further detail;

Fig. 7 illustrates wherein to carry out the substrat structure of crystallization by crystallization processes shown in Figure 2 and by the figure of the shape of the semiconductive thin film of crystallization;

Fig. 8 is the sectional view that the example of TFT manufacturing process shown in Figure 2 is shown according to sequence of steps;

Fig. 9 is the sectional view that the reprocessing of TFT manufacturing process shown in Figure 8 is shown according to sequence of steps;

Figure 10 is the cross-section photograph of Fig. 9 (g);

Figure 11 is the photo from top observed Figure 10;

Figure 12 is the characteristic performance plot relatively that a large amount of TFT that obtain by technology shown in Fig. 8 and 9 are shown;

Figure 13 illustrates the circuit diagram that wherein thin-film transistor among Fig. 1 is applied to the example of LCD;

Figure 14 illustrates the mobility in a large amount of p-channel transistors and the figure of the relation between the drain edge position;

Figure 15 is illustrated in the drain current in a plurality of thin-film transistors with the drain edge that is respectively formed at the diverse location place and the figure of the relation between the gate voltage;

Figure 16 is the performance plot that another embodiment of mobility characteristics in the n-channel-type thin-film transistor shown in Figure 1 and the relation between cutoff current characteristic and the drain edge position is shown; And

Figure 17 is the performance plot that characteristic another embodiment relatively of a large amount of TFT that obtain by the technology shown in Fig. 8 and 9 is shown.

Detailed description of the present invention

Embodiments of the invention are described below with reference to the accompanying drawings.Following explanation relates to one embodiment of the present of invention, and it is intended to illustrate General Principle of the present invention.Therefore, this explanation is not will limit the invention to this embodiment part or be restricted to the structure of accompanying drawing shown in concrete.In following detailed description and accompanying drawing, represent similar element with similar reference marker.

The inventor has developed and has applied for about by draining or near source electrode edge and crystal growth end position aimed at the crystal region that is used as to the crystal of crystal along continuous straight runs growth and provided the method for optimized mobility characteristics to make the patent of the technology of p-or n-channel-type TFT.In order in the big crystallite dimension crystal region of crystal along continuous straight runs growth, to form TFT as much as possible, the inventor dedicates oneself to study near the transistor characteristic of the crystal region the crystal growth original position, promptly is used for the cutoff current characteristic and the mobility characteristics of leakage current.As a result, with respect to the position of the drain edge that wherein forms TFT, the inventor has been found that the appropriate area that presents optimized transistor characteristic.

In first embodiment, in the crystal region of crystal along continuous straight runs growth, form n-channel-type TFT.In this case, by form n-channel-type TFT make the drain electrode of TFT or source area the channel region lateral edges be arranged in crystal region not with crystal growth original position or vertical-growth original position near corresponding position, for example, in distance crystal growth original position or the about 1.7 μ m of vertical-growth original position, perhaps, obtain optimized cutoff current characteristic away from about 2.4 to the 4.6 μ m of crystal growth original position or about 4.9 to 5.5 μ m.

In another embodiment, by form n-channel-type TFT make the channel region lateral edges of the drain electrode of TFT or source area be arranged in crystal region not with crystal growth original position or vertical-growth original position near corresponding position, for example, in distance crystal growth original position or the about 1.0 μ m of vertical-growth original position, perhaps, obtain optimized cutoff current characteristic away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m.

In a second embodiment, in the crystal region of crystal along continuous straight runs growth, form p-channel-type TFT.In this case, by form p-channel-type TFT make the drain electrode of TFT or source area the channel region lateral edges be arranged in crystal region away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m, for example, at least away from crystal growth start bit or vertical-growth original position 2.3 μ m, obtain optimized mobility characteristics.

At first, with reference to figure 1, will the thin-film transistor of first and second embodiment according to the present invention be described.First and second embodiment relate to different channel type, n and p, but have identical structure.Fig. 1 is the sectional view that the amplification in the zone that wherein forms these thin-film transistors is shown.First and second embodiment have following denominator.

In the light radiation district of non-single crystal semiconductor layer, form crystal region (5 by the crystal growth on the horizontal direction; (7-S-C-D-8)).Crystal region 5 is formed so that crystal growth is carried out from crystal growth original position 7 beginning along continuous straight runs, and at crystal growth end position 8 places, crystal is elevated to maximum.Make and use up non-single crystal semiconductor layer, for example amorphous silicon film 4 (referring to Fig. 7) carries out radiation so that the crystal along continuous straight runs is grown, to form the crystal region 5 of crystallization.Crystal region 5 for example be wherein crystal from the silicon fiml of crystal growth original position 7 beginning in crystal growth direction 13 growths.Crystal region 5 has the surface of inclination, and it has the thickness that increases towards crystal growth end position 8.In this crystal region 5, the electronics in the channel region or the mobility in hole (μ max) increase on the crystal growth direction 13 of TFT and significantly increase near crystal growth end position 8.

A large amount of fine grain distributes in crystal growth original position 7 vicinity.Therefore the inventor has been found that the drain edge of not expecting by with TFT forms TFT with near the aligning of crystal growth original position 7.In other words, by its drain edge is formed TFT with near the aligning of crystal growth original position 7, meeting is the mobility of degenerated transistors undesirably

Consider above-mentioned characteristic, make TFT according to the embodiment of the invention.Especially, the crystal region above utilizing is arranged in TFT and is formed on crystal region away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m.Have been found that this structure can make electronics or hole mobility (μ max) be maximized in above-mentioned position.

In the light radiation district of non-single crystal semiconductor layer, the crystal growth by in the horizontal direction forms crystal region 5; In crystal region 5, crystal is from crystal growth original position 7 beginnings growth in the horizontal direction.Crystal region 5 is the semiconductive thin films with inclined surface 14, and this inclined surface raises towards crystal growth end position 8.In other words, crystal region 5 is the semiconductive thin films with inclined surface, and thickness begins dull in the horizontal direction increasing from the crystal growth original position.

Though agnogenio, laser has remarkable influence at 8 places, edge of the raised area, collide with the terminal of the crystal region 5 of growing from the left side of Fig. 1 in this terminal from the crystal region 5 of the right side growth of Fig. 1.This is in this region generating high membrane stress and wearing and tearing.Estimate that this can make the performance degradation such as mobility.Make the drain electrode or the channel region lateral edges of source area be arranged in crystal region not with crystal growth original position 7 corresponding positions.On the other hand, the channel region lateral edges of drain electrode or source area is positioned near the summit of the dull inclined surface that increases of thickness.For example, non-single crystal semiconductor film is polycrystalline film or the amorphous film such as Si.

Now, with reference to figure 1, will the example of the concrete structure of the n-that drives LCD or p-channel-type TFT be described.TFT 1 among Fig. 1 has the top gate type thin film transistor structure.Substrate 2 can be insulator substrates or have semiconductor or the metal substrate that is formed on its lip-deep dielectric film.On the dielectric substrate of for example glass substrate 2 dielectric film is set, for example silicon oxide film 3.For example, silicon oxide film 3 is for cvd film or thermal oxide film and have for example thickness of 1 μ m.On silicon oxide film 3, non-single crystal semiconductor film is set, for example, amorphous silicon film 4.Amorphous silicon film 4 has 30 to 300nm thickness, more specifically, and 200nm for example.For example come the deposited amorphous silicon fiml by plasma CVD.

In whole amorphous silicon film 4 or its presumptive area, form crystal region 5.Fig. 1 illustrates two crystal regions 5.Crystal region 5 has the light intensity distributions of the reverse peak pattern that is similar to shown in the L among Fig. 7 (b).Have the light beam of the energy of enough melt amorphous silicon films 4 by utilization, for example the radiation of KrF excimer laser makes crystal region 5 crystallizations.

In by the crystal region 5 that has as the laser institute crystallization of a plurality of light intensity distributions of reverse peak pattern, carry out crystal growth, and film thickness increases continuously from crystal growth original position 7 beginning along continuous straight runs.Near crystal growth end position 8, crystal region 5 have with by the corresponding shape of cross section of the monocrystalline silicon membrane of crystallization and rise.

In by the crystal region 5 that has as the laser institute crystallization of a plurality of light intensity distributions of reverse peak pattern, crystal is at adjacent forward peak part P, i.e. the crystal growth end position 8 of crystallization, and (referring to Fig. 7 (b)) each other collides.This has produced and the corresponding angle section of the silicon fiml shape that rises.In this manual, its precalculated position is defined as semiconductive thin film 4a by the semiconductive thin film of crystallization.The pulse duration of the light intensity distributions by the reverse peak shape among Fig. 7 (b) is determined the length between crystal growth original position 7 and the crystal growth end position 8.

In this embodiment, by the drain electrode of the channel region C of TFT 1 or source electrode edge are placed in the crystal region 5 not with crystal growth original position 7 or vertical-growth original position near corresponding position, form TFT 1.

For example, be placed in the crystal region in distance crystal growth original position 0.7 μ m or by drain edge 10 (side 10) away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m with the channel region C of TFT 1, for example in the about 2.3 μ m of distance crystal growth original position, form n-channel-type TFT according to first embodiment.Form channel region C and make it adjacent, and make source area S adjacent with channel region C with drain region D.

In another embodiment, be placed in the crystalline region in distance crystal growth original position 1.0 μ m or by drain edge 10 (side 10) away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m with the channel region C of TFT1, for example in the about 2.3 μ m of distance crystal growth original position, form n-channel-type TFT according to first embodiment.Form channel region C and make it adjacent, and make source area S adjacent with channel region C with drain region D.

For example, be placed in the crystal region away from crystal growth original position 7 at least 2.3 μ m, form p-channel-type TFT according to second embodiment by drain edge 10 (side 10) with the channel region C of TFT 1.Form channel region C and make it adjacent, and make source area S adjacent with channel region C with drain region D.

To be arranged on the channel region C such as gate insulating films such as silicon oxide film 11, so that aim at it.Silicon oxide film can be by based at 300 to 400 ℃, for example the direct oxidation low temperature process of the microwave heating CVD under 350 ℃ and the oxide-film that forms.

Gate electrode 12 is arranged on the gate insulating film 11, so that it is aimed at channel region C.Make TFT 1 thus.In this manual, TFT has the element of TFT structure and not only can also be used for memory, capacitor or resistor as transistor.

Now, with reference to the artwork of figure 2, the example of the method that is used to make n-or p-channel TFT 1 is described.Represent by identical reference marker with those element components identical among Fig. 1.Omitting it describes in detail to avoid repetition.

At first, make crystalline substrate.For example, be sent to plasma CVD apparatus with quartz substrate or by the glass substrate 2 that non-alkali glass is formed.Glass substrate 2 placed and is installed on the pre-position (step-1) in the plasma CVD apparatus.Subsequently, by plasma CVD in gas phase, grow lower floor's dielectric film, for example silicon oxide film 3 (step-2).For example, can under the sedimentation time of 500 ℃ underlayer temperature and 40 minutes, carry out plasma CVD.

Then, growing in gas phase by plasma CVD will be by the non-single crystal semiconductor film of being made up of amorphous silicon or polysilicon (step-3) of crystallization; Non-single crystal semiconductor film is that film thickness is the amorphous silicon film 4 of 30 to 300nm (for example about 200nm).For example by LP-CVD (low pressure chemical vapor deposition) deposited amorphous silicon fiml 4 on silicon oxide film 3.Amorphous silicon film 4 (a-Si) has for example thickness of 200nm.For example under the condition of the sedimentation time of the pressure that comprises the flow velocity of 150sccm, 8Pa, 450 ℃ underlayer temperature and 35 minutes, at Si ₂H ₆Carry out LP-CVD technology under the atmosphere.In this case, use LP-CVD technology, PE-CVD (low temperature plasma CVD) technology replaces but for example also can use.

Non-single crystal semiconductor film is not limited to amorphous silicon film 4 (Si).For example, can use such as films such as Ge or SiGe.In addition, the deposition of non-single crystal semiconductor film is not limited to CVD technology.For example, can use sputtering equipment to carry out deposition.

Then, in order to form the crystal region of big crystallite dimension, by plasma CVD, on amorphous silicon film 4 the deposition thickness be 10 to 100nm (for example 10nm) can the transmission incident light coverlay, silicon oxide film for example.For example by LP-CVD technology, under the sedimentation time of 500 ℃ underlayer temperatures and 10 minutes, cvd silicon oxide film on amorphous silicon film 4.Coverlay is made up of dielectric film and is brought into play hot memory action.In step subsequently, when using laser to carry out crystallization, coverlay has reduced the changing down of the temperature of non-single crystal semiconductor film 2.Make the coverlay (step-4) of crystallization thus.

Carry out crystallisation step 5 and 6 then.Crystalline substrate 2 is arranged in and is installed in the pre-position of crystallizer.The pulse type excimer laser that use has a light intensity distributions of the reverse peak pattern shown in Fig. 7 (b) comes radiation to be sent to crystallization position in the crystalline substrate of crystallizer.Heating is by the zone of radiation and make its fusing (step-5).

This Temperature Distribution is stored in the coverlay 35 heat.Stop that excimer laser is with according to reducing the temperature of the semiconductor film that is melted with the corresponding temperature gradient of the light intensity distributions shown in Fig. 9 (b).Utilize this temperature lifting technique, because the hot memory action of coverlay, temperature slowly reduces.Therefore, crystal growth is taken place in proper order with interrelating,, wherein form the crystal (step-6) of big crystallite dimension to form crystal region 5 with temperature gradient.Excimer laser for example can be that KrF excimer laser and its can have for example 350mJ/cm ²Energy density.The positional information of crystallization is pre-stored in the computer (not shown).The automatically mobile in order substrate of computer also places it in crystallization position place in the crystalline substrate, and the laser emission substrate that is used for crystallization then is to finish crystallisation step 5 and 6.

Crystallisation step 5 and 6 uses the phase modulated excimer laser crystallisation that describes in detail later.In this case, use the surface of excimer laser radiation coverlay with reverse peak shape light intensity distributions R (seeing Fig. 7 (b)).Pulsed laser radiation makes by this zone melting of the amorphous silicon film 4 of laser emission.The temperature of fusion zone reduces, simultaneously blocking laser.Solidify the position and move in the horizontal direction producing continuous crystalline growth, thereby form crystal region 5.

In crystal region 5, crystal growth is carried out from crystal growth original position shown in Figure 17 beginning along continuous straight runs.Distance from crystal growth original position 7 to crystal growth end position 8 is 5.0 μ m the n-channel-type according to first embodiment.This distance is 5.0 μ m in the example according to the p-channel-type of second embodiment.Crystal growth is converted into amorphous silicon film 4 the semiconductive thin film 4a of part or all of crystallization.Can carry out the one or many pulsed laser radiation.Perhaps, can with pulsed laser radiation and the radiation that utilizes another kind of light source for example the light of photoflash lamp combine.

Therefore, usually the crystal region 5 that forms is carried out shaping, advance, and crystal is in 8 risings of crystal growth end position, as shown in Figure 1 so that crystal growth begins along continuous straight runs from crystal growth original position 7.

Then, in order in the crystal region of big crystallite dimension, to form TFT 1, remove silicon oxide film (step-7) from the coverlay that is deposited.Can remove silicon oxide film by dry method etch technology.For example, can use BCl ₃Or CH ₄Etching gas as dry method etch technology.

Then, finished thereon and carried out the TFT manufacturing process on the glass substrate 2 of crystallization processes.For example, be placed in the crystal region in distance crystal growth original position 7 or vertical-growth original position 0.7 μ m or by channel region lateral edges, make n-channel-type TFT according to first embodiment away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m with the drain electrode of TFT or source area.

In another embodiment, be placed in the crystal region in distance crystal growth original position 7 or vertical-growth original position 1.0 μ m or by channel region lateral edges, make n-channel-type TFT according to first embodiment away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m with the drain electrode of TFT or source area.

Be placed in the crystal region away from crystal growth original position or vertical-growth original position 2.3 μ m by channel region lateral edges, make p-channel-type TFT according to second embodiment with the drain electrode of TFT or source area.

In this manual, crystal growth original position or vertical-growth original position are the positions that crystal growth begins in the single-crystal region of crystallization, as shown in Fig. 7 (c).In crystal growth original position 7, meticulous crystallographic grain accumulates in the crystal growth start-up portion.Crystal growth original position 7 be not with the corresponding crystal growth original position of fine crystals crystal grain part.The channel region lateral edges of the drain electrode of TFT or source area is drain region or the drain electrode at the boundary position place between the source area or the edge of source electrode that contacts at channel region with channel region.

Then, the glass substrate 2 that will have a semiconductive thin film of crystallization be sent in the plasma CVD apparatus (not shown) the precalculated position and with its placement be installed in this position.Plasma CVD apparatus is deposited on silicon oxide film on the surface of the crystalline semiconductor film that exposes by plasma CVD from the glass substrate 1 that is transmitted, so that form gate insulating film 11, and shown in Fig. 8 (a) (step-8).

Then, the glass substrate 2 that has formed gate insulating film 11 on it is sent to sputtering equipment and is positioned at wherein, this sputtering equipment deposition forms the electrically conductive film 40 of gate electrode, shown in Fig. 8 (b).For example, deposition of aluminum (Al) 40 is as gate electrode (step-9).Then substrate is sent to plasma etching equipment, in this equipment, utilizes the mask that constitutes by resist film 41 that it is carried out plasma etching, to form gate electrode 12 (step-9).

The gate electrode 12 that will form in above-mentioned steps subsequently is as mask, so that the high concentration impurities ion is injected in the crystal region, so that form source electrode and drain region.Foreign ion for example is phosphonium ion that is used for the n-channel transistor and the boron ion that is used for the p-channel transistor.In blanket of nitrogen, carry out annealing process (for example, carrying out 1 hour) subsequently, with activated impurity at 600 ℃.In crystal region, form source area S and drain region D thus, as shown in fig. 1.This produces channel region C between source area S and drain region D, make carrier mobility (step-10) in this channel region.

On gate insulation layer 11 and gate electrode 12, form the interlayer insulating film (not shown) then.In interlayer insulating film, form the contact hole (not shown) so that source and drain electrode are connected to source area S and drain region D.

Then, will constitute the metal level of gate electrode, source and drain electrode, aluminium for example is filled in the contact hole and is deposited on the interlayer insulating film (not shown).The metal level that uses photoetching technique will be deposited on the interlayer insulating film is etched into predetermined pattern.This formation source and drain electrode are to make n-or p-channel-type thin-film transistor (step-11).In first and second embodiment, TFT 1 has for example grid length of 1 μ m.

In above-mentioned manufacturing process, source area S by will be adjacent or the lateral edges of drain region D with channel region C be placed in the crystal region not with crystal growth original position 7 corresponding positions, form TFT.In other words, come the oriented side edge by gate electrode 12 as the ion injecting mask.Thus gate electrode 12 is placed and is installed on the crystal region not with crystal growth original position 7 near corresponding positions.

With reference to figure 3 and 4, with the measurement of explanation to the transistor characteristic of the n-that makes thus or p-channel-type TFT.

Fig. 3 and Figure 16 are illustrated in the cut-off current [A] (leakage current) in the n-channel TFT 1 that forms in the crystal region 5 of crystallization as mentioned above and the performance diagram of the relation between the drain edge position.Fig. 3 illustrates when source-drain electrode voltage Vds=0.1V and Dang Yuan-cutoff current characteristic that shown during gate electrode voltage Vgs=-5V.

Fig. 4 is the mobility [mu] FE[cm that is illustrated in the p-channel TFT 1 that forms in the crystal region 5 of crystallization as mentioned above ²/ Vs] and the drain edge position between the performance diagram of relation.Fig. 3 illustrates when source-drain electrode voltage Vds=0.1V and Dang Yuan-mobility characteristics that shown during gate electrode voltage Vgs=-5V.Crystal region depends on the pulse duration of reverse peak shape light intensity distributions.For example, determined to make the technology that the crystal region of 5 μ m sizes is produced in batches.

Observation to cutoff current characteristic is as follows:

So that forming (in crystal region), drain edge in distance crystal growth original position 70.7 μ m or away from the TFT 1 of the mode manufacturing of about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m, presents bigger cut-off current, it is unsuitable cutoff current characteristic (less cut-off current, promptly, suitable cutoff current characteristic), referring to Fig. 3.

In another embodiment, so that forming (in crystal region), drain edge in distance crystal growth original position 71.0 μ m or away from the TFT 1 of the mode manufacturing of about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m, presents less cut-off current, be suitable cutoff current characteristic, referring to Figure 16.

So that forming (in crystal region), drain edge in distance crystal growth original position 70.5 μ m or away from the n-channel-type TFT 1 of the mode manufacturing of about 1.5 to the 1.8 μ m of crystal growth original position or about 3.0 to 3.7 μ m, presents less cut-off current, it is suitable cutoff current characteristic (bigger cut-off current, promptly, unsuitable cutoff current characteristic), referring to Fig. 3.

In another embodiment, so that the n-channel-type TFT1 that drain edge forms away from the mode manufacturing of crystal growth original position 7 about 1.0 to 2.0 μ m or about 3.7 to 4.6 μ m presents bigger cut-off current, be unsuitable cutoff current characteristic, referring to Figure 16.

Observation to mobility characteristics is as follows:

As shown in Figure 4, so that the n-channel-type TFT 1 that drain edge is formed in the crystal region away from the mode manufacturing of crystal growth original position or about 0.7 to the 2.6 μ m of vertical-growth original position or about 3.1 to 4.5 μ m presents suitable mobility characteristics.

On the other hand, so that drain edge be formed on apart from presenting the mobility that reduces in the crystal growth original position 70.7 μ m or away from the p-channel-type TFT 1 of the mode manufacturing of crystal growth original position 7 about 2.2 to 3.1 μ m or about 4.7 to 5.0 μ m; These TFT are difficult to utilize.

In another embodiment, so that drain edge is formed on apart from presenting the mobility that reduces in the crystal growth original position 70.7 μ m or away from the p-channel-type TFT 1 of the mode manufacturing of crystal growth original position 7 about 2.7 to 3.1 μ m or about 4.5 to 5.0 μ m, these TFT are difficult to utilize.

With reference now to Fig. 5 to 7,, crystallizer is specifically described, this crystallizer forms shape like this makes crystal growth advance in the horizontal direction from crystal growth original position 7 beginnings that have a large amount of fine crystals crystal grain, and crystal raises towards crystal growth end position 8.

As shown in Figure 5, crystallizer 20 comprises illuminator 15, is arranged on phase modulation component 16 on the optical axis of illuminator 15, is arranged on image on the optical axis of phase modulation component 16 and forms optical system 17 and support the stand 19 that is arranged on the crystalline substrate 18 on the optical axis that image forms optical system 17.

Illuminator 15 is optical systems shown in Figure 6, and for example is made up of light source 21 and homogenizer 22.Light source 21 can be a KrF excimer laser light source 21, and it provides wavelength for example to be the light of 248nm.Perhaps, light source 21 can be that emission wavelength is the KrF excimer laser of the XeCl excimer laser light source of the pulsed light of 308nm, pulsed light that emission wavelength is 248nm or the ArF excimer laser of the pulsed light that emission wavelength is 193nm.Perhaps, light source 21 can be the YAG LASER Light Source.Perhaps, light source 21 can be the another kind of suitably light source that the output energy is enough to melt non-single crystal semiconductor film, for example amorphous silicon film 4.Homogenizer 22 is arranged on the optical axis by light source 21 emitted laser.

Homogenizer 22 makes by the luminous intensity of light source 21 emitted laser and to incidence angle homogenizing in the cross section of luminous flux of the light of phase modulation component 16.Homogenizer 22 for example has optical beam expander 23, first compound eye (fly eye) lens 24, the first condenser optics system 25, second fly's-eye lens 26 and the second condenser optics system 27, and above-mentioned all elements are arranged on the optical axis from the laser of light source.

In illuminator 15, by light source 21 emission laser.Then, laser is exaggerated and incides then on first fly's-eye lens 24 via optical beam expander 23.On the back focal plane of first fly's-eye lens 24, form a plurality of light sources.Shine the incidence surface of second fly's-eye lens 26 with overlap mode from the luminous flux of a plurality of light sources.As a result, on the back focal plane of second fly's-eye lens 26, formed than more light sources on the back focal plane of first fly's-eye lens 24.In the future the idiomorphism luminous flux that is formed in a large amount of light sources on the back focal plane of second fly's-eye lens 26 incides phase modulation component 16 via the second condenser optics system 27.Luminous flux is with overlap mode irradiation phase modulation component 16 thus.

As a result, first fly's-eye lens 24 in the homogenizer 22 and the first condenser optics system 25 constitute first homogenizer, and its homogenizing is incident on the incidence angle of the laser on the phase modulation component 16.Second fly's-eye lens 26 and the second condenser optics system 27 constitute second homogenizer, and it is in each position homogenizing on the surface of phase modulation component 16 luminous intensity from the laser of first homogenizer, and the incidence angle of light is by homogenizing.Illuminator 22 forms thus has almost the laser of light intensity distributions uniformly.Use this laser emission phase modulation component 16.

Phase modulation component 16, that is, phase shifter is an optical element of modulating the phase place of the light of being launched by homogenizer 22.Phase modulation component 16 is launched the laser beam of the reverse peak shape minimum light intensity distribution that has shown in Fig. 7 (b) then, and Fig. 7 (b) is the part zoomed-in view that reverse peak shape minimum light intensity distributes.In this accompanying drawing, axis of abscissas is represented position (position on the radiating surface), and axis of ordinates is represented luminous intensity (energy).

Phase shifter 16 as phase modulation component can form by make step in transparent elements such as for example quartz substrate material.Phase shifter 16 makes the boundary diffraction of laser beam between step so that they are interfered mutually, and spatial distribution is applied on the laser intensity thereby incite somebody to action periodically.Phase shifter is not limited to this example.For example, form light transmission region, this zone with the horizontal phase difference that has 180 ° around the corresponding border of step part x=0.Usually, when Wavelength of Laser is defined as λ and forms refractive index on the transparent substrates material when being the transparent medium of n, for the needed film thickness difference t between transparent medium and transparent substrates material of phase difference that obtains 180 ° is provided by t=λ/2 (n-1).When the quartz substrate material has 1.46 refractive index, because the XeCl excimer laser has the wavelength of 308nm, so need the step of 334.8nm size to realize 180 ° phase difference.For example, can form this step by selective etch.

Perhaps, can form step part by using the SiNx film it to be deposited as transparent medium and by PECVD, LPCVD etc.In this case, when this SiNx film has 2.0 refractive index, it can be deposited into the thickness of 154nm on the quartz substrate material and then it be etched with the formation step.The laser intensity that has passed the phase shifter with 180 ° of phase differences demonstrates periodically variable pattern, shown in Fig. 7 (b).

In the present embodiment, periodically phase shifter is by repeating and periodically form the mask that step obtains.In the present embodiment, the width of phase-shift pattern and the distance between the pattern for example all are 3 μ m.It must be 180 ° that phase difference does not need, but only must obtain to be suitable for making the laser intensity of semiconductor thin film crystallization to distribute.

As shown in Figure 5, the laser modulated by phase modulation component 16 of phase place forms optical system 17 via image and incides on the crystalline substrate 18 such as amorphous silicon film.So place image and form optical system 17 so that make the patterned surfaces and crystalline substrate 18 optical conjugates of phase modulation component 16.In other words, proofread and correct the height and position of stand 19 so that crystalline substrate 18 is arranged on the surface with the patterned surfaces optical conjugate of phase modulation component 16 (image forms the imaging surface of optical system 17).

Image formation optical system 17 is included in the aperture diaphragm 33 between positive lens groups 31 and the positive lens groups 32.It can be optical lens that image forms optical system 17, and it will be from the image projection of phase modulation component 16 on crystalline substrate 18, and does not change its ratio, or it for example is reduced to 1/5th with ratio.

Aperture diaphragm 33 shown in Figure 5 has a plurality of aperture diaphragms that comprise the aperture part (light transmission part) with different size.These aperture diaphragms 33 can mutual alternative about optical path.Perhaps, each in a plurality of aperture diaphragms 33 can have the iris stop (iris stop) of the size that can continuously change the aperture part.Under any circumstance, the aperture size in the aperture diaphragm 33 (perhaps image forms the numerical aperture NA of the image-side of optical system 4) is so set so that produce the light intensity distributions that needs on the semiconductor film on the crystalline substrate 18.It can be refraction or reflective optics or double reflection and refraction optical system that image forms optical system.

Shown in Fig. 7 (a), crystalline substrate 18 is made of silicon oxide film 3, amorphous silicon film 4 and the coverlay 35 as lower floor's dielectric film, and order on the glass substrate 2 that for example is used for LCD forms these films by chemical vapor deposition method (CVD technology) or sputtering technology.

Lower floor's dielectric film is for example by SiO ₂Form, and have 500 to 1000nm film thickness.Lower floor's dielectric film 3 prevents that amorphous silicon film 4 from directly contacting with glass substrate 2 in order to avoid will being mixed into the amorphous silicon film 4 such as impurity such as Na from glass substrate 2 depositions.Lower floor's dielectric film 3 also prevents from during amorphous silicon film 4 crystallizations melting caloric directly to be transferred to glass substrate 2.Lower floor's dielectric film 3 is stored heat of fusion effectively and is reduced fast to avoid temperature, helps to form the crystal of big crystallite dimension thus.

Amorphous silicon film 4 will be by crystallization with the source electrode, drain electrode and the raceway groove that form TFT and have for example 30 to 250nm film thickness.The heat that coverlay 35 produces when being stored in amorphous silicon film 4 fusings during the crystallization processes.This hot storage effect helps to form the crystal region of big crystallite dimension.Coverlay 35 is dielectric films, for example silicon oxide film (SiO ₂), and can have 100, for example the thickness of 300nm to 400nm.

Crystalline substrate 18 is sent on the stand 19 of crystallizer as shown in Figure 5 automatically.Then crystalline substrate 18 is placed on the precalculated position and by vacuum or electrostatic chuck clamping.

Now, with reference to Fig. 6 and 7 explanation crystallization processes.Pulse laser by LASER Light Source shown in Figure 6 21 emission incides on the homogenizer 22, the intensity of these homogenizer 22 homogenizing laser and to the incidence angle of the light of phase modulation component 16.In other words, homogenizer 22 will be propagated to obtain linear beam (it has for example lineal measure of 200mm) in the horizontal direction from the laser beam of light source 21.Homogenizer 22 also carries out homogenizing to light intensity distributions.For example, the cylindrical lens of a plurality of directions Xs is arranged on the Y direction to form the luminous flux on a plurality of Y of being arranged on directions, uses the cylindrical lens redistribution luminous flux of other directions X.Similarly, the cylindrical lens of a plurality of Y directions is arranged on the directions X to form a plurality of luminous fluxes that are arranged on the directions X, uses the cylindrical lens redistribution luminous flux of other Y direction.

Laser can for example be the XeCl excimer laser with 308nm wavelength.Single duration of triggering (one shot) pulse for example is 20 to 200ns.Under these conditions, use pulsed laser radiation phase modulation component 16.The pulse laser beam that enters the phase modulation component 16 that periodically forms is diffracted so that interfere with each other at step part.Phase modulation component 16 produces the periodically variable light intensity distributions of the reverse peak pattern shown in Fig. 7 (b) thus.

In reverse peak pattern-like light intensity distributions, between minimum light intensity partial L and maximum light intensity part P, desired output is enough to the laser intensity of melt amorphous silicon film 4.The pulse laser that passes phase modulation component 16 is incided on the amorphous silicon film 4, form optical system 17 by image simultaneously it is focused on the surface of crystalline substrate 18.

Incident pulse laser almost transmission is crossed coverlay 35 and is absorbed by amorphous silicon film 4.As a result, amorphous silicon film 4 is heated by radiation areas and melts.The fusing heat is stored in existence by coverlay 35 and silicon oxide film 3.

When stopping the radiation of using pulse laser, be tending towards to reduce at a high speed by the temperature of radiation areas.In this case, the heat that is stored in coverlay 35 and the silicon oxide film 3 is used so that temperature reduces very lentamente.Reduced by the light intensity distributions of the temperature of radiation area according to the reverse peak pattern-like that produces by phase modulation component 16.This makes the crystal growth along continuous straight runs carry out continuously to maximum light intensity part P from the minimum light intensity partial L.

In other words, moved to high temperature side from low temperature side continuously by the position of solidifying in the fusion zone in the radiation area.That is to say that shown in Fig. 7 (c) and 7 (d), crystal growth proceeds to crystal growth end position 8 from crystal growth original position 7.Shown in Fig. 7 (d), crystal raises near by the crystal growth end position 8 in the radiation area a little.Fig. 7 (c) is the plane graph that the shape of the crystal region 5 in the amorphous silicon film 4 that is produced by peeling off of coverlay 35 is shown.Fig. 7 (c) shows crystal growth, and how along continuous straight runs proceeds to crystal growth end position 8 from crystal growth original position 7.

Fig. 7 (d) is the sectional view of Fig. 7 (c).Shown in Fig. 7 (d), the film thickness of semiconductive thin film 4a increases to crystal growth end position 8 from crystal growth original position 7.Crystal has inclined surface, and it has a summit at crystal growth end position 8 places.This section shape represents that crystallization causes having at crystal growth end position 8 angular shape on summit.Fig. 9 (d) part illustrates a plurality of reverse peak shape light intensity distributions shown in Fig. 7 (b).Single reverse peak shape light intensity distributions pattern causes having a pair of dihedral variation and the only film thickness distribution of a pair of raised portion.

Finished the crystallization processes that uses pulse laser thus.The crystal region of process crystal growth is enough greatly to hold one or more function element.Fig. 7 (b), 7 (c) and 7 (d) make the correlation that has been shown in broken lines them.Especially, in Fig. 7 (b), 7 (c) and 7 (d), locate to begin crystal growth in the reverse peak partial L (crystal growth original position 7) of reverse peak shape light intensity distributions.Crystal growth ends at forward peak part P (crystal growth end position 8).The film thickness of monocrystalline silicon increases continuously crystal growth end position 8 from crystal growth original position 7, and crystal raises near end position 8.

Control crystallizer shown in Figure 5 20 according to the program that is pre-stored in the controller (not shown).Particularly, crystallization control equipment 20 like this is so that the crystal region in the next amorphous silicon film 4 of use pulse laser autoemission.In order to move to next crystal region, for example can select by radiation position by mobile stand 19.Certainly, can relative to each other move the selective freezing position by making crystalline substrate 18 and light source 21.

In case selected new crystal region and finished aligning, then launched next pulse laser.Repeat this Laser emission make crystalline substrate 18 in wide scope by crystallization.On entire substrate, carry out crystallization processes thus.The amorphous silicon film that wherein forms crystal region 4 shown in Fig. 7 (d) is called semiconductive thin film 4a.

Now, with reference to figure 8 and 9, the example of the part of the TFT manufacturing process after the step shown in Figure 2-8 is described.Represent by identical reference marker with parts identical among Fig. 1 to 7, and omitted their detailed description.

In above-mentioned steps, deposited SiO on the surface of the substrate of crystallization ₂Film, coverlay 35.SiO ₂Film can also be as the gate insulating film of TFT.Yet, if during crystallization processes, will sneak into SiO from the impurity of amorphous silicon film 4 owing to wearing and tearing wait ₂In the film, then preferably etch away SiO ₂Film.In this example, removed SiO ₂

Shown in Fig. 8 (a), with gate insulating film 11, for example SiO ₂Film is deposited on the semiconductive thin film 4a, and it is positioned on the substrate surface of having removed coverlay 35.Gate insulating film 11 is for example by the silicon oxide film of LP-CVD process deposits on semiconductive thin film 4a.Carry out LP-CVD under the condition below, for example underlayer temperature is 500 ℃, and sedimentation time is 45 minutes.

Form gate electrode 12 then.Especially, as shown in Fig. 8 (b), deposit gate electrode layer on gate insulating film 11, for example aluminium lamination 40.By for example sputtering at the silicon oxide film (SiO of gate insulating film 11 ₂Film) deposits the aluminium lamination 40 that for example 100nm is thick on.Sputtering condition comprises for example 100 ℃ underlayer temperature and 10 minutes sedimentation time.

Optionally etching aluminium lamination 40 is to form gate electrode 12 in the pre-position.In order to realize this purpose, on aluminium lamination 40, form resist pattern 41.By resist film being applied to aluminium lamination 40, utilize the photomask resist film that optionally exposes, remove resist film then and stay the masked area that is used for gate electrode, form resist pattern 41.Form resist pattern 41 thus, as shown in Fig. 8 (c).

The position of resist pattern 41 that is used to form gate electrode 12 is very important.Resist pattern 41 is formed in the crystal region not near the corresponding position with crystal growth original position 7.

For example, resist pattern 41 is patterned into the source-drain electrode edge is formed in the crystal region in distance crystal growth original position 70.7 μ m or away from about 2.0 to the 3.8 μ m of crystal growth original position or about 4.6 to 5.0 μ m, for example away from crystal region 5 about 2.3 μ m.

Use resist pattern 41 to remove aluminium lamination 40 then as mask.For example, carry out dry method etch technology to form gate electrode 12, shown in Fig. 8 (d).Dry method etch technology is for example used BCl ₃Or CH ₄As etching gas.Subsequently, shown in Fig. 9 (e), remove the resist pattern 41 on the gate electrode 12.

Then, as shown in Fig. 9 (f), use gate electrode 12 as mask with doping impurity in semiconductive thin film 4a.If TFT 1 of the present invention is the n-channel-type, then phosphonium ion is injected among the semiconductive thin film 4a as impurity.If TFT 1 of the present invention is the p-channel-type, then the boron ion is injected among the semiconductive thin film 4a.For example, such as logical circuit constituting such as CMOS inverters by n-channel-type TFT and p-channel-type TFT.

That is to say, first and second embodiment are combined.Therefore carry out one of them the ion that is used to form n and p channel-type TFT and inject, and use such as forbidding that masks such as resist that unwanted ion injects cover the semiconductive thin film 4a of other TFT.

After ion being injected into n and p channel-type TFT 1, carry out annealing process to activate the impurity that has been injected among the semiconductive thin film 4a, for example phosphorus or boron.In nitrogen environment, the heat treatment of carrying out 3 hours under 600 ℃ underlayer temperature for example is to carry out annealing process.As a result, shown in Fig. 9 (g), in semiconductive thin film 4a, on the opposite side of gate electrode 12, form source S and drain D district with high concentration impurities.

As a result, forming the source S adjacent with channel region C or the lateral edges 10 in drain D district makes it be positioned at correct position place as shown in Figure 1.

On gate insulating film 11 and gate electrode 12, form the interlayer dielectric (not shown) then.By being formed on the through hole (not shown) in the interlayer dielectric, use known technology to form source electrode, drain electrode and gate electrode (not shown) etc.Can make and form TFT1 in this way.

Figure 10 illustrates the microphotograph of the cross section structure of the TFT 1 that makes as mentioned above.With the lateral edges 10 of drain region D be arranged on crystal growth end position 8 in the crystal region near.Figure 10 illustrates stacking fault S1 and D1 and has appeared in source S among the TFT and the drain D district and its extending to than shallow portion than the deep branch from semiconductive thin film 4a.Figure 10 is clearly shown that also gate electrode 12 tilts.

Figure 11 is the plan view of Figure 10.The lateral edges 10 that Figure 11 illustrates the drain region D adjacent with channel region C be arranged on crystal growth end position 8 near.

The lateral edges 10 that Figure 12 illustrates drain region D in n-channel-type thin-film transistor the position and the relation between the electron mobility μ of n type TFT, wherein this edge is adjacent with channel region C; Expression lateral edges position on axis of abscissas, and on axis of ordinates, represent electron mobility.

Figure 12 and Figure 17 are the drawing of the mobility characteristics of a large amount of n-type TFT.Present these mobility characteristics by the n-type TFT that wherein in distance crystal growth end position 81.5 mu m ranges, forms drain edge (the channel region lateral edges of drain region D).Represent the wherein mobility characteristics of the n-type TFT at formation source electrode edge (the channel region lateral edges of source area S) in the scope of distance crystal growth end position 81.5 μ m with the characteristic that rectangle is drawn.By showing grid voltage (abscissa) performance diagram of drain current (ordinate) is determined mobility characteristics.In the time of in the edge among the TFT is formed on apart from the scope of crystal growth end position 81.5 μ m, no matter this edge belongs to drain region or source area, and the characteristic that it presented much at one.

As shown in Figure 2, the edge 10 of drain region D that wherein will be adjacent with channel region C is formed on apart from the TFT 1 in the crystal growth end position 81.5 μ m and presents 150cm ²The mobility of/v.s.Especially, the edge 10 of drain region D that wherein will be adjacent with channel region C is formed on apart from the TFT 1 in crystal growth end position 80.05 to the 0.2 μ m and presents excellent characteristic, that is, and and 150cm ²The mobility of/v.s.

In Figure 12, wherein form the characteristic of the TFT of channel region away near drawing data (next the crystal region end position 8) expression of crystal growth end position 8 across crystal growth end position 8.N-type TFT presents characteristic shown in Figure 14, but also can obtain above-mentioned characteristic from p-type TFT.In addition, in the TFT 1 of this example, electric current is parallel to the direction of crystal growth, and promptly horizontal direction flows.Is optimum at crystal growth direction by electric current.

Now, with reference to Figure 13, the example that will TFT according to the present invention be applied to the transistor circuit in the display such as LCD for example is described wherein.

Figure 13 illustrates the example of the display part of an active matrix-type liquid crystal display device 50, and this display 50 comprises transparent substrates 52, pixel electrode 53, scan line 54, holding wire 55, counterelectrode 56, TFT 1, scan line drive circuit 57, signal-line driving circuit 58 and liquid-crystal controller 59.

Above-mentioned thin-film transistor constitutes the peripheral circuit part that comprises scan line drive circuit 57 and signal-line driving circuit 58, and it must be operated under high speed.This display can realize comprising the system display of the active element that is used for peripheral circuit part, memory circuit part etc.

Formation according to TFT 1 of the present invention so that its have as with reference to figure 1 described this structure.TFT 1 according to the present invention is applicable to must be with the peripheral circuit part of high speed operation.For example, can be according to TFT 1 of the present invention as the TFT element that constitutes scan line drive circuit 57, signal-line driving circuit 58 etc.The peripheral circuit portion that comprises scan line drive circuit 57 and signal-line driving circuit 58 divides expectation to be made up of TFT, in this TFT, the source electrode edge of source area S or the drain edge of drain region D are formed in the scope apart from crystal growth end position 80.05 to 0.2 μ m.Form this TFT peripheral circuit is made of the TFT with good characteristic, comprise 300cm at least ²The mobility of/v.s (μ max).

The display of Zhi Zaoing can realize comprising the system display of the active element that is used for peripheral circuit part, memory circuit part etc. thus.This display also is effective reducing on size and the weight.

Now, will describe refer to figs. 14 and 15 another example TFT.Figure 14 is illustrated in the mobility characteristics among the p-channel-type TFT and the example of the relation between the drain edge position.Shown in this accompanying drawing, when drain edge was positioned at away from the about 1 μ m of crystal growth original position, mobility began to increase, and when between the 1 and 2.3 μ m of drain edge in distance crystal growth original position, mobility increases continuously.When the length between crystal growth original position 7 and the crystal growth end position 8 is 2.5 μ m, present this characteristic.

Figure 15 illustrates the drain current among the TFT and the performance diagram of the relation between the gate voltage, wherein drain edge be formed on (1) crystal growth original position neighbouring, (2) for the optimal location of mobility or (3) near the crystal growth end position.As shown in figure 15, present optimal properties at optimal location place (2) for mobility.Figure 14 to 15 has near the position the crystal growth original position (1) with for the position (2) and the relation between near the position the crystal growth end position (3) at the optimal location place of mobility.

Thin-film transistor shown in Figure 1 can constitute the thin-film transistor 1 in each circuit and the memory of being made up of thin-film transistor, capacitor, resistor etc. as required.In other words, in this manual, term " thin-film transistor " comprises the element that can be made of thin-film transistor shown in Figure 1, except its function.

The thin-film transistor of Zhi Zaoing can be applied to the drive circuit of LCD or EL (electroluminescence) display or be used for the memory (SRAM or DRAM) of each image element circuit or the integrated circuit of CPU thus.

As mentioned above, the foregoing description provides the TFT with high electronics or hole mobility.The TFT that demonstrates this high mobility can be applicable to comprise the peripheral circuit part of scan line drive circuit 57 and signal-line driving circuit 58.The invention provides the TFT that presents suitable cutoff current characteristic, this TFT is also applicable to the peripheral circuit part that comprises scan line drive circuit 57 and signal-line driving circuit 58.

Several embodiments of the present invention have been illustrated and have described.Described in this manual embodiments of the invention only are exemplary also obviously can changing without departing from the scope of the invention.

Claims (10)

1, a kind of n-channel-type thin-film transistor, it has source area, channel region and drain region in semiconductive thin film, and this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, and this thin-film transistor has gate insulating film and gate electrode on this channel region,

It is characterized in that: will drain or the channel region lateral edges of source area is arranged in this crystal region in distance crystal growth original position or the about 1.0 μ m of vertical-growth original position or away from about 2.0 to the 3.8 μ m of described crystal growth original position or about 4.6 to 5.0 μ m.

2, a kind of n-channel-type thin-film transistor, it has source area, channel region and drain region in semiconductive thin film, this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, and this crystal region has the inclined surface that raises on crystal growth direction, this thin-film transistor has gate insulating film and gate electrode on this channel region

It is characterized in that: will drain or the channel region lateral edges of source area is arranged in this crystal region in the about 1.0 μ m of distance crystal growth original position or away from about 2.0 to the 3.8 μ m of described crystal growth original position or about 4.6 to 5.0 μ m.

3, a kind of p-channel-type thin-film transistor, it has source area, channel region and drain region in semiconductive thin film, and this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, and this thin-film transistor has gate insulating film and gate electrode on this channel region,

It is characterized in that: will drain or the channel region lateral edges of source area is arranged in this crystal region away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m.

4, a kind of p-channel-type thin-film transistor, it has source area, channel region and drain region in semiconductive thin film, this semiconductive thin film has the crystal region of crystal along continuous straight runs growth, and this crystal region has the inclined surface that raises on crystal growth direction, this thin-film transistor has gate insulating film and gate electrode on this channel region

It is characterized in that: will drain or the channel region lateral edges of source area is arranged in this crystal region away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m.

5, a kind of method that is used to make n-channel-type thin-film transistor the method is characterized in that to comprise:

Use has the laser emission non-single crystal semiconductor film of reverse peak shape light intensity distributions so that by the step of the regional crystallization of radiation with the formation crystal region; And

The drain electrode by will be adjacent with channel region or the lateral edges of source area be arranged in this crystal region in distance crystal growth original position or the about 0.5 μ m of vertical-growth original position, in the about 1.0 μ m of the described crystal growth original position of distance or form the step of thin-film transistor away from about 2.0 to the 3.8 μ m of described crystal growth original position or about 4.6 to 5.0 μ m.

6, a kind of method that is used to make p-channel-type thin-film transistor the method is characterized in that to comprise:

Use has the laser emission non-single crystal semiconductor film of reverse peak shape light intensity distributions so that by the step of the regional crystallization of radiation with the formation crystal region; And

The drain electrode by will be adjacent with channel region or the lateral edges of source area are arranged in this crystal region the step that forms thin-film transistor away from crystal growth original position or vertical-growth original position 0.7 to 2.6 μ m or 3.1 to 4.5 μ m.

7, a kind of display is characterized in that: thin-film transistor according to claim 1 is arranged in the peripheral circuit part that comprises signal and scan line drive circuit and need operate under high speed.

8, a kind of display is characterized in that: thin-film transistor according to claim 2 is arranged in the peripheral circuit part that comprises signal and scan line drive circuit and need operate under high speed.

9, a kind of display is characterized in that: thin-film transistor according to claim 3 is arranged in the peripheral circuit part that comprises signal and scan line drive circuit and need operate under high speed.

10, a kind of display is characterized in that: thin-film transistor according to claim 4 is arranged in the peripheral circuit part that comprises signal and scan line drive circuit and need operate under high speed.

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