CN1893110A - Nitride semiconductor device - Google Patents

Nitride semiconductor device Download PDF

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Publication number
CN1893110A
CN1893110A CN 200610095956 CN200610095956A CN1893110A CN 1893110 A CN1893110 A CN 1893110A CN 200610095956 CN200610095956 CN 200610095956 CN 200610095956 A CN200610095956 A CN 200610095956A CN 1893110 A CN1893110 A CN 1893110A
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layer
ohmic electrode
nitride
based semiconductor
thickness
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狩野隆司
太田洁
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

A nitride semiconductor device includes a nitride semiconductor layer having a main surface, and an ohmic electrode formed on the main surface of the nitride semiconductor layer. The ohmic electrode includes a silicon layer formed to contact with the main surface of the nitride semiconductor layer, and a first metal layer formed on the silicon layer.

Description

Nitride-based semiconductor device
Cross reference with related application
The application is based on the Japanese patent application of submitting to June 29 formerly 2005-190316 number, and advocates its priority, to its full content at this in conjunction with to do reference.
Technical field
The present invention relates to a kind of nitride-based semiconductor device, relate in particular to a kind of nitride-based semiconductor device that possesses the Ohmic electrode that on the nitride-based semiconductor layer, forms.
Background technology
In the past, known have a nitride-based semiconductor device (for example opening flat 9-69623 communique with reference to the spy) that possesses the Ohmic electrode that forms on the nitride-based semiconductor floor.
In above-mentioned patent documentation 1, following technology is disclosed, promptly on the nitride-based semiconductor layer of n type, form after the Ohmic electrode, by under about 500 ℃～about 700 ℃, annealing, make Ohmic electrode and nitride-based semiconductor layer ohmic contact well.
In addition, in the past, known have possess the mode that contact with first type surface with nitride-based semiconductor layers such as InGaN layer and AlGaN layers form with Al be main component layer and the nitride-based semiconductor device of the Ohmic electrode of Ti layer etc.This nitride-based semiconductor device, under the state that utilizes wafer process (wafer process) to make, the ohm property of Ohmic electrode and nitride-based semiconductor layer is good, on the other hand, in assembling procedure, if apply about 250 ℃～about 350 ℃ heat when welding waits, then ohm property worsens.Like this, when the ohm property of Ohmic electrode and nitride-based semiconductor layer worsened, the forward voltage of diode characteristic (Vf) rose, and consumed the defective that electric power increases so exist.Therefore, same with above-mentioned patent documentation 1 in the past, after forming Ohmic electrode,, make Ohmic electrode and nitride-based semiconductor layer ohmic contact well by under about 500 ℃～about 700 ℃ high temperature, annealing.
Like this, nitride-based semiconductor device in the past, after forming Ohmic electrode, under the situation of at high temperature not annealing, the ohm property that has Ohmic electrode and a nitride-based semiconductor layer is the problem that worsens of the heat when assembling sometimes.
In addition, disclosed nitride-based semiconductor device in the above-mentioned patent documentation 1, same with above-mentioned nitride-based semiconductor device in the past, on the nitride-based semiconductor layer of n type, form after the Ohmic electrode, not under the situation of annealing under the high temperature about 500 ℃～about 700 ℃ under, the ohm property that has Ohmic electrode and a nitride-based semiconductor layer is the problem that worsens of the heat when assembling sometimes.
Summary of the invention
The nitride-based semiconductor device of a first aspect of the present invention possesses nitride-based semiconductor layer with first type surface and the Ohmic electrode that forms on the first type surface of nitride-based semiconductor layer, Ohmic electrode comprises silicon layer that contacts formation with the first type surface of nitride-based semiconductor layer and the first metal layer that forms on silicon layer.
In the nitride-based semiconductor device of this first aspect, as mentioned above, by being constituted, Ohmic electrode comprises silicon layer that contacts formation with the first type surface of nitride-based semiconductor layer and the first metal layer that on silicon layer, forms, because the effect of the silicon layer that contacts with the first type surface of nitride-based semiconductor layer, in the assembling procedure after Ohmic electrode forms, even under the situation that applies for example about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen, and worsens because of heat so can suppress the ohm property of Ohmic electrode and nitride-based semiconductor layer.This point is by experimental verification described later.As the effect of this silicon layer, consider following aspect.Think: with at the big nitride-based semiconductor layer of band gap (bandgap) (for example, band gap: the situation difference that directly forms the first metal layer on the first type surface about 3.5eV), by (for example across the little silicon layer of band gap, band gap: about 1.1eV) form the first metal layer, can make Ohmic electrode ohmic contact well by the nitride-based semiconductor layer, simultaneously, in assembling procedure, even under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of above-mentioned good Ohmic contact.
In the nitride-based semiconductor device of above-mentioned first aspect, preferred above-mentioned the first metal layer comprise can with the metal of above-mentioned nitride-based semiconductor layer ohmic contact.
In the nitride-based semiconductor device of above-mentioned first aspect, preferred: Ohmic electrode forms on the nitride-based semiconductor layer of p type, and the first metal layer comprises at least one side among Pd and the Pt.Constitute if so, even then in the nitride-based semiconductor layer of the p type that is difficult to obtain ohmic contact, on the nitride-based semiconductor layer of p type, form the first metal layer that comprises at least one side among Pd and the Pt by silicon layer, also can easily obtain the more good Ohmic contact of the nitride-based semiconductor layer of Ohmic electrode and p type thus, and, in assembling procedure,, also can keep the state of its good Ohmic contact even under the situation that applies about 250 ℃～about 350 ℃ heat.
In the nitride-based semiconductor device of above-mentioned first aspect, preferred: Ohmic electrode forms on the nitride-based semiconductor layer of n type, and Ohmic electrode also comprises the Al layer that is configured between silicon layer and the first metal layer.Constitute if so, then forming on the nitride-based semiconductor layer of n type under the situation of Ohmic electrode, can easily obtain the more good Ohmic contact of the nitride-based semiconductor layer of Ohmic electrode and n type, and, in assembling procedure, even under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of its good Ohmic contact.
In the nitride-based semiconductor device of above-mentioned first aspect, preferred: above-mentioned Ohmic electrode forms on the above-mentioned nitride-based semiconductor layer of n type, between above-mentioned silicon layer and above-mentioned the first metal layer, comprises the either party of Pd layer and Pt layer at least.
In the nitride-based semiconductor device of above-mentioned first aspect, preferred silicon layer is made of amorphous silicon.Constitute if so, then because amorphous silicon contains a lot of defectives, so become conducting state because of the defective that contains in the amorphous silicon between nitride-based semiconductor layer and the Ohmic electrode.Thus, think that the characteristic that can suppress Ohmic electrode is owing to the influence of the heat that produces worsens in the assembling procedure of the nitride-based semiconductor electronic device with nitride-based semiconductor device.
In the nitride-based semiconductor device of above-mentioned first aspect, preferably also possesses second metal level that on Ohmic electrode, forms.Constitute if so, then can easily Ohmic electrode be connected with external electric by second metal level.
In the nitride-based semiconductor device of above-mentioned first aspect, preferred silicon layer has the following thickness of the above 30nm of 0.5nm.Confirm by experiment: if silicon layer is set at such thickness, then make Ohmic electrode and nitride-based semiconductor layer ohmic contact more well easily, and, in assembling procedure, even under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of its good Ohmic contact.
The nitride-based semiconductor device of a second aspect of the present invention possesses the nitride-based semiconductor layer of p type and the Ohmic electrode that forms on the nitride-based semiconductor layer of p type, Ohmic electrode is included in silicon layer that forms on the nitride-based semiconductor layer of p type and the first metal layer that forms on silicon layer.
In the nitride-based semiconductor device of this second aspect, as mentioned above, by Ohmic electrode being constituted the silicon layer that forms on the nitride-based semiconductor layer that is included in the p type, with the first metal layer that on silicon layer, forms, because the effect of the silicon layer that on the nitride-based semiconductor layer of p type, forms, even in the nitride-based semiconductor layer of the p type that is difficult to obtain ohmic contact, also can access the good Ohmic contact of the nitride-based semiconductor layer of Ohmic electrode and p type, simultaneously, in the assembling procedure after Ohmic electrode forms, even under the situation that applies for example about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen, and worsens because of heat so can suppress the ohm property of the nitride-based semiconductor layer of Ohmic electrode and p type.This point is by experimental verification described later.As the effect of this silicon layer, consider following aspect.Think: with at the big nitride-based semiconductor layer of band gap (for example, band gap: the situation difference that directly forms the first metal layer on the first type surface about 3.5eV), by (for example across the little silicon layer of band gap, band gap: about 1.1eV) form the first metal layer, can make Ohmic electrode ohmic contact well by the nitride-based semiconductor layer of p type, simultaneously, in assembling procedure, even under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of above-mentioned good Ohmic contact.
In the nitride-based semiconductor device of above-mentioned second aspect, preferred: between the nitride-based semiconductor layer and silicon layer of p type, be provided with can with the ohmic metal layer of the nitride-based semiconductor layer ohmic contact of p type.Form silicon layer like this on by the nitride-based semiconductor layer of ohmic metal layer and forming on this silicon layer under the situation of the first metal layer in the p type, effect by silicon layer, can access the more good Ohmic contact of the nitride-based semiconductor layer of the Ohmic electrode that comprises ohmic metal layer, silicon layer and the first metal layer and p type, and, in assembling procedure, even under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of its good Ohmic contact.
The nitride-based semiconductor device of a third aspect of the present invention possesses the nitride-based semiconductor layer of n type and the Ohmic electrode that forms on the nitride-based semiconductor layer of said n type, above-mentioned Ohmic electrode is included in silicon layer that forms on the nitride-based semiconductor layer of said n type and the first metal layer that forms on above-mentioned silicon layer, above-mentioned the first metal layer comprise can with the material of the nitride-based semiconductor layer ohmic contact of said n type, above-mentioned Ohmic electrode comprises any in Pd layer and the Pt layer at least between above-mentioned silicon layer and above-mentioned the first metal layer.
In the nitride-based semiconductor device of this third aspect, owing between the nitride-based semiconductor layer of n type and the first metal layer, be formed with silicon layer and Pd layer or silicon layer and Pt layer, so the characteristic that can suppress Ohmic electrode worsens owing to the influence of the heat that produces in the assembling procedure of the nitride-based semiconductor electronic device with nitride-based semiconductor device.
At this, though Pd layer and Pt layer with respect to p type nitride-based semiconductor layer ohmic contact, are the materials that forms schottky junction with respect to n type nitride-based semiconductor layer.In the nitride-based semiconductor device of this aspect, the Ohmic electrode as the nitride-based semiconductor layer of n type by common obsolete Pd layer or Pt layer are included in the Ohmic electrode, can suppress the characteristic degradation of Ohmic electrode.
In the nitride-based semiconductor device of the above-mentioned third aspect, preferred above-mentioned silicon layer is made of amorphous silicon.Constitute if so, then because amorphous silicon contains a lot of defectives, so become conducting state because of the defective that contains in the amorphous silicon between the nitride-based semiconductor layer of n type and the Pd layer (or Pt layer).Thus, think: even in the assembling procedure of nitride-based semiconductor electronic device, apply heat treatment about 300 ℃～400 ℃ with nitride-based semiconductor device, a little reaction only takes place between the first metal layer and the Pd layer (or Pt layer), so can keep the nitride-based semiconductor layer of n type and the ohmic contact of the first metal layer.
Description of drawings
Fig. 1 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression first execution mode of the present invention.
Fig. 2 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of first execution mode shown in Fig. 1.
Fig. 3 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of first execution mode shown in Fig. 1.
Fig. 4 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of first execution mode shown in Fig. 1.
Fig. 5 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of first execution mode shown in Figure 1.
Fig. 6 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of first execution mode shown in Figure 1.
Fig. 7 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of first execution mode shown in Figure 1.
Fig. 8 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of first execution mode shown in Figure 1.
Fig. 9 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 10 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 11 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 12 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 13 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 14 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 15 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 16 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 17 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 18 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 19 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 20 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 21 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 22 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 23 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 24 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.
Figure 25 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression second execution mode of the present invention.
Figure 26 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of second execution mode shown in Figure 25.
Figure 27 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of second execution mode shown in Figure 25.
Figure 28 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of second execution mode shown in Figure 25.
Figure 29 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of second execution mode shown in Figure 25.
Figure 30 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of second execution mode shown in Figure 25.
Figure 31 is the sectional view of structure of the nitride-based semiconductor light-emitting diode (nitride-based semiconductor device) of expression the 3rd execution mode of the present invention.
Figure 32 is the figure of structure that is used to describe in detail the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.
Figure 33 is the figure of structure that is used to describe in detail the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.
Figure 34 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.
Figure 35 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.
Figure 36 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.
Figure 37 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.
Figure 38 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.
Figure 39 is used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor light-emitting diode of confirming the 3rd execution mode shown in Figure 31 and the figure of the experiment of carrying out.
Figure 40 is the sectional view of structure of the nitride-based semiconductor light-emitting diode (nitride-based semiconductor device) of expression the 4th execution mode of the present invention.
Figure 41 is the figure of structure that is used to describe in detail the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.
Figure 42 is the figure of structure that is used to describe in detail the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.
Figure 43 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.
Figure 44 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.
Figure 45 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.
Figure 46 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.
Figure 47 is used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor light-emitting diode of confirming the 4th execution mode shown in Figure 40 and the figure of the experiment of carrying out.
Figure 48 is used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor light-emitting diode of confirming the 4th execution mode shown in Figure 40 and the figure of the experiment of carrying out.
Figure 49 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression the 5th execution mode of the present invention.
Figure 50 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of the 5th execution mode shown in Figure 49.
Figure 51 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of the 5th execution mode shown in Figure 49.
Figure 52 is used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor laser device of confirming the 5th execution mode shown in Figure 49 and the figure of the experiment of carrying out.
Figure 53 is used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor laser device of confirming the 5th execution mode shown in Figure 49 and the figure of the experiment of carrying out.
Figure 54 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression the 6th execution mode of the present invention.
Figure 55 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of the 6th execution mode shown in Figure 54.
Figure 56 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of the 6th execution mode shown in Figure 54.
Figure 57 is the sectional view of structure of the bipolar transistor (nitride-based semiconductor device) of expression the 7th execution mode of the present invention.
Figure 58 is the figure of structure that is used to describe in detail the bipolar transistor of the 7th execution mode shown in Figure 57.
Figure 59 is the figure of structure that is used to describe in detail the bipolar transistor of the 7th execution mode shown in Figure 57.
Figure 60 is the figure of structure that is used to describe in detail the bipolar transistor of the 7th execution mode shown in Figure 57.
Figure 61 is the sectional view of manufacturing process that is used to illustrate the bipolar transistor of the 7th execution mode shown in Figure 57.
Figure 62 is the sectional view of manufacturing process that is used to illustrate the bipolar transistor of the 7th execution mode shown in Figure 57.
Figure 63 is the sectional view of manufacturing process that is used to illustrate the bipolar transistor of the 7th execution mode shown in Figure 57.
Figure 64 is the sectional view of manufacturing process that is used to illustrate the bipolar transistor of the 7th execution mode shown in Figure 57.
Figure 65 is the figure of structure that is used to illustrate the nitride-based semiconductor device of the 8th execution mode of the present invention.
Figure 66 is the figure of structure that is used to describe in detail the nitride-based semiconductor device of the 8th execution mode of the present invention shown in Figure 65.
Figure 67 is used to describe in detail the figure of structure of the nitride-based semiconductor device of the 8th execution mode of the present invention shown in Figure 65.
Figure 68 is the figure of structure that is used to illustrate the nitride-based semiconductor device of the 9th execution mode of the present invention.
Figure 69 is the figure of structure that is used to describe in detail the nitride-based semiconductor device of the 9th execution mode of the present invention shown in Figure 68.
Figure 70 is the figure of structure that is used to describe in detail the nitride-based semiconductor device of the 9th execution mode of the present invention shown in Figure 68.
Figure 71 is used to illustrate for the effect of the n side Ohmic electrode of the nitride-based semiconductor device of confirming the 9th execution mode shown in the 8th execution mode shown in Figure 65 and Figure 68 and the figure of the experiment of carrying out.
Figure 72 is used to illustrate for the effect of the n side Ohmic electrode of the nitride-based semiconductor device of confirming the 9th execution mode shown in the 8th execution mode shown in Figure 65 and Figure 68 and the figure of the experiment of carrying out.
Figure 73 is used to illustrate for the effect of the n side Ohmic electrode of the nitride-based semiconductor device of confirming the 9th execution mode shown in the 8th execution mode shown in Figure 65 and Figure 68 and the figure of the experiment of carrying out.
Figure 74 is used to illustrate for the effect of the n side Ohmic electrode of the nitride-based semiconductor device of confirming the 9th execution mode shown in the 8th execution mode shown in Figure 65 and Figure 68 and the figure of the experiment of carrying out.
Embodiment
Below, with reference to accompanying drawing embodiments of the present invention are described.
(first execution mode)
Fig. 1 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression first execution mode of the present invention.Fig. 2～Fig. 4 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of first execution mode shown in Fig. 1.With reference to Fig. 1～Fig. 4, at first, the structure of the nitride-based semiconductor laser device of first execution mode is described.
In the nitride-based semiconductor laser device of first execution mode, as shown in Figure 1, on the first type surface of n type GaN substrate 1, be formed with have about 400nm thickness by Al xGa 1-xThe n type coating layer (clad layer) 2 that N (x=0.07) constitutes.N type GaN substrate 1 is an example of " the nitride-based semiconductor layer of n type " of the present invention.On n type coating layer 2, be formed with the active layer 3 of MQW structure (multiple quantum trap structure).As shown in Figure 2, this active layer 3 have with have about 3nm thickness by In xGa 1-xA plurality of well layer 3a that N (x=0.15) constitutes with have about 20nm thickness by In xGa 1-xThe MQW structure of a plurality of barrier layer 3b alternative stacked that N (x=0.02) constitutes.In addition, on active layer 3, as shown in Figure 1, be formed with by having Al about 400nm thickness, that comprise protuberance and par and doped with Mg xGa 1-xThe p type coating layer 4 that N (x=0.07) constitutes.
In addition, on the protuberance of p type coating layer 4, be formed with by In with about 10nm thickness and doped with Mg xGa 1-xThe p type contact layer 5 that N (x=0.02) constitutes.Protuberance and p type contact layer 5 by p type coating layer 4 constitute ridge (ridge) portion that becomes current path.P type contact layer 5 is examples of " the nitride-based semiconductor layer of p type " of the present invention.In addition, on p type contact layer 5, be formed with p side Ohmic electrode 6.P side Ohmic electrode 6 is examples of " Ohmic electrode " of the present invention.
At this, in the first embodiment, as shown in Figure 3, p side Ohmic electrode 6 by have about 1nm thickness and contact with the surface of p type contact layer 5 Si (silicon) the layer 6a that constitutes by amorphous silicon that form, with the Pd layer 6b formation with about 20nm thickness.In addition, Pd layer 6b is an example of " the first metal layer " of the present invention.
In addition, as shown in Figure 1, form by SiO in the mode of the side that covers spine and p side Ohmic electrode 6 2The current barrier layer 7 that constitutes.
In addition, in the first embodiment, in the regulation zone on p side Ohmic electrode 6 and current barrier layer 7, form pad electrode (pad electrode) 8 in the mode that contacts above with p side Ohmic electrode 6.Pad electrode 8 is examples of " second metal level " of the present invention.This pad electrode 8 is from p side Ohmic electrode 6 sides, is made of the Ti layer (not shown) with about 100nm thickness, the Au layer (not shown) that has the Pd layer (not shown) of about 150nm thickness and have about 300nm thickness successively.
In addition, the back side of n type GaN substrate 1 (below) on the regulation zone in, be formed with n side Ohmic electrode 9.N side Ohmic electrode 9 is examples of " Ohmic electrode " of the present invention.
In addition, in the first embodiment, as shown in Figure 4, n side Ohmic electrode 9 is from n type GaN substrate 1 side, is made of the Pd layer 9c that has about 1nm thickness and contact Si layer 9a that the amorphous silicon that forms constitutes with n type GaN substrate 1 following, have the Al layer 9b of about 6nm thickness and have about 30nm thickness successively.Wherein, Al layer 9b and Pd layer 9c are examples of " the first metal layer " of the present invention.In addition, in the first embodiment, below n side Ohmic electrode 9 on, as shown in Figure 1, be formed with the pad electrode 10 that constitutes by Au layer with about 300nm thickness.Pad electrode 10 is examples of " second metal level " of the present invention.
Below, the result of the forward voltage the when nitride-based semiconductor laser device of first execution mode measured the forward current that flows through about 20mA is described.In addition, as a comparative example, the Pd layer only is set in p side Ohmic electrode the Si layer not being set and in n side Ohmic electrode, the Si layer is not set and existing nitride-based semiconductor laser device that Al layer and Pd layer only be set is also measured forward voltage.As a result, the nitride-based semiconductor laser device of first execution mode after wafer process, for the forward voltage of 4.4V, after assembling procedure, is the forward voltage of 4.2V.Relative therewith, existing nitride-based semiconductor laser device, after wafer process, the forward voltage for the 4.4V that equates with above-mentioned first execution mode after assembling procedure, is the forward voltage of 7.5V.That is, the result is: existing nitride-based semiconductor laser device, and after the assembling procedure, forward voltage rises, and the nitride-based semiconductor laser device of first execution mode, forward voltage improves.Can confirm according to this result, have about 1nm thickness and the Si layer 6a that forms in the mode that contacts with p type contact layer 5, n side Ohmic electrode 9 constituted to comprise simultaneously and have about 1nm thickness and contact the Si layer 9a that forms by p side Ohmic electrode 6 being constituted comprise, can suppress the ohm property of the ohm property of p side Ohmic electrode 6 and p type contact layer 5 and n side Ohmic electrode 9 and n type GaN substrate 1 after p side Ohmic electrode 6 and 9 formation of n side Ohmic electrode because the about 250 ℃～about 350 ℃ heat that applies during welding when assembling worsens with n type GaN substrate 1.
In the first embodiment, as mentioned above, p side Ohmic electrode 6 constituted to comprise have about 1nm thickness and contact the Si layer 6a that forms with the first type surface of p type contact layer 5, with the Pd layer 6b that on Si layer 6a, forms with about 20nm thickness, and, n side Ohmic electrode 9 constituted to comprise have about 1nm thickness and contact the Si layer 9a that forms with n type GaN substrate 1 following, the Al layer 9b that forms on below Si layer 9a with about 6nm thickness, with below Al layer 9b on the Pd layer 9c that form with about 30nm thickness, thus, by the Si layer 6a that contact with the first type surface of p type contact layer 5 and n type GaN substrate 1 respectively and the effect of 9a, even during the welding the during assembling after p side Ohmic electrode 6 and 9 formation of n side Ohmic electrode, apply under the situation of about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen.Thus, can suppress p side Ohmic electrode 6 worsens because of heat with the ohm property of p type contact layer 5 and the ohm property of n side Ohmic electrode 9 and n type GaN substrate 1.This point is by experimental verification described later.As the effect of this Si layer 6a and 9a, consider following aspect.Think: with (band gap: the situation that directly forms Pd layer 6b and Al layer 9b on the first type surface about 3.5eV) respectively is different at the big p type contact layer 5 of band gap and n type GaN substrate 1, by respectively across little Si layer 6a of band gap and 9a (band gap: about 1.1eV) form Pd layer 6b and Al layer 9b, can make p side Ohmic electrode 6 and n side Ohmic electrode 9 respectively with p type contact layer 5 and n type GaN substrate 1 ohmic contact more well, and, when the welding in when assembling, even under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of above-mentioned good Ohmic contact.
In addition, in the first embodiment, Si layer 6a and 9a are formed amorphous silicon, the Si layer 6a and the 9a that are made of amorphous silicon are because inside has a lot of defectives (not shown), so can electronics be passed through through these a plurality of defectives (not shown).Thus, electronics can be respectively between Si layer 6a and 9a are easily by Pd layer 6b and p type contact layer 5 and between Al layer 9b and the n type GaN substrate 1, so can easily make p side Ohmic electrode 6 and n side Ohmic electrode 9 respectively with p type contact layer 5 and n type GaN substrate 1 ohmic contact.
Fig. 5～Fig. 8 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of first execution mode shown in Figure 1.Below, with reference to Fig. 1～Fig. 8, the manufacturing process of the nitride-based semiconductor device of first execution mode is described.
At first, as shown in Figure 5, use MOCVD (Metal Organic Chemical VaporDeposition: method metal organic chemical vapor deposition), on the first type surface of n type GaN substrate 1 successively growth have about 400nm thickness by Al xGa 1-xThe n type coating layer 2 that N (x=0.07) constitutes, the active layer 3 of MQW structure, by Al with about 400nm thickness and doped with Mg xGa 1-xThe p type coating layer 4 that N (x=0.07) constitutes and by In with about 10nm thickness and doped with Mg xGa 1-xThe p type contact layer 5 that N (x=0.02) constitutes.When growth activity layer 3, make have about 3nm thickness by In xGa 1-xA plurality of well layer 3a (with reference to Fig. 2) that N (x=0.15) constitutes and have about 20nm thickness by In xGa 1-xA plurality of barrier layer 3b (with reference to Fig. 2) alternating growth that N (x=0.02) constitutes.After this, use the electron beam evaporation plating method, on p type contact layer 5, form p side Ohmic electrode 6 and SiO with about 300nm thickness 2Layer 11.In the first embodiment, under the situation that forms p side Ohmic electrode 6, form the Pd layer 6b (with reference to Fig. 3) that has the Si layer 6a (with reference to Fig. 3) of about 1nm thickness and have about 20nm thickness successively.At this moment, because Si layer 6a is by the formation of electron beam evaporation plating method, so form amorphous silicon.So, use photoetching technique, at SiO 2In the regulation zone on the layer 11, form resist 12.
Then, as shown in Figure 6, with resist 12 as mask, use RIE (Reactive IonEtching: method reactive ion etching), remove from SiO 2The upper surface of layer 11 exposes the part on the surface of p type coating layer 4 to the regulation zone of p type coating layer 4 degree of depth midway.Thus, in p type coating layer 4, form par and protuberance, simultaneously, form the spine that constitutes by the protuberance of p type coating layer 4 and the p type contact layer 5 on this protuberance.At this moment, SiO 2Layer 11 and p side Ohmic electrode 6 use based on CF 4The RIE method of gas is removed, and p type contact layer 5 and p type coating layer 4 use based on Cl 2The RIE method of gas is removed.After this, remove the operation of liquid and the operation of the HF that use cushions, remove resist 12 and SiO through using resist 2 Layer 11.
Then, as shown in Figure 7, use plasma CVD method, with the mode that covers whole form have about 300nm thickness by SiO 2The current barrier layer 7 that constitutes.Then, use photoetching technique, the part on the current barrier layer 7 that is positioned on the p side Ohmic electrode 6 forms the resist 13 with peristome 13a.At this moment, the peristome 13a of resist 13 forms and has A/F and become big tilted shape upward gradually.So, as mask, use based on CF with resist 13 4The RIE method of gas is carried out etching to the current barrier layer 7 of the part of the peristome 13a of resist 13.At this moment, the A/F of the peristome 13a of resist 13 shown in the arrow of Fig. 7, little by little becomes big along with etched carrying out.Thus, current barrier layer 7 above be flattened.After this, remove resist 13, become state shown in Figure 8.
After this, in the first embodiment, as shown in Figure 1, use the electron beam evaporation plating method, on p side Ohmic electrode 6 and on the regulation zone of current barrier layer 7, Au layer (not shown) from p side Ohmic electrode 6 sides are piled up the Ti layer (not shown) with about 100nm thickness, the Pd layer (not shown) with about 150nm thickness successively and had about 300nm thickness forms pad electrode 8.Afterwards, use and grind and etching technique, n type GaN substrate 1 is formed the thickness with about 100nm.
Afterwards, in the first embodiment, use the electron beam evaporation plating method, in the regulation zone below n type GaN substrate 1 on (back side), from n type GaN substrate 1 side, pile up Si layer 9a (with reference to Fig. 4) successively, have the Al layer 9b (with reference to Fig. 4) of about 6nm thickness and have the Pd layer 9c (with reference to Fig. 4) of about 30nm thickness, formation n side Ohmic electrode 9 with about 1nm thickness.At this moment, Si layer 9a is because by the formation of electron beam evaporation plating method, so form amorphous silicon.Then, use the electron beam evaporation plating method, below n side Ohmic electrode 9 on, form the pad electrode 10 of Au layer formation with about 300nm thickness.
Fig. 9～Figure 24 is used to illustrate for the effect of the nitride-based semiconductor laser device of confirming first execution mode shown in Figure 1 and the figure of the experiment of carrying out.Below, illustrate for the effect of the nitride-based semiconductor laser device of confirming above-mentioned first execution mode and the experiment of carrying out with reference to Fig. 9～Figure 24.In this experiment, making is used to measure the sample (with reference to Fig. 9) of p side Ohmic electrode and n side Ohmic electrode ohm property separately, and estimates.As the manufacture method of this sample, at first, as shown in Figure 9, use mocvd method, on n type GaN substrate 21, form p type InGaN layer 22 with about 3nm thickness.Then,, on p type InGaN layer 22, separate the interval of regulation, form 2 p side Ohmic electrodes 23 by vacuum vapour deposition.Then, by vacuum vapour deposition, below n type GaN substrate 21 on, separate the interval of regulation, form 2 n side Ohmic electrodes 24.
At first, with reference to Fig. 9～Figure 21, illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor laser device of confirming above-mentioned first execution mode and the experiment of carrying out.In this experiment, p side Ohmic electrode 23 is constituted the Pd layer with about 20nm thickness that comprises on the Si layer that contact with p type InGaN layer 22 and this Si layer, and make the varied in thickness of Si layer.Particularly, make the sample that the Si layer is formed the thickness of about 0.5nm, about 1nm, about 2nm, about 10nm, about 15nm, about 20nm and about 30nm respectively.In addition, as a comparative example, make: the sample that only forms p side Ohmic electrode 23 by Pd layer with about 10nm thickness; Pt layer with about 1nm thickness that is provided with by replacing the Si layer and the Pd layer with about 10nm thickness that forms on the Pt layer form the sample of p side Ohmic electrode 23; Only form the sample of p side Ohmic electrode 23 by the Pt layer.Then, measure to form after the said sample and at set point of temperature (about 300 ℃, about 350 ℃, about 400 ℃, about 500 ℃ and the about 600 ℃) I-E characteristic (I-V characteristic) after the heat treatment 5 minutes down.It is the results are shown in Figure 10～Figure 16, Figure 18 and Figure 19.In addition, the resistance value under the state (as depo. state) of not heat-treating after forming with sample is carried out standardization as benchmark, calculates the variation ratio of resistance value.It is the results are shown in Figure 17 and Figure 20.Use is measured I-E characteristic as the kymograph of one of detecting characteristic of semiconductor device.The following describes these measurement result.
In that being constituted, p side Ohmic electrode 23 comprises under the situation that contacts with p type InGaN layer 22 with Si layer of the following thickness of about 30nm more than about 0.5nm, can clearly distinguish according to Figure 10～I-V characteristic shown in Figure 16 and resistance variations ratio shown in Figure 17, under about situation of heat-treating below 350 ℃, the ohm property of p side Ohmic electrode 23 does not worsen.In addition, under the thickness of Si layer is situation more than the 15nm, can distinguish clearly that from Figure 14～I-V characteristic shown in Figure 16 and resistance variations ratio shown in Figure 17 if heat-treat, then ohm property worsens under about 400 ℃.Relative therewith, only forming under the situation of p side Ohmic electrode 23 by Pd layer with about 10nm thickness, can clearly distinguish from I-V characteristic shown in Figure 180 and resistance variations ratio shown in Figure 20, under the situation of heat-treating under about 300 ℃, the ohm property of p side Ohmic electrode 23 worsens, and along with heat treatment temperature increases, the deterioration of ohm property further develops.In addition, do not comprising the Si layer, forming by Pt layer and Pd layer under the situation of p side Ohmic electrode 23, can clearly distinguish from I-V characteristic shown in Figure 19 and resistance variations ratio shown in Figure 20, under the situation of heat-treating under about 300 ℃, the ohm property of p side Ohmic electrode 23 worsens, and becomes with respect to heat treated temperature, resistance value increase and decrease labile state.In addition,, can distinguish clearly that under the situation of heat-treating under about 300 ℃ and about 400 ℃, the ohm property of p side Ohmic electrode 23 worsens from resistance variations ratio shown in Figure 20 only forming under the situation of p side Ohmic electrode 23 by the Pt layer.
Below, describe the I-V characteristic under each thickness of Si layer of correspondence of first execution mode and the I-V characteristic of comparative example in detail.Thickness at the Si layer is that as shown in figure 10, under about situation of heat-treating below 400 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.) under the situation of about 0.5nm, worsens.On the other hand, under the situation of heat-treating under about 500 ℃, resistance value (R=V/I) increases slightly, and the ohm property of p side Ohmic electrode 23 worsens slightly.In addition, under the situation of heat-treating under about 600 ℃, the ohm property of p side Ohmic electrode 23 worsens significantly, can not get ohmic contact.In addition, under the situation of about 1nm, as shown in figure 11, under about situation of heat-treating below 500 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.) at the thickness of Si layer, deterioration.Under the situation of heat-treating under about 600 ℃, resistance value increases, and the ohm property of p side Ohmic electrode 23 worsens.In addition, under the situation of about 2nm, as shown in figure 12, under about situation of heat-treating below 500 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.) at the thickness of Si layer, deterioration.Under the situation of heat-treating under about 600 ℃, resistance value increases, and the ohm property of p side Ohmic electrode 23 worsens.In addition, under the situation of about 10nm, as shown in figure 13, under about situation of heat-treating below 400 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.) at the thickness of Si layer, deterioration.In addition, under the situation of heat-treating under about 500 ℃, resistance value increases slightly, and the ohm property of p side Ohmic electrode 23 worsens slightly.In addition, under the situation of heat-treating under about 600 ℃, resistance value further increases, and the ohm property of p side Ohmic electrode 23 further worsens.
In addition, under the situation of about 15nm, as shown in figure 14, under about situation of heat-treating below 350 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.) at the thickness of Si layer, deterioration.Under the situation of heat-treating under about 400 ℃, resistance value increases slightly, and the ohm property of p side Ohmic electrode 23 worsens slightly.Under the situation of heat-treating under about 500 ℃ and about 600 ℃, ohm property worsens significantly.In addition, under the situation of about 20nm, as shown in figure 15, under about situation of heat-treating below 350 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.) at the thickness of Si layer, deterioration.Under the situation of heat-treating under about 400 ℃～about 600 ℃, ohm property worsens significantly.In addition, under the situation of about 30nm, as shown in figure 16, under about situation of heat-treating below 350 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.) at the thickness of Si layer, deterioration.Under the situation of heat-treating under about 400 ℃～about 600 ℃, ohm property worsens significantly.
Relative therewith, under the situation of the comparative example that is only formed p side Ohmic electrode 23 by the Pd layer with about 10nm thickness, as shown in figure 18, under the situation of heat-treating under about 300 ℃, resistance value increases, and the ohm property of p side Ohmic electrode 23 worsens.In addition, under the situation of heat-treating under about 400 ℃, the ohm property of p side Ohmic electrode 23 worsens significantly, can not get ohmic contact.In addition, under the situation of heat-treating under about 500 ℃ and 600 ℃, the ohm property of p side Ohmic electrode 23 further worsens.In addition, formed by Pt layer and Pd layer under the situation of p side Ohmic electrode 23, as shown in figure 19, under the situation of heat-treating under about 300 ℃, resistance value increases slightly, and the ohm property of p side Ohmic electrode 23 worsens slightly.In addition, under the situation of heat-treating under about 400 ℃, the ohm property of p side Ohmic electrode 23 worsens significantly, can not get ohmic contact.In addition, under the situation of heat-treating under about 500 ℃, ohm property recovers, and obtains forming the identical ohm property in back with sample.In addition, under the situation of heat-treating under about 600 ℃, the ohm property of p side Ohmic electrode 23 worsens significantly, can not get ohmic contact.
In addition, by comprise the Si layer in p side Ohmic electrode 23, under about situation of heat-treating below 350 ℃, the ohm property of p side Ohmic electrode 23 does not worsen, and can consider following reason.Promptly, can think this be because: have about 0.5nm～about 30nm thickness and contact the Si layer of formation with the first type surface of p type InGaN layer 22 by p side Ohmic electrode 23 being constituted comprise, with the Pd layer that on the Si layer, forms with about 20nm thickness, with (band gap: the situation that directly forms the Pd layer on the first type surface about 3.5eV) is different at the big p type InGaN layer 22 of band gap, by across the little Si layer of band gap (band gap: about 1.1eV) form the Pd layer, can make p side Ohmic electrode ohmic contact well by p type InGaN layer 22, simultaneously, under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of good Ohmic contact.
In addition, as mentioned above, form the Si layer, the Si layer is formed amorphous silicon by utilizing vacuum vapour deposition.The Si layer that is made of amorphous silicon has a lot of defectives in the inside of Si layer like this, so can electronics be passed through through these a lot of defectives.Thus, can think: because electronics can be between the Si layer be easily by Pd layer and p type InGaN layer 22, so can easily make p side Ohmic electrode 23 and p type InGaN layer 22 ohmic contact.
In addition, variation as above-mentioned first execution mode, under the situation that p side Ohmic electrode 23 is constituted the Au layer that comprises the Si layer that contacts with p type InGaN layer 22, the Pd layer that is forming on the Si layer and forming on the Pd layer, also measure I-E characteristic with about 10nm thickness with about 20nm thickness with about 1nm thickness.The result obtains and p side Ohmic electrode 23 is constituted the identical I-E characteristic of situation (with reference to Figure 11) that comprises Si layer with about 1nm thickness that contacts with p type InGaN layer 22 and the Pd layer with about 20nm thickness that forms on the Si layer as shown in figure 21.Thus, distinguish: form the situation and the situation that does not form the Au layer of Au layer on the Pd layer of p side Ohmic electrode 23, ohm property does not have difference.
Then, with reference to Fig. 9 and Figure 22～Figure 24, illustrate for the effect of the n side Ohmic electrode of the nitride-based semiconductor laser device of confirming above-mentioned first execution mode and the experiment of carrying out.In this experiment, the n side Ohmic electrode 24 of sample that will be corresponding with first execution mode shown in Figure 9 constitute comprise the Si layer that contact with the back side (following) of n type GaN substrate 21 with about 1nm thickness, below the Si layer on formation the Al layer with about 6nm thickness and below the Al layer on the Pd layer with about 30nm thickness of formation.In addition, as a comparative example, with n side Ohmic electrode 24 constitute comprise the Al layer that contacts with the back side (following) of n type GaN substrate 21 with about 6nm thickness and below the Al layer on the Pd layer that forms with about 30nm thickness.And, similarly measure I-E characteristic (I-V characteristic) with the experiment of carrying out for the effect of confirming above-mentioned p side Ohmic electrode, calculate the variation ratio of resistance value.It is the results are shown in Figure 22～Figure 24.
Under the situation of the sample corresponding that forms n side Ohmic electrode 24 by Si layer, Al layer and Pd layer with first execution mode, as Figure 22 and shown in Figure 24, under the situation of heat-treating under about 300 ℃, the ohm property of n side Ohmic electrode 24 is identical with the situation of not heat-treating (asdepo.), does not worsen.On the other hand, under the situation of heat-treating under about 400 ℃, resistance value increases slightly, and the ohm property of p side Ohmic electrode 23 worsens slightly.In addition, under the situation of heat-treating under about 500 ℃, obtain forming the not bad ohm property in back than sample.In addition, under the situation of heat-treating under about 600 ℃, obtain forming better ohm property of back than sample.Relative therewith, under the situation of the sample of the comparative example that forms n side Ohmic electrode 24 by Al layer and Pd layer, as Figure 23 and shown in Figure 24, under the situation of heat-treating under about 300 ℃, the ohm property of n side Ohmic electrode 24 worsens significantly, can not get ohmic contact.Thus, distinguish: the situation of sample that forms first execution mode of n side Ohmic electrode 24 by Si layer, Al layer and Pd layer, compare with the situation of the sample of the comparative example that is formed n side Ohmic electrode 24 by Al layer and Pd layer, the ohm property that can suppress n side Ohmic electrode 24 worsens because of heat treatment.
In addition, the deterioration of the ohm property by n side Ohmic electrode 24 being constituted the n side Ohmic electrode 24 that comprises the Si layer, causes because of heat treatment is suppressed, can think since with the same reason of situation of p side Ohmic electrode 23.
(second execution mode)
Figure 25 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression second execution mode of the present invention.Figure 26 is the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of second execution mode shown in Figure 25.With reference to Figure 25 and Figure 26, illustrate in this second execution mode, different with above-mentioned first execution mode, make the thickness of the Si layer of p side Ohmic electrode increase to the situation of about 2nm.
In the nitride-based semiconductor laser device of second execution mode, as shown in figure 25, be formed with n type GaN substrate 1, n type coating layer 2, active layer 3 and p type coating layer 4 with the composition identical and thickness with above-mentioned first execution mode.In addition, same with above-mentioned first execution mode on the protuberance of p type coating layer 4, be formed with In with about 10nm thickness and doped with Mg xGa 1-xThe p type contact layer 5 that N (x=0.02) constitutes.In addition, form by SiO with the side of the protuberance that covers p type coating layer 4 and the top mode of par 2The current barrier layer 107 that constitutes.
In addition, the mode with the top and side that covers regulation zone on current barrier layer 107 top and p type contact layer 5 is formed with p side Ohmic electrode 106.P side Ohmic electrode 106 is examples of " Ohmic electrode " of the present invention.At this, in second execution mode, p side Ohmic electrode 106, as shown in figure 26, from p type contact layer 5 sides, successively by have about 2nm thickness and contact Si (silicon) the layer 106a that constitutes by amorphous silicon that form with the surface of p type contact layer 5 and on Si layer 106a on the Pd layer 106b formation that forms with about 20nm thickness.That is, different with the thickness (1nm) of the Si layer 6a of the p side Ohmic electrode 6 of first execution mode in this second execution mode, be 2nm with the thickness setting of the Si layer 106a of p side Ohmic electrode 106.In addition, the structure of the p side Ohmic electrode 106 of this second execution mode is identical with the p side Ohmic electrode 6 of first execution mode.Wherein, Pd layer 106b is an example of " the first metal layer " of the present invention.
In addition, on p side Ohmic electrode 106, as shown in figure 25, be formed with pad electrode 108.Pad electrode 108 is examples of " second metal level " of the present invention.This pad electrode 108 is from p side Ohmic electrode 106 sides, is made of Ti layer (not shown) with about 100nm thickness and Au layer (not shown) with about 1 μ m thickness successively.
In addition, in the regulation zone below n type GaN substrate 1 on (back side), be formed with n side Ohmic electrode 9 and pad electrode 10 with composition and the thickness identical with above-mentioned first execution mode.Promptly, n side Ohmic electrode 9, as shown in Figure 4, from n type GaN substrate 1 side, constitute by the Pd layer 9c that has about 1nm thickness and contact the Si layer 9a that constitutes by amorphous silicon that form with n type GaN substrate 1 following, have the Al layer 9b of about 6nm thickness and have about 100nm thickness successively.
Below, the result of the forward voltage the when nitride-based semiconductor laser device of second execution mode measured the forward current that flows through about 20mA is described.The nitride-based semiconductor laser device of second execution mode and above-mentioned first execution mode are same, after wafer process, are the forward voltage of 4.4V, and, after assembling procedure, be the forward voltage of 4.2V.Can confirm according to this result, different with above-mentioned first execution mode, the thickness of the Si layer 106a of p side Ohmic electrode 106 is increased under the situation of about 2nm, also same with above-mentioned first execution mode, the about 250 ℃～about 350 ℃ heat of the ohm property that can suppress p side Ohmic electrode 106 and p type contact layer 5 during because of assembling worsens.
In second execution mode, as mentioned above, p side Ohmic electrode 106 constituted to comprise have about 2nm thickness and contact the Si layer 106a that forms with the first type surface of p type contact layer 5, with the Pd layer 106b that on Si layer 106a, forms with about 20nm thickness, simultaneously, n side Ohmic electrode 9 constituted to comprise have about 1nm thickness and contact the Si layer 9a that forms with n type GaN substrate 1 following, with below Si layer 9a on the Al layer 9b that form with about 6nm thickness, with the Pd layer 9c that on Al layer 9b, forms with about 100nm thickness, thus, same with above-mentioned first execution mode, by the Si layer 106a that contact with the first type surface of p type contact layer 5 and n type GaN substrate 1 respectively and the effect of 9a, during welding during assembling after p side Ohmic electrode 106 and n side Ohmic electrode 9 forms, apply under the situation of about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen.Thus, can suppress the ohm property of p side Ohmic electrode 106 and p type contact layer 5 and the ohm property of n side Ohmic electrode 9 and n type GaN substrate 1 worsens because of heat.
In addition, other effect of second execution mode and above-mentioned first execution mode are same.
Figure 27～Figure 30 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor laser device of second execution mode shown in Figure 25.Next, with reference to Figure 25～Figure 30, the manufacturing process of the nitride-based semiconductor laser device of second execution mode is described.
At first, use and the same operation of first execution mode shown in Figure 5, on n type GaN substrate 1, growing n-type coating layer 2, active layer 3, p type coating layer 4 and p type contact layer 5 successively.After this, as shown in figure 27, use the electron beam evaporation plating method, on P type contact layer 5, form SiO with about 300nm thickness 2Layer 111.Then, use photoetching technique, at SiO 2In the regulation zone on the layer 111, form resist 112.
Then, as shown in figure 28, as mask, use the RIE method with resist 112, will be from SiO 2Remove in upper surface to the regulation zone of the degree of depth midway of p type coating layer 4 of layer 111, and the part on the surface of p type coating layer 4 is exposed.Thus, in p type coating layer 4, form par and protuberance, and, the spine that constitutes by the protuberance of p type coating layer 4 and the p type contact layer 5 on this protuberance formed.At this moment, same with above-mentioned first execution mode, SiO 2Layer 111 uses based on CF 4The RIE method of gas is removed, and p type contact layer 5 and p type coating layer 4 use based on Cl 2The RIE method of gas is removed.After this, remove the operation of liquid and the operation of the HF that use cushions, remove resist 112 and SiO through using resist 2 Layer 111.
Then, as shown in figure 29, use plasma CVD method, form by SiO in the mode that covers whole 2The current barrier layer 107 that constitutes.Afterwards, same with the operation of the formation resist 13 of above-mentioned first execution mode, use photoetching technique, the part on the current barrier layer 107 that is positioned on the p type contact layer 5 forms the resist 113 with peristome 113a.Afterwards, use and the same operation of above-mentioned first execution mode, as mask, use based on CF with resist 113 4The RIE method of gas is carried out etching to the current barrier layer 107 of the part of the peristome 113a of resist 113.After this, remove resist 113, become state shown in Figure 30.
After this, as shown in figure 25, use the electron beam evaporation plating method, on p type contact layer 5 and on the regulation zone of current barrier layer 107, form p side Ohmic electrode 106.
In addition, in second execution mode, under the situation that forms p side Ohmic electrode 106, form the Si layer 106a (with reference to Figure 26) of thickness successively and have the Pd layer 106b (with reference to Figure 26) of about 20nm thickness with about 2nm.At this moment, Si layer 106a is because by the formation of electron beam evaporation plating method, so form amorphous silicon.
Then, use the electron beam evaporation plating method, on p side Ohmic electrode 106,, pile up the Au layer (not shown) that has the Ti layer (not shown) of about 100nm thickness and have about 1 μ m thickness successively, form pad electrode 108 from p side Ohmic electrode 106 sides.Afterwards, use and the same operation of above-mentioned first execution mode, in the regulation zone below n type GaN substrate 1 on (back side), form n side Ohmic electrode 9 that constitutes by Si layer 9a (with reference to Fig. 4), Al layer 9b and Pd layer 9c and the pad electrode 10 that constitutes by the Au layer.
(the 3rd execution mode)
Figure 31 is the sectional view of structure of the nitride-based semiconductor light-emitting diode (nitride-based semiconductor device) of expression the 3rd execution mode of the present invention.Figure 32 and Figure 33 are the figure of structure that is used to describe in detail the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.With reference to Figure 31～Figure 33, illustrate in the 3rd execution mode, different with above-mentioned first execution mode, on the p type contact layer that constitutes by GaN, form p side Ohmic electrode, and constitute the situation of p side Ohmic electrode by Si layer, Pd layer and Ti layer.
In the nitride-based semiconductor light-emitting diode of the 3rd execution mode, as shown in figure 31, on sapphire substrate 201, be formed with the n type coating layer 202 that constitutes by GaN with about 400nm thickness.N type coating layer 202 is examples of " the nitride-based semiconductor layer of n type " of the present invention.In the regulation zone on n type coating layer 202, be formed with the active layer 203 of MQW structure of the layer of identical composition of the active layer 3 of lamination and above-mentioned first execution mode and thickness.
At this, in the 3rd execution mode, on active layer 203, be formed with p type contact (coating) layer 205 of GaN formation with about 400nm thickness and doped with Mg.P type contact layer 205 is examples of " the nitride-based semiconductor layer of p type " of the present invention.In addition, will be above p type contact layer 205 remove to the regulation zone of the degree of depth midway of n type coating layer 202.
In addition, in the regulation zone on p type contact layer 205, be formed with the p side Ohmic electrode 206 that has through the function of light.P side Ohmic electrode 206 is examples of " Ohmic electrode " of the present invention.In addition, in the 3rd execution mode, p side Ohmic electrode 206, shown in figure 32, from p type contact layer 205 sides, successively by having about 1nm thickness and contacting Si (silicon) the layer 206a that constitutes by amorphous silicon that form with the surface of p type contact layer 205, have the Pd layer 206b of about 5nm thickness and have the Ti layer 206c formation of about 1nm thickness.Wherein, Pd layer 206b is an example of " the first metal layer " of the present invention.
In addition, to cover the mode of p side Ohmic electrode 206 and n type coating layer 202, form by SiO 2The surface protection film 207 that constitutes.This surface protection film 207 has peristome 207a in the regulation zone on p side Ohmic electrode 206, simultaneously, has peristome 207b in the regulation zone on n type coating layer 202.In addition, on p side Ohmic electrode 206, be formed with pad electrode 208 in mode through peristome 207a contact.Wherein, pad electrode 208 is examples of " second metal level " of the present invention.This pad electrode 208 is from p side Ohmic electrode 206 sides, is made of the Ti layer (not shown) with about 10nm thickness, the Au layer (not shown) that has the Pd layer (not shown) of about 100nm thickness and have about 300nm thickness successively.
In addition, on n type coating layer 202, be formed with n side Ohmic electrode 209 in mode through peristome 207b contact.Wherein, n side Ohmic electrode 209 is examples of " Ohmic electrode " of the present invention.This n side Ohmic electrode 209, as shown in figure 33, from n type coating layer 202 sides, constitute by the Pd layer 209c that has about 1nm thickness and contact the Si layer 209a that constitutes by amorphous silicon that form with the surface of n type coating layer 202, have the Al layer 209b of about 6nm thickness and have about 100nm thickness successively.Wherein, Al layer 209b and Pd layer 209c are examples of " the first metal layer " of the present invention.In addition, on n side Ohmic electrode 209, as shown in figure 31, be formed with the pad electrode 210 that constitutes by Au layer with about 300nm thickness.Wherein, pad electrode 210 is examples of " second metal level " of the present invention.
The result of the forward voltage when the nitride-based semiconductor light-emitting diode of the 3rd execution mode measured the forward current that flows through about 20mA then, is described.In addition, as a comparative example, also existing nitride-based semiconductor light-emitting diode is measured forward voltage.Existing nitride-based semiconductor light-emitting diode constitutes and comprises: by the Pd layer with about 2nm thickness, have the Au layer of about 4nm thickness and have the p side Ohmic electrode that the Ni layer of about 1nm thickness forms; The pad electrode that the Au layer by having about 300nm thickness that forms on p side Ohmic electrode constitutes; By Al layer with have the n side Ohmic electrode that the Pd layer of about 30nm thickness forms with about 6nm thickness; The pad electrode that constitutes with the Au layer that on n side Ohmic electrode, forms by having about 300nm thickness.As a result, the nitride-based semiconductor light-emitting diode of the 3rd execution mode after wafer process, is the forward voltage of about 3.5V, and, after assembling procedure, be the forward voltage of about 3.5V.Relative therewith, existing nitride-based semiconductor light-emitting diode after wafer process, is the forward voltage of about 3.5V, and, after assembling procedure, be the forward voltage of about 4.0V.That is, the result is: existing nitride-based semiconductor light-emitting diode, and after assembling procedure, forward voltage rises; And the nitride-based semiconductor light-emitting diode of the 3rd execution mode, forward voltage does not change.Can confirm according to this result: on, the p type contact layer 205 that by GaN constituting different, form p side Ohmic electrode 206 with above-mentioned first execution mode and the n type coating layer 202 that constituting by GaN on form under the situation of n side Ohmic electrode 209, also same with above-mentioned first execution mode, can suppress the ohm property of the ohm property of p side Ohmic electrode 206 and p type contact layer 205 and n side Ohmic electrode 209 and n type coating layer 202 because about 250 ℃～about 350 ℃ heat when assembling worsens.In addition, the light transmission rate of p side Ohmic electrode 206 is about about 70%, equates with the light transmission rate of in the past p side Ohmic electrode.
In the 3rd execution mode, as mentioned above, p side Ohmic electrode 206 constituted to comprise have about 1nm thickness and contact the Si layer 206a that forms with the first type surface of p type contact layer 205, the Pd layer 206b that on Si layer 206a, forms with about 5nm thickness, with Ti layer 206c with about 1nm thickness, simultaneously, n side Ohmic electrode 209 constituted to comprise have about 1nm thickness and contact the Si layer 209a that forms with the first type surface of n type coating layer 202, the Al layer 209b that on Si layer 209a, forms with about 6nm thickness, with the Pd layer 209c that on Al layer 209b, forms with about 100nm thickness, thus, same with above-mentioned first execution mode, by the Si layer 206a that contact with the first type surface of p type contact layer 205 and n type coating layer 202 respectively and the effect of 209a, during welding during assembling after p side Ohmic electrode 206 and n side Ohmic electrode 209 forms, apply under the situation of about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen.Thus, can suppress p side Ohmic electrode 206 worsens because of heat with the ohm property of p type contact layer 205 and the ohm property of n side Ohmic electrode 209 and n type coating layer 202.This point is by experimental verification described later.
In addition, other effect of the 3rd execution mode and above-mentioned first execution mode are same.
Figure 34～Figure 38 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 3rd execution mode shown in Figure 31.Next, with reference to Figure 31～Figure 38, the manufacturing process of the nitride-based semiconductor light-emitting diode of the 3rd execution mode is described.
At first, in the 3rd execution mode, as shown in figure 34, use mocvd method, on sapphire substrate 201, successively growth have the n type coating layer 202 that constitutes by GaN, the MQW structure of about 400nm thickness active layer 203, have p type that the GaN of about 400nm thickness and doped with Mg constitutes and contact (coating) layers 205.Wherein, active layer 203 similarly forms with the active layer 3 of above-mentioned first execution mode.Then, use photoetching technique, in the regulation zone on p type contact layer 205, form resist 212.
Then, as shown in figure 35, resist 212 as mask, is used the RIE method, will be above p type contact layer 205 remove, the part on the surface of n type coating layer 202 is exposed to the regulation zone of the degree of depth midway of n type coating layer 202.After this, remove resist 212.
Then, as shown in figure 36, use the electron beam evaporation plating method, in the regulation zone on p type contact layer 205, form p side Ohmic electrode 206.In addition, in the 3rd execution mode, under the situation that forms p side Ohmic electrode 206, form Si layer 206a (with reference to Figure 32) successively, have the Pd layer 206b of about 5nm thickness and have the Ti layer 206c of about 1nm thickness with about 1nm thickness.At this moment, because Si layer 206a is by the formation of electron beam evaporation plating method, so form amorphous silicon.Then, use plasma CVD method, with the mode that covers whole form have about 300nm thickness by SiO 2The surface protection film 207 that constitutes.Afterwards, use photoetching technique, in the regulation zone on surface protection film 207, form resist 213.
Then, as shown in figure 37, resist 213 as mask, is used the HF of buffering, etched surfaces diaphragm 207.Thus, in surface protection film 207, form peristome 207a.Afterwards, remove resist 213.
Then, as shown in figure 38, use the electron beam evaporation plating method, on the surface of the p side Ohmic electrode 206 that exposes by peristome 207a, Au layer (not shown) from p side Ohmic electrode 206 sides are piled up the Ti layer (not shown) with about 10nm thickness, the Pd layer (not shown) with about 100nm thickness successively and had about 300nm thickness forms pad electrode 208.
Afterwards, as shown in figure 31, use and the same operation of operation that in surface protection film 207, forms peristome 207a, form peristome 207b in the regulation zone of the surface protection film 207 on n type coating layer 202.Then, use the electron beam evaporation plating method, on the surface of the n type coating layer 202 that exposes by peristome 207b, from n type coating layer 202 sides, pile up Si layer 209a (with reference to Figure 33) successively, have the Al layer 209b (with reference to Figure 33) of about 6nm thickness and have the Pd layer 209c (with reference to Figure 33) of about 100nm thickness, formation n side Ohmic electrode 209 with about 1nm thickness.At this moment, Si layer 209a is because by the formation of electron beam evaporation plating method, so form amorphous silicon.Then, use the electron beam evaporation plating method, on n side Ohmic electrode 209, form the pad electrode 210 that constitutes by Au layer with about 300nm thickness.
Figure 39 is used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor light-emitting diode of confirming the 3rd execution mode shown in Figure 31 and the figure of the experiment of carrying out.Next, the experiment of carrying out for the effect of the p side Ohmic electrode of the nitride-based semiconductor light-emitting diode of confirming above-mentioned the 3rd execution mode with reference to Fig. 9 and Figure 39 explanation.In this experiment, same with above-mentioned first execution mode, making is used to measure the sample (with reference to Fig. 9) of p side Ohmic electrode and n side Ohmic electrode ohm property separately, and estimates.As shown in Figure 9, this sample forms the p type GaN layer 22a with about 3nm thickness on n type GaN substrate 21.Then, utilize vacuum vapour deposition, on p type GaN layer 22a, separate the interval of regulation, form 2 p side Ohmic electrodes 23.Then, utilize vacuum vapour deposition, below n type GaN substrate 21 on, separate the interval of regulation, form 2 n side Ohmic electrodes 24.Wherein, the Pd layer that p side Ohmic electrode 23 has the Si layer of about 2nm thickness by setting and formation has about 20nm thickness on the Si layer forms.Then, similarly measure I-E characteristic with the experiment of carrying out for the effect of confirming p side Ohmic electrode of above-mentioned first execution mode.It is the results are shown in Figure 39.
Under the situation that p side Ohmic electrode 23 is formed at the 3rd execution mode on the p type GaN layer 22a, as shown in figure 39, distinguish: under about situation of heat-treating below 400 ℃, the ohm property of p side Ohmic electrode 23 does not worsen.Particularly, under about situation of heat-treating below 400 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.), does not worsen.In addition, under the situation of heat-treating under about 500 ℃ and about 600 ℃, resistance value increases slightly, and the ohm property of p side Ohmic electrode 23 worsens slightly.
(the 4th execution mode)
Figure 40 is the sectional view of structure of the nitride-based semiconductor light-emitting diode (nitride-based semiconductor device) of expression the 4th execution mode of the present invention.Figure 41 and Figure 42 are the figure of structure that is used to describe in detail the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.With reference to Figure 40～Figure 42, illustrate in the 4th execution mode, different with above-mentioned the 3rd execution mode, constitute the situation of p side Ohmic electrode by Si layer, Pt layer, Ti layer and Pd layer.
In the nitride-based semiconductor light-emitting diode of the 4th execution mode, as shown in figure 40, below n type GaN substrate 301 on, be formed with the n type coating layer 302 that constitutes by GaN that comprises protuberance and par with about 400nm thickness.Wherein, n type GaN substrate 301 is examples of " the nitride-based semiconductor layer of n type " of the present invention.In the regulation zone on below the protuberance of n type coating layer 302, the active layer 303 of the MQW structure of the layer of active layer 3 same compositions of formation lamination and above-mentioned first execution mode and thickness.In addition, below active layer 303 on, be formed with p type contact (coatings) that GaN with about 400nm thickness and doped with Mg constitutes layers 305.Wherein, p type contact layer 305 is examples of " the nitride-based semiconductor layer of p type " of the present invention.In addition, will be below p side contact layer 305 remove to the regulation zone of the degree of depth midway of n type coating layer 302.
In addition, the mode with the following side that covers p side contact layer 305 and n type coating layer 302 forms by SiO 2The surface protection film 307 that constitutes.The part in the regulation zone of this surface protection film 307 on below p type contact layer 305 has peristome 307a.In addition, in p type contact layer 305, form p side Ohmic electrode 306 in mode through peristome 307a contact.Wherein, p side Ohmic electrode 306 is examples of " Ohmic electrode " of the present invention.
At this, in the 4th execution mode, as shown in figure 41, p side Ohmic electrode 306 is from p type contact layer 305 sides, successively by having about 2nm thickness and contacting Si (silicon) layer 306a, the Pt layer 306b with about 20nm thickness, the Ti layer 306c with about 10nm thickness that are made of amorphous silicon that form with p type contact layer 305 following, have the Pd layer 306d formation of about 100nm thickness.Wherein, Pt layer 306b, Ti layer 306c and Pd layer 306d are examples of " the first metal layer " of the present invention.In addition, below p side Ohmic electrode 306 on, with the mode that contacts below of p side Ohmic electrode 306, be formed with the pad electrode 308 that Au layer with about 300nm thickness constitutes.Wherein, pad electrode 308 is examples of " second metal level " of the present invention.
In addition, in the regulation zone on n type GaN substrate 301, as shown in figure 40, be formed with n side Ohmic electrode 309.Wherein, n side Ohmic electrode 309 is examples of " Ohmic electrode " of the present invention.As shown in figure 42, this n side Ohmic electrode 309 is from n type GaN substrate 301 sides, is made of the Pd layer 309c that has about 1nm thickness and contact the Si layer 309a that is made of amorphous silicon that form with the surface of n type GaN substrate 301, have the Al layer 309b of about 10nm thickness and have about 100nm thickness successively.Wherein, Al layer 309b and Pd layer 309c are examples of " the first metal layer " of the present invention.In addition, on n side Ohmic electrode 309, as shown in figure 40, be formed with the pad electrode 310 of Au layer formation with about 300nm thickness.Wherein, pad electrode 310 is examples of " second metal level " of the present invention.
The result of the forward voltage when the nitride-based semiconductor light-emitting diode of the 4th execution mode measured the forward current that flows through about 20mA then, is described.The nitride-based semiconductor light-emitting diode of the 4th execution mode, same with above-mentioned the 3rd execution mode, the result is: with respect to the forward voltage after the wafer process, the forward voltage after the assembling procedure does not change.Can confirm according to this result: different with above-mentioned the 3rd execution mode, p side Ohmic electrode is constituted under the situation that comprises Si layer, Pt layer, Ti layer and Pd layer, also same with above-mentioned the 3rd execution mode, can suppress the ohm property of p side Ohmic electrode 306 and p type contact layer 305 and n side Ohmic electrode 309 and n type GaN substrate 301 ohm property since the about 250 ℃～about 350 ℃ heat that applies during welding during assembling after p side Ohmic electrode 306 and 309 formation of n side Ohmic electrode worsen.In addition, the light reflectivity of p side Ohmic electrode 306 is about about 70% during for 400nm at emission wavelength, equates with the light reflectivity of existing p side Ohmic electrode.
In the 4th execution mode, as mentioned above, p side Ohmic electrode 306 constituted to comprise have about 2nm thickness and contact the Si layer 306a that forms with p type contact layer 305 following, the Pt layer 306b that forms on below Si layer 306a with about 20nm thickness, the Ti layer 306c that forms on below Pt layer 306b with about 10nm thickness, with below Ti layer 306c on the Pd layer 306d that form with about 100nm thickness, and, n side Ohmic electrode 309 constituted to comprise have about 1nm thickness and contact the Si layer 309a that forms with the surface of n type GaN substrate 301, the Al layer 309b that on Si layer 309a, forms with about 10nm thickness, with the Pd layer 309c that on Al layer 309b, forms with about 100nm thickness, thus, same with above-mentioned first execution mode, by the Si layer 306a that contact with the first type surface of p type contact layer 305 and n type GaN substrate 301 respectively and the effect of 309a, during welding during assembling after p side Ohmic electrode 306 and n side Ohmic electrode 309 forms, apply under the situation of about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen.Thus, can suppress p side Ohmic electrode 306 worsens because of heat with the ohm property of p type contact layer 305 and the ohm property of n side Ohmic electrode 309 and n type GaN substrate 301.This point is by experimental verification described later.
In addition, other effect of the 4th execution mode and above-mentioned first execution mode are same.
Figure 43～Figure 46 is the sectional view of manufacturing process that is used to illustrate the nitride-based semiconductor light-emitting diode of the 4th execution mode shown in Figure 40.Next, with reference to Figure 40～Figure 46, the manufacturing process of the nitride-based semiconductor light-emitting diode of the 4th execution mode is described.In addition, when making the nitride-based semiconductor light-emitting diode,,, illustrate with the state of putting upside down up and down (state of Figure 43～Figure 46) so in the 4th execution mode, make Figure 40 Rotate 180 degree owing on n type substrate, form each layer.
At first, as shown in figure 43, use mocvd method, below n type GaN substrate 301 on, successively growth have the n type coating layer 302 that constitutes by GaN, the MQW structure of about 400nm thickness active layer 303, have p type that the GaN of about 400nm thickness and doped with Mg constitutes and contact (coating) layers 305.Wherein, active layer 303 similarly forms with the active layer 3 of above-mentioned first execution mode.Then, use photoetching technique, in the regulation zone on p type contact layer 305, form resist 312.
Then, as shown in figure 44, resist 312 as mask, is used the RIE method, remove below p type contact layer 305, the part on the surface of n type coating layer 302 is exposed to the regulation zone of n type coating layer 302 degree of depth midway.After this, remove resist 312.
Then, as shown in figure 45, use plasma CVD method, with the mode that covers whole form have about 300nm thickness by SiO 2The surface protection film 307 that constitutes.Then, use photoetching technique, in the regulation zone on surface protection film 307, form resist 313.Then, resist 313 as mask, is used the HF of buffering, etched surfaces diaphragm 307.Thus, in surface protection film 307, form peristome 307a.After this, remove resist 313.
Then, as shown in figure 46, use the electron beam evaporation plating method, on the surface of the p type contact layer 305 that exposes by peristome 307a, form p side Ohmic electrode 306.In addition, in the 4th execution mode, under the situation that forms p side Ohmic electrode 306, form Si layer 306a (with reference to Figure 41), Pt layer 306b successively, have the Ti layer 306c of about 10nm thickness and have the Pd layer 306d of about 100nm thickness with about 20nm thickness with about 2nm thickness.At this moment, Si layer 306a forms by the electron beam evaporation plating method, so form amorphous silicon.Then, use the electron beam evaporation plating method, on p side Ohmic electrode 306, pile up Au layer, form pad electrode 308 with about 300nm thickness.
Afterwards, as shown in figure 40, use the electron beam evaporation plating method, in the regulation zone on n type GaN substrate 301, from n type GaN substrate 301 sides, pile up Si layer 309a (with reference to Figure 42) successively, have the Al layer 309b of about 10nm thickness and have the Pd layer 309c of about 100nm thickness, formation n side Ohmic electrode 309 with about 1nm thickness.At this moment, Si layer 309a forms by the electron beam evaporation plating method, so form amorphous silicon.Then, use the electron beam evaporation plating method, on n side Ohmic electrode 309, form the pad electrode 310 of Au layer formation with about 300nm thickness.
Figure 47 and Figure 48 are used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor light-emitting diode of confirming the 4th execution mode shown in Figure 40 and the figure of the experiment of carrying out.Next, with reference to Fig. 9, Figure 47 and Figure 48, illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor light-emitting diode of confirming above-mentioned the 4th execution mode and the experiment of carrying out.In this experiment, same with above-mentioned first execution mode, making is used to measure the sample (with reference to Fig. 9) of p side Ohmic electrode and n side Ohmic electrode ohm property separately, and estimates.In addition, p side Ohmic electrode 23 (with reference to Fig. 9) is constituted comprise Si layer with about 1nm thickness and the Pt layer that on this Si layer, forms with about 20nm thickness.Then, similarly measure I-E characteristic, calculate the variation ratio of resistance value with the experiment of carrying out for the effect of confirming p side Ohmic electrode of above-mentioned first execution mode.The measurement result of I-E characteristic is shown in Figure 47, the calculating of variation ratio of resistance value be the results are shown in Figure 48.
Under the situation of the 4th execution mode that is formed p side Ohmic electrode 23 by Si layer and Pt layer, as Figure 47 and shown in Figure 48, distinguish: the ohm property of p side Ohmic electrode 23 is suppressed because of the deterioration that heat treatment produces.In addition, forming by Si layer and Pt layer under the situation of p side Ohmic electrode 23, as shown in figure 48, distinguish: obtain and the nitride-based semiconductor light-emitting diode same degree good Ohmic characteristic that forms above-mentioned first execution mode of p side Ohmic electrode 23 by Si layer and Pd layer.Particularly, formed by Si layer and Pt layer under the situation of p side Ohmic electrode 23, as shown in figure 47, by heat-treating under about 300 ℃, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.), does not worsen.In addition, under the situation of heat-treating under about 400 ℃, resistance value increases slightly, and the ohm property of p side Ohmic electrode 23 worsens slightly.In addition, under the situation of heat-treating under about 500 ℃ and about 600 ℃, obtain forming back (situation of not heat-treating) identical ohm property with sample.
(the 5th execution mode)
Figure 49 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression the 5th execution mode of the present invention.Figure 50 and Figure 51 are the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of the 5th execution mode shown in Figure 49.With reference to Figure 49～Figure 51, illustrate in the 5th execution mode, different with above-mentioned first execution mode, only in p side Ohmic electrode, comprise the Si layer, and, the situation of Pt layer or Pd layer also is set between Si layer and p side contact layer.
In the nitride-based semiconductor laser device of the 5th execution mode, as shown in figure 49, be formed with the n type GaN substrate 1, n type coating layer 2, active layer 3, p type coating layer 4 and the p type contact layer 5 that have with above-mentioned first execution mode same composition and thickness.In addition, on p type contact layer 5, be formed with p side Ohmic electrode 406.Wherein, p side Ohmic electrode 406 is examples of " Ohmic electrode " of the present invention.
At this, in the 5th execution mode, as shown in figure 50, p side Ohmic electrode 406 is from p type contact layer 5 sides, successively by have about 1nm thickness and can with Pt (Pd) the layer 406a of p type contact layer 5 ohmic contact, have Si (silicon) the layer 406b that constitutes by amorphous silicon of about 1nm thickness and on Si layer 406b on the Pd layer 406c formation that forms with about 20nm thickness.Pt (Pd) layer 406a is owing to being the less thickness of about 1nm, so consider to form island (not shown).Therefore, consider that Si layer 406b contacts partly with the part of not formation Pt (Pd) the layer 406a of p type contact layer 5.In addition, Pt (Pd) layer 406a is an example of " ohmic metal layer " of the present invention, and Pd layer 406c is an example of " the first metal layer " of the present invention.
In addition, same with above-mentioned first execution mode as shown in figure 49, be formed with the current barrier layer 7 that has with above-mentioned first execution mode same composition and thickness with the side of the protuberance that covers p type coating layer 4 and the top mode of par.Then, in the regulation zone on p side Ohmic electrode 406 and current barrier layer 7, be formed with pad electrode 408 in the mode that contacts above with p side Ohmic electrode 406.Pad electrode 408 is examples of " second metal level " of the present invention.This pad electrode 408 is from p side Ohmic electrode 406 sides, is made of the Ti layer (not shown) with about 100nm thickness, the Au layer (not shown) that has the Pd layer (not shown) of about 200nm thickness and have about 300nm thickness successively.
In addition, in the regulation zone on below n type GaN substrate 1, be formed with n side Ohmic electrode 409.In addition, in the 5th execution mode, n side Ohmic electrode 409 shown in Figure 51, from n type GaN substrate 1 side, is made of Al layer 409a with about 6nm thickness and the Pd layer 409b with about 100nm thickness successively.In addition, below n side Ohmic electrode 409 on, as shown in figure 49, be formed with the pad electrode 10 that has with above-mentioned first execution mode same composition and thickness.
The result of the forward voltage the when nitride-based semiconductor laser device of the 5th execution mode measured the forward current that flows through about 20mA then, is described.In addition, as a comparative example, the Pd layer only is set in p side Ohmic electrode the Si layer not being set and in n side Ohmic electrode, the Si layer is not set and existing nitride-based semiconductor laser device that Al layer and Pd layer only be set is also measured forward voltage.As a result, the nitride-based semiconductor laser device of the 5th execution mode after wafer process, for the forward voltage of 4.4V, after assembling procedure, is the forward voltage of 4.8V.Relative therewith, existing nitride-based semiconductor laser device after wafer process, for the forward voltage of 4.5V, after assembling procedure, is the forward voltage of 7.5V.That is, the result is: existing nitride-based semiconductor laser device, and after assembling procedure, forward voltage rising 3.0V, and the nitride-based semiconductor laser device of the 5th execution mode, behind assembling procedure, forward voltage rising 0.4V.Can think this be because: in the nitride-based semiconductor laser device of the 5th execution mode, because n side Ohmic electrode 409 is existing structures, so after assembling procedure, forward voltage rising 0.4V, on the other hand, by Si layer 406b is set in p side Ohmic electrode 406, can suppress ohm property and after assembling procedure, worsen.In addition, can confirm: under the situation that Pt (Pd) the layer 406a with about 1nm thickness is set between the Si layer 406b of p type contact layer 5 and p side Ohmic electrode 406, p side Ohmic electrode 406 is contacted well with p type contact layer 5.
In the 5th execution mode, as mentioned above, by being constituted, p side Ohmic electrode 406 comprises Pt (Pd) the layer 406a that has about 1nm thickness and on p type contact layer 5, form, 406a goes up the Si layer 406b with about 1nm thickness that forms at Pt (Pd) layer, with the Pd layer 406c that on Si layer 406b, forms with about 20nm thickness, same with above-mentioned first execution mode, effect by the Si layer 406b of formation on p type contact layer 5, during welding during assembling after p side Ohmic electrode 406 forms, apply under the situation of about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen.Thus, the ohm property that can suppress p side Ohmic electrode 406 and p type contact layer 5 worsens because of heat.This point is by experimental verification described later.As the effect of this Si layer 406b, can consider following aspect.Promptly, same with above-mentioned first execution mode, think: with (band gap: the situation that directly forms Pd layer 406c on the first type surface about 3.5eV) is different at the big p type contact layer 5 of band gap, by across the little Si layer 406b of band gap (band gap: about 1.1eV) form Pd layer 406c, can make p side Ohmic electrode 406 and p type contact layer 5 ohmic contact more well, and, when the welding in when assembling, under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of above-mentioned good Ohmic contact.
In addition, in the above-described 5th embodiment, between p type contact layer 5 and Si layer 406b, be provided with can with the Pt with about 1nm thickness (Pd) of p type contact layer 5 ohmic contact layer 406a.Forming Si layer 406b on the p type contact layer 5 and forming on this Si layer 406b under the situation of Pd layer 406c through Pt (Pd) layer 406a like this, effect by Si layer 406b, can obtain comprising the p side Ohmic electrode 406 of Pt (Pd) layer 406a, Si layer 406b and Pd layer 406c and the more good Ohmic contact of p type contact layer 5, and, in assembling procedure, under the situation that applies about 250 ℃～about 350 ℃ heat, can keep the state of this good Ohmic contact.
In addition, other effect of the 5th execution mode and above-mentioned first execution mode are same.
Next, with reference to Figure 49～Figure 51, the manufacturing process of the nitride-based semiconductor laser device of the 5th execution mode is described.
At first, use and the same operation of first execution mode shown in Figure 5 growing n-type coating layer 2, active layer 3, p type coating layer 4 and p type contact layer 5 successively on n type GaN substrate 1.After this, as shown in figure 49, use the electron beam evaporation plating method, on p type contact layer 5, form p side Ohmic electrode 406.
In addition, in the 5th execution mode, under the situation that forms p side Ohmic electrode 406, form Pt (Pd) layer of 406a (with reference to Figure 50) successively, have the Si layer 406b of about 1nm thickness and have the Pd layer 406c of about 20nm thickness with about 1nm thickness.At this moment, Pt (Pd) layer 406a is owing to the less thickness that forms about 1nm, so consider to form island (not shown).Therefore, consider that Si layer 406b contacts partly with the part of not formation Pt (Pd) the layer 406a of p type contact layer 5.In addition, Si layer 406b is because by the formation of electron beam evaporation plating method, so form amorphous silicon.Then, same with above-mentioned first execution mode as shown in figure 49, form current barrier layer 7.
Then, use the electron beam evaporation plating method, on p side Ohmic electrode 406 and on the regulation zone of current barrier layer 7, from p side Ohmic electrode 406 sides, pile up Ti layer (not shown) successively, have the Pd layer (not shown) of about 200nm thickness and have the Au layer (not shown) of about 300nm thickness, formation pad electrode 408 with about 100nm thickness.Afterwards, use and grind and etching technique, n type GaN substrate 1 is formed the thickness with about 100nm.Afterwards, use the electron beam evaporation plating method, in the regulation zone below n type GaN substrate 1 on (back side), from n type GaN substrate 1 side, pile up the Pd layer 409b that has the Al layer 409a (with reference to Figure 51) of about 6nm thickness and have about 100nm thickness successively, form n side Ohmic electrode 409.Then, with above-mentioned first execution mode similarly, below n side Ohmic electrode 409 on, form pad electrode 10.
Figure 52 and Figure 53 are used to illustrate for the effect of the p side Ohmic electrode of the nitride-based semiconductor laser device of confirming the 5th execution mode shown in Figure 49 and the figure of the experiment of carrying out.Next, the experiment of carrying out for the effect of the p side Ohmic electrode of the nitride-based semiconductor laser device of confirming above-mentioned the 5th execution mode with reference to Fig. 9, Figure 52 and Figure 53 explanation.In this experiment, same with above-mentioned first execution mode, make the sample (with reference to Fig. 9) of the ohm property be used to measure p side Ohmic electrode, and estimate.In addition, make p side Ohmic electrode 23 (with reference to Fig. 9) constituted comprise Pt layer with about 1nm thickness, constitute at the Si layer that forms on this Pt layer with at the sample of the Pd layer that forms on this Si layer with p side Ohmic electrode 23 with about 20nm thickness with about 1nm thickness comprise Pd layer with about 1nm thickness, at the sample of Si layer that forms on this Pd layer and the Pd layer that on this Si layer, forms with about 20nm thickness with about 1nm thickness.Then, similarly measure I-E characteristic with the experiment of carrying out for the effect of confirming p side Ohmic electrode of above-mentioned first execution mode.It is the results are shown in Figure 52 and Figure 53.
Under the situation of the 5th execution mode that is formed p side Ohmic electrode 23 by Pt layer, Si layer and Pd layer, distinguish: under about situation of heat-treating below 600 ℃, the ohm property of p side Ohmic electrode 23 does not worsen.In addition, under the situation of the 5th execution mode that is formed p side Ohmic electrode 23 by Pd layer, Si layer and Pd layer, distinguish: under about situation of heat-treating below 500 ℃, the ohm property of p side Ohmic electrode 23 does not worsen.Particularly, forming by Pt layer, Si layer and Pd layer under the situation of p side Ohmic electrode 23, shown in Figure 52, by under about 300 ℃～about 600 ℃, heat-treating, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.), does not worsen.In addition, forming by Pd layer, Si layer and Pd layer under the situation of p side Ohmic electrode 23, shown in Figure 53, by under about 300 ℃～about 500 ℃, heat-treating, the ohm property of p side Ohmic electrode 23 is identical with the situation of not heat-treating (as depo.), does not worsen.Under the situation of heat-treating under about 600 ℃, resistance value increases, and the ohm property of p side Ohmic electrode 23 worsens.Can confirm according to these results: do not make the Si layer that constitutes p side Ohmic electrode 23 contact with p type contact layer (p type InGaN layer 22), form between Si layer and the p type contact layer under the situation of Pd layer or Pt layer, because the use of Si layer, can obtain the more good Ohmic contact of p side Ohmic electrode 23 and p type contact layer (p type InGaN layer 22), and, in assembling procedure, under the situation that applies about 250 ℃～about 350 ℃ heat, also can keep the state of this good Ohmic contact.
(the 6th execution mode)
Figure 54 is the sectional view of structure of the nitride-based semiconductor laser device (nitride-based semiconductor device) of expression the 6th execution mode of the present invention.Figure 55 and Figure 56 are the figure of structure that is used to describe in detail the nitride-based semiconductor laser device of the 6th execution mode shown in Figure 54.With reference to Figure 54～Figure 56, illustrate in the 6th execution mode, different with above-mentioned first execution mode, only in n side Ohmic electrode, comprise the situation of Si layer.
In the nitride-based semiconductor laser device of the 6th execution mode, shown in Figure 54, be formed with the n type GaN substrate 1, n type coating layer 2, active layer 3, p type coating layer 4 and the p type contact layer 5 that have with above-mentioned first execution mode same composition and thickness.In addition, on p type contact layer 5, be formed with p side Ohmic electrode 506.
At this, in the 6th execution mode, shown in Figure 55, p side Ohmic electrode 506 is from p type contact layer 5 sides, is made of Pt layer 506a with about 1nm thickness and Pd layer 506b with about 20nm thickness successively.
In addition, same with above-mentioned first execution mode shown in Figure 54, with the side of the protuberance that covers p type coating layer 4 and the top mode of par, form the current barrier layer 7 that has with above-mentioned first execution mode same composition and thickness.Then, in the regulation zone on p side Ohmic electrode 506 and current barrier layer 7, be formed with pad electrode 508 in the mode that contacts above with p side Ohmic electrode 506.This pad electrode 508 is from p side Ohmic electrode 506 sides, is made of the Ti layer (not shown) with about 100nm thickness, the Au layer (not shown) that has the Pd layer (not shown) of about 200nm thickness and have about 300nm thickness successively.
In addition, in the regulation zone on below n type GaN substrate 1, form n side Ohmic electrode 509.N side Ohmic electrode 509 is examples of " Ohmic electrode " of the present invention.In addition, in the 6th execution mode, shown in Figure 56, n side Ohmic electrode 509 is from n type GaN substrate 1 side, successively by having about 1nm thickness and contacting Si (silicon) the layer 509a that is made of amorphous silicon that form with the surface of n type GaN substrate 1, have the Al layer 509b of about 6nm thickness and have the Pd layer 509c formation of about 30nm thickness.Wherein, Al layer 509b and Pd layer 509c are examples of " the first metal layer " of the present invention.In addition, below n side Ohmic electrode 509 on, shown in Figure 54, be formed with the pad electrode 10 that has with above-mentioned first execution mode same composition and thickness.
The result of the forward voltage the when nitride-based semiconductor laser device of the 6th execution mode measured the forward current that flows through about 20mA then, is described.In addition, as a comparative example, same with above-mentioned the 5th execution mode, the Pd layer only is set in p side Ohmic electrode the Si layer not being set, simultaneously in n side Ohmic electrode, the Si layer is not set and existing nitride-based semiconductor laser device that Al layer and Pd layer only be set is also measured forward voltage.As a result, the nitride-based semiconductor laser device of the 6th execution mode after wafer process, for the forward voltage of 4.4V, after assembling procedure, is the forward voltage of 7.0V.Relative therewith, existing nitride-based semiconductor laser device after wafer process, for the forward voltage of 4.5V, after assembling procedure, is the forward voltage of 7.5V.That is, the result is: existing nitride-based semiconductor laser device, and after assembling procedure, forward voltage rising 3.0V, and the nitride-based semiconductor laser device of the 6th execution mode, behind assembling procedure, forward voltage rising 2.6V.Can think this be because: in the nitride-based semiconductor laser device of the 6th execution mode, because p side Ohmic electrode 506 is existing structures, so after assembling procedure, forward voltage rising 2.6V, on the other hand, by Si layer 509a is set in n side Ohmic electrode 509, can suppress ohm property and after assembling procedure, worsen.
In the 6th execution mode, as mentioned above, have about 1nm thickness and contact the Si layer 509a that forms with n type GaN substrate 1 following by n side Ohmic electrode 509 being constituted comprise, the Al layer 509b that forms on below Si layer 509a with about 6nm thickness, with below Al layer 509b on the Pd layer 509c that form with about 30nm thickness, same with above-mentioned first execution mode, the effect of the Si layer 509a that contacts by first type surface with n type GaN substrate 1, during welding during assembling after n side Ohmic electrode 509 forms, apply under the situation of about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen.Thus, the ohm property that can suppress n side Ohmic electrode 509 and n type GaN substrate 1 worsens because of heat.
In addition, other effect of the 6th execution mode and above-mentioned first execution mode are same.
Next, with reference to Figure 54～Figure 56, the manufacturing process of the nitride-based semiconductor laser device of the 6th execution mode is described.
At first, use and the same operation of first execution mode shown in Figure 5, on n type GaN substrate 1, growing n-type coating layer 2, active layer 3, p type coating layer 4 and p type contact layer 5 successively.After this, shown in Figure 54, use the electron beam evaporation plating method, on p type contact layer 5, form p side Ohmic electrode 506.
In addition, in the 6th execution mode, under the situation that forms p side Ohmic electrode 506, form the Pd layer 506b that has the Pt layer 506a (with reference to Figure 55) of about 1nm thickness and have about 20nm thickness successively.Then, shown in Figure 54, similarly form current barrier layer 7 with above-mentioned first execution mode.
Then, use the electron beam evaporation plating method, on p side Ohmic electrode 506 and on the regulation zone of current barrier layer 7, from p side Ohmic electrode 506 sides, pile up Ti layer (not shown) successively, have the Pd layer (not shown) of about 200nm thickness and have the Au layer (not shown) of about 300nm thickness, formation pad electrode 508 with about 100nm thickness.Afterwards, use and grind and etching technique, n type GaN substrate 1 is formed the thickness with about 100nm.Afterwards, use and the same operation of above-mentioned first execution mode, in the regulation zone on below n type GaN substrate 1, form n side Ohmic electrode 509.N side Ohmic electrode 509 is formed by Si layer 509a, the Pd layer 509c that have the Al layer 509b of about 6nm thickness and have about 30nm thickness.Then, below n side Ohmic electrode 509 on, form and to have and the same composition of above-mentioned first execution mode and the pad electrode 10 of thickness.
(the 7th execution mode)
Figure 57 is the sectional view of structure of the bipolar transistor (nitride-based semiconductor device) of expression the 7th execution mode of the present invention.Figure 58～Figure 60 is the figure of structure that is used to describe in detail the bipolar transistor of the 7th execution mode shown in Figure 57.With reference to Figure 57～Figure 60, illustrate in the 7th execution mode, different with above-mentioned first～the 6th execution mode, nitride-based semiconductor device of the present invention is applied to situation in the bipolar transistor.
In the bipolar transistor of the 7th execution mode, shown in Figure 57, on sapphire substrate 601, be formed with unadulterated n type GaN substrate 602 and have the n type collector layer 603 that constitutes by GaN of about 300nm thickness with about 500nm thickness.Wherein, n type collector layer 603 is examples of " the nitride-based semiconductor layer of n type " of the present invention.In addition, in the regulation zone on the collector layer 603 of n type, be formed with collector electrode Ohmic electrode 604.Wherein, collector electrode Ohmic electrode 604 is examples of " Ohmic electrode " of the present invention.This collector electrode Ohmic electrode 604, shown in Figure 58, from collector layer 603 sides, successively by having about 1nm thickness and contacting Si (silicon) the layer 604a that constitutes by amorphous silicon that form with the surface of collector layer 603, have the Al layer 604b of about 6nm thickness and have the Pd layer 604c formation of about 30nm thickness.Wherein, Al layer 604b and Pd layer 604c are examples of " the first metal layer " of the present invention.In addition, on collector electrode Ohmic electrode 604, be formed with the pad electrode 605 of Au layer formation with about 300nm thickness.Pad electrode 605 is examples of " second metal level " of the present invention.
In addition, in the 7th execution mode, separating in the zone of predetermined distance with collector electrode Ohmic electrode 604 and pad electrode 605 on collector layer 603 is formed with the In with about 200nm thickness and doped with Mg xGa 1-xThe base layer 606 of the p type that N (x=0.02) constitutes.The base layer 606 of p type is an example of " the nitride-based semiconductor layer of p type " of the present invention.In addition, in the regulation zone on the base layer 606 of p type, be formed with base ohmic electrode 607.Base ohmic electrode 607 is examples of " Ohmic electrode " of the present invention.This base ohmic electrode 607 is shown in Figure 59, from base layer 606 sides, successively by having about 1nm thickness and contacting Si (silicon) layer 607a that is made of amorphous silicon that forms and the Pd layer 607b formation with about 20nm thickness with the surface of base layer 606.In addition, Pd layer 607b is an example of " the first metal layer " of the present invention.In addition, on base ohmic electrode 607, be formed with the pad electrode 608 of Au layer formation with about 10nm thickness.In addition, pad electrode 608 is examples of " second metal level " of the present invention.
In addition, in the 7th execution mode, separating in the zone of predetermined distance on base layer 606, be formed with the emitter layer 609 of the n type that constitutes by GaN with about 300nm thickness with base ohmic electrode 607 and pad electrode 608.The emitter layer 609 of n type is an example of " the nitride-based semiconductor layer of n type " of the present invention.In addition, in the regulation zone on the emitter layer 609 of n type, be formed with emitter Ohmic electrode 610.Emitter Ohmic electrode 610 is examples of " Ohmic electrode " of the present invention.This emitter Ohmic electrode 610, shown in Figure 60, from emitter layer 609 sides, constitute by the Pd layer 610c that has about 1nm thickness and contact the Si layer 610a that constitutes by amorphous silicon that form with the surface of emitter layer 609, have the Al layer 610b of about 6nm thickness and have about 30nm thickness successively.Al layer 610b and Pd layer 610c are examples of " the first metal layer " of the present invention.On emitter Ohmic electrode 610, be formed with the pad electrode 611 of Au layer formation with about 300nm thickness.Pad electrode 611 is examples of " second metal level " of the present invention.
The result of the bipolar transistor mensuration current amplification degree (magnification ratio of the relative base current of collector current) that the nitride-based semiconductor device by the 7th execution mode is constituted then, is described.In addition, as a comparative example, to Al layer and Pd layer being set by in the collector electrode Ohmic electrode Si layer not being set, simultaneously the Si layer not being set in base ohmic electrode and the Pd layer only is set and in the emitter Ohmic electrode, the Si layer is not set and the bipolar transistor that the existing nitride-based semiconductor device of Al layer and Pd layer constitutes is set also measures current amplification degree.The bipolar transistor of the 7th execution mode, after wafer process, the current amplification degree for about 13 after assembling procedure, also is about 13 current amplification degree.The bipolar transistor relative therewith, that existing nitride-based semiconductor device constitutes, after wafer process, about 13 current amplification degree for equating with above-mentioned the 7th execution mode after assembling procedure, drops to about 10 current amplification degree.Can think this be because: in existing bipolar transistor, because about 250 ℃～about 350 ℃ heat during assembling, the ohm property of collector electrode, base stage, emitter worsens, thereby produces voltage drop in the interface of the interface of the interface of collector electrode Ohmic electrode 604 and collector layer 603, base ohmic electrode 607 and base layer 606 and emitter Ohmic electrode 610 and emitter layer 609.Can confirm according to this result: bipolar transistor is being used under the situation of bipolar transistor, the about 250 ℃～about 350 ℃ heat that applies during the welding of the ohm property that can suppress collector electrode, base stage, emitter during owing to assembling worsens.
In the 7th execution mode, as mentioned above, collector electrode Ohmic electrode 604 constituted to comprise have about 1nm thickness and contact the Si layer 604a that forms with the surface of collector layer 603, Al layer 604b with about 6nm thickness, with Pd layer 604c with about 30nm thickness, simultaneously, base ohmic electrode 607 constituted to comprise have about 1nm thickness and contact the Si layer 607a that forms with the surface of base layer 606, with Pd layer 607b with about 20nm thickness, and, emitter Ohmic electrode 610 constituted to comprise have about 1nm thickness and contact the Si layer 610a that forms with the surface of emitter layer 609, Al layer 610b and Pd layer 610c with about 6nm thickness with about 30nm thickness, thus, same with above-mentioned first execution mode, by respectively with collector layer 603, the Si layer 604a that the first type surface of base layer 606 and emitter layer 609 contacts, the effect of 607a and 610a, at collector electrode Ohmic electrode 604, during welding during assembling after base ohmic electrode 607 and emitter Ohmic electrode 610 forms, under the situation that applies about 250 ℃～about 350 ℃ heat, ohm property also is difficult to worsen.Thus, can suppress collector electrode Ohmic electrode 604 worsens because of heat with the ohm property of ohm property, base ohmic electrode 607 and the base layer 606 of collector layer 603 and the ohm property of emitter Ohmic electrode 610 and emitter layer 609.
In addition, other effect of the 7th execution mode and above-mentioned first execution mode are same.
Figure 61～Figure 64 is the sectional view of manufacturing process that is used to illustrate the bipolar transistor of the 7th execution mode shown in Figure 57.Next, the manufacturing process of the bipolar transistor of the 7th execution mode is described with reference to Figure 57～Figure 64.
At first, shown in Figure 61, use mocvd method, on sapphire substrate 601, growth successively: have about 500nm thickness unadulterated n type GaN substrate 602, have the n type collector layer 603 that constitutes by GaN of about 300nm thickness, In with about 200nm thickness and doped with Mg xGa 1-xThe p type base layer 606 that N (x=0.02) constitutes and have the n type emitter layer 609 that constitutes by GaN of about 300nm thickness.Then, use photoetching technique, in the regulation zone of emitter layer 609, form resist 612.
Then, shown in Figure 62, resist 612 as mask, is used the RIE method, the regulation zone of removing emitter layer 609.
Then, shown in Figure 63, use photoetching technique, in the regulation zone of base layer 606 and emitter layer 609, form resist 613.Afterwards, resist 613 as mask, is used the RIE method, remove the regulation zone of base layer 606.
After this, shown in Figure 64, use the electron beam evaporation plating method, on base layer 606, form the pad electrode 608 of base ohmic electrode 607 and Au layer formation with about 10nm thickness.In addition, under the situation that forms base ohmic electrode 607, form the Pd layer 607b that has the Si layer 607a (with reference to Figure 59) of about 1nm thickness and have about 20nm thickness successively.At this moment, Si layer 607a forms by the electron beam evaporation plating method, so form amorphous silicon.
Then, shown in Figure 57, use the electron beam evaporation plating method, in the collector layer 603 and the regulation zone on the emitter layer 609 of n type, form collector electrode Ohmic electrode 604 respectively and have pad electrode 605 and the emitter Ohmic electrode 610 that the Au layer of about 300nm thickness constitutes and the pad electrode 611 of Au layer formation with about 300nm thickness.In addition, under the situation that forms collector electrode Ohmic electrode 604, form Si layer 604a successively, have the Al layer 604b of about 6nm thickness and have the Pd layer 604c of about 30nm thickness with about 1nm thickness.In addition, under the situation that forms emitter Ohmic electrode 610, with the operation that forms above-mentioned collector electrode Ohmic electrode 604 similarly, form Si layer 610a successively, have the Al layer 610b of about 6nm thickness and have the Pd layer 610c of about 30nm thickness with about 1nm thickness.At this moment, Si layer 604a and 610a are because by the formation of electron beam evaporation plating method, so form amorphous silicon.
(the 8th execution mode)
Below, the 8th execution mode of the present invention is described.In addition, the nitride-based semiconductor device of the 8th execution mode has and the same structure of nitride-based semiconductor device shown in above-mentioned the 3rd execution mode.Therefore, the difference of main above-mentioned the 3rd execution mode of explanation and the 8th execution mode below.
Particularly, in the above-described 3rd embodiment, Si layer 209a, Al layer 209b and the Pd layer 209c of lamination constitute n side Ohmic electrode 209 by begin successively from n type coating layer 202 sides.Relative therewith, in the 8th execution mode, n side Ohmic electrode is made of Si layer, Pd layer (or Pt layer) and the Al layer from n type coating layer (the nitride-based semiconductor layer of n type) lamination successively.
That is, in the 8th execution mode, n side Ohmic electrode contains Pd layer (or Pt layer) between Si layer and Al layer (the first metal layer).
Below, with reference to accompanying drawing, the structure of the nitride-based semiconductor device of the 8th execution mode of the present invention is described.Figure 65 is the figure of structure of the nitride-based semiconductor device of expression the 8th execution mode of the present invention.
Shown in Figure 65, nitride-based semiconductor device has: sapphire substrate 801, n type coating layer 802, active layer 803, p type contact layer 805, p side Ohmic electrode 806, surface protection film 807, pad electrode 808, n side Ohmic electrode 809 and pad electrode 810.
N type coating layer 802 is by Al xGa 1-xN (x=0.07) constitutes, and has the thickness of about 400nm.Active layer 803 has by In xGa 1-xThe well layer that N (x=0.15) constitutes and by In xGa 1-xBarrier layer, well layer and barrier layer alternative stacked that N (x=0.02) constitutes.In addition, the well layer has the thickness of 3nm, and the barrier layer has the thickness of 20nm.
P type coating layer 805 is by Al xGa 1-xN (x=0.07) constitutes, and has the thickness of 400nm.In addition, in p type coating layer 805, be doped with Mg as dopant material.In addition, at p type coating layer 805 superimposed layers the p type contact layer (not shown) of Mg as dopant material that mixed arranged.
P side Ohmic electrode 806 shown in Figure 66, has Si layer 806a, Pd layer 806b and Au layer 806c.Si layer 806a, Pd layer 806b and Au layer 806c begin lamination successively from p type contact layer 805.In addition, Si layer 806a has the thickness of 1nm, and Pd layer 806b has the thickness of 30nm, and Au layer 806c has the thickness of 300nm.
In addition, Si layer 806a as mentioned above, preferably is made of amorphous silicon.In addition, p side Ohmic electrode 806 also replaces Pd layer 806b can have the Pt layer.
Surface protection film 807 is by SiO 2Constitute, be configured to cover n type coating layer 802 and p side Ohmic electrode 806.
Pad electrode 808 for example is made of Si, Ti and Au, and Si, Ti and Au begin lamination successively from p side Ohmic electrode 806.In addition, Si has the thickness of 3nm, and Ti has the thickness of 200nm, and Au has the thickness of 300nm.
N side Ohmic electrode 809 shown in Figure 67, has Si layer 809a, Pd layer 809b and Al layer 809c.Si layer 809a, Pd layer 809b and Al layer 809c begin lamination successively from n type coating layer 802.In addition, Si layer 809a has the thickness of 3nm, and Pd layer 809b has the thickness of 2nm, and Al layer 809c has the thickness of 6nm.
In addition, Si layer 809a as mentioned above, preferably is made of amorphous silicon.In addition, n side Ohmic electrode 809 also can have the Pt layer and replaces Pd layer 809b.
Pad electrode 810 for example is made of Si, Ti and Au, and Si, Ti and Au begin lamination successively from n side Ohmic electrode 809.In addition, Si has the thickness of 3nm, and Ti has the thickness of 200nm, and Au has the thickness of 300nm.
In addition, the manufacturing process of the nitride-based semiconductor device of the 8th execution mode and above-mentioned the 3rd execution mode are same, so omit explanation.
(the 9th execution mode)
Below, the 9th execution mode of the present invention is described.In addition, the nitride-based semiconductor device of the 9th execution mode has and the same structure of nitride-based semiconductor device shown in the second above-mentioned execution mode.Therefore, second execution mode that main explanation below is above-mentioned and the difference of the 9th execution mode.
Particularly, in the second above-mentioned execution mode, Si layer 9a, Al layer 9b and the Pd layer 9c of lamination constitute n side Ohmic electrode 9 by begin successively from n type GaN substrate 1.Relative therewith, in the 9th execution mode, Si layer, Pd layer (or Pt layer) and the Al layer of lamination constitute n side Ohmic electrode by begin successively from n type coating layer (the nitride-based semiconductor layer of n type).
That is, in the 9th execution mode, n side Ohmic electrode contains Pd layer (or Pt layer) between Si layer and Al layer (the first metal layer).
Below, with reference to accompanying drawing, the structure of the nitride-based semiconductor device of the 9th execution mode of the present invention is described.Figure 68 is the figure of structure of the nitride-based semiconductor device of expression the 9th execution mode of the present invention.
Shown in Figure 68, nitride-based semiconductor device has: n type GaN substrate 901, n type coating layer 902, active layer 903, p type coating layer 904, p type contact layer 905, p side Ohmic electrode 906, current barrier layer 907, pad electrode 908, n side Ohmic electrode 909 and pad electrode 910.
N type coating layer 902 is by Al xGa 1-xN (x=0.07) constitutes, and has 400nm thickness.Active layer 903 has by In xGa 1-xThe well layer that N (x=0.15) constitutes and by In xGa 1-xBarrier layer, well layer and barrier layer alternative stacked that N (x=0.02) constitutes.In addition, the well layer has the thickness of 3nm, and the barrier layer has the thickness of 20nm.
P type coating layer 904 is by Al xGa 1-xN (x=0.07) constitutes, and has the thickness of 400nm.In addition, in p type coating layer 904, be doped with Mg as dopant material.
P type contact layer 905 is by In xGa 1-xN (x=0.02) constitutes, and has the thickness of 10nm.In addition, in p type contact layer 905, be doped with Mg as dopant material.
P side Ohmic electrode 906 shown in Figure 69, has Si layer 906a, Pd layer 906b and Au layer 906c.Si layer 906a, pd layer 906b and Au layer 906c begin lamination successively from p type contact layer 905.In addition, Si layer 906a has the thickness of 1nm, and Pd layer 906b has the thickness of 30nm, and Au layer 906c has the thickness of 300nm.
In addition, Si layer 906a as mentioned above, preferably is made of amorphous silicon.In addition, p side Ohmic electrode 906 also can have the Pt layer and replaces Pd layer 906b.
Current barrier layer 907 is by SiO 2Constitute, have the thickness of 300nm.In addition, current barrier layer 907 is arranged on the p type coating layer 904.
Pad electrode 908 for example is made of Si, Ti and Au, and Si, Ti and Au begin lamination successively from p side Ohmic electrode 906.In addition, Si has the thickness of 3nm, and Ti has the thickness of 200nm, and Au has the thickness of 300nm.
N side Ohmic electrode 909 shown in Figure 70, has Si layer 909a, Pd layer 909b and Al layer 909c.Si layer 909a, Pd layer 909b and Al layer 909c begin lamination successively from n type GaN substrate 901.In addition, Si layer 909a has the thickness of 3nm, and Pd layer 909b has the thickness of 2nm, and Al layer 909c has the thickness of 6nm.
In addition, Si layer 909a as mentioned above, preferably is made of amorphous silicon.In addition, n side Ohmic electrode 909 also can have the Pt layer and replaces Pd layer 909b.
Pad electrode 910 for example is made of Si, Ti and Au, and Si, Ti and Au begin lamination successively from n side Ohmic electrode 909.In addition, Si has the thickness of 3nm, and Ti has the thickness of 200nm, and Au has the thickness of 300nm.
In addition, the manufacturing process of the nitride-based semiconductor device of the 9th execution mode and above-mentioned second execution mode are same, so omit its explanation.
Below, illustrate for the effect of the n side Ohmic electrode of the nitride-based semiconductor device of confirming the 8th execution mode and the 9th execution mode and the experiment of carrying out.
The sample and the confirmation method of the effect that is used to confirm n side Ohmic electrode at first, are described.Figure 71 is used to illustrate the sample of the effect of confirming n side Ohmic electrode and the figure of confirmation method.
Shown in Figure 71, on n type GaN substrate 21, sky is opened the interval of regulation, utilizes vacuum vapour deposition, forms n side Ohmic electrode 24.
In addition, as the sample of n side Ohmic electrode 24, make following 4 kinds of samples.Particularly, as the sample of the n side Ohmic electrode of the 8th execution mode of the present invention and the 9th execution mode, form from n type GaN substrate 21 and begin the sample (hereinafter referred to as Si/Pd/Al (3/2/6nm) sample) of lamination SI layer (3nm), Pd (2nm) layer and Al layer (6nm) successively and begin the sample (hereinafter referred to as Si/Pt/Al (3/2/6nm) sample) of lamination SI layer (3nm) successively, Pt (2nm) layer and Al layer (6nm) from n type GaN substrate 21.On the other hand, the sample of n side Ohmic electrode as a comparative example forms from n type GaN substrate 21 and begins the sample (hereinafter referred to as Al/Pd (6/10nm) sample) of lamination Al layer (6nm) and Pd (10nm) layer successively and begin the sample (hereinafter referred to as Al/Pt (6/10nm) sample) of lamination Al layer (6nm) successively and Pt (10nm) layer from n type GaN substrate 21.
At first, the result who makes mensuration pin 25 and n side Ohmic electrode 24 contact, measure I-E characteristic (I-V characteristic) is described.Figure 72 is the figure of I-E characteristic (I-V characteristic) of each sample of this experiment of expression.Characteristic after Figure 72 represents just with the characteristic after n side Ohmic electrode 24 evaporations are on n type GaN substrate 21 with in blanket of nitrogen n side Ohmic electrode 24 to be applied heat treatment.
Shown in Figure 72 (a) and Figure 72 (b), Si/Pd/Al (3/2/6nm) sample and Si/Pt/Al (3/2/6nm) sample, even apply 350 ℃ the heat that equates with the temperature of the heat treatment of in assembling procedure, carrying out (little chip bonding (die bond)), also almost can't see the deterioration of I-V characteristic.
Relative therewith, shown in Figure 72 (c) and Figure 72 (d), Al/Pd (6/10nm) sample and Al/Pt (6/10nm) sample when applying hot about 300 ℃, are confirmed I-V characteristic rapid deterioration.
Then, with with after n side Ohmic electrode 24 evaporations are on n type GaN substrate 21, do not apply the resistance value of heat treated state (as depo. state) as benchmark, carry out standardization, measure owing to the variation ratio that n side Ohmic electrode 24 is applied the resistance value that heat treatment changes.Figure 73 is the figure of variation ratio of resistance value of each sample of this experiment of expression.
Shown in Figure 73, in Si/Pd/Al (3/2/6nm) sample and Si/Pt/Al (3/2/6nm) sample,, also almost can't see the variation of resistance value even each sample is applied heat treatment.Relative therewith, in Al/Pd (6/10nm) sample and Al/Pt (6/10nm) sample, when applying hot about 300 ℃, confirm the resistance value rapid deterioration.
Can clearly confirm from the experimental result shown in Figure 72 and Figure 73: according to the n side Ohmic electrode of Si layer, Pd layer (or Pt layer) and Al layer lamination successively, promptly between Si layer and Al layer (the first metal layer), be provided with the n side Ohmic electrode of Pd layer (or Pt layer), can suppress ohm property and descend because of the heat treatment of carrying out in the assembling procedure.
At last, make Si layer, Pd layer (or Pt layer) the 2 kind samples different, measure the variation ratio of the resistance value of each sample with the thickness of Al layer.Figure 74 is the figure of variation ratio of resistance value of each sample of this experiment of expression.
In this experiment, as the sample of n side Ohmic electrode 23, the thickness that the thickness of making Si layer, Pd layer (or Pt layer) and Al layer is respectively the sample (hereinafter referred to as 1/1/60 sample) of 1nm, 1nm and 60nm and Si layer, Pd layer (or Pt layer) and Al layer is respectively the sample (hereinafter referred to as 30/20/60 sample) of 30nm, 20nm and 60nm.
Shown in Figure 74, when making the varied in thickness of Si layer, Pd layer (or Pt layer), confirm that the variation ratio of resistance value changes because of heat treatment.That is, the variation ratio of affirmation resistance value has the character of the thickness that depends on Si layer, Pd layer (or Pt layer).
(other execution mode)
Current disclosed execution mode all should be thought illustration in all respects, and unrestricted.Scope of the present invention is not by the explanation of above-mentioned execution mode but represented by the scope of claim, and, comprise and the implication of the scope equalization of claim and all changes in the scope.
For example, in above-mentioned first～the 7th execution mode, illustrated that the nitride-based semiconductor device of the present invention that will possess the Ohmic electrode that forms on the nitride-based semiconductor layer is applied to nitride-based semiconductor laser device, example in nitride-based semiconductor light-emitting diode and the bipolar transistor, but the invention is not restricted to this, also the nitride-based semiconductor device that possesses the Ohmic electrode that forms on the nitride-based semiconductor layer can be applied to nitride-based semiconductor laser device, in the nitride-based semiconductor device beyond nitride-based semiconductor light-emitting diode and the bipolar transistor.
In addition, in the above-described 5th embodiment, illustrated that Pt (Pd) layer that will contact with p type contact layer is forming island and forming the example of Si layer in the mode that contacts with the part of not formation Pt (Pd) layer on the p type contact layer on the p type contact layer, but the invention is not restricted to this, also can on the p type contact layer Pt (Pd) layer formed stratiform, on the Pt of this stratiform (Pd) layer, form the Si layer.

Claims (12)

1. nitride-based semiconductor device is characterized in that:
Possess: nitride-based semiconductor layer with first type surface; With the Ohmic electrode that on the first type surface of described nitride-based semiconductor layer, forms,
Described Ohmic electrode comprises: contact the silicon layer that forms with the first type surface of described nitride-based semiconductor layer; With the first metal layer that on described silicon layer, forms.
2. nitride-based semiconductor device according to claim 1 is characterized in that:
Described the first metal layer comprise can with the metal of described nitride-based semiconductor layer ohmic contact.
3. nitride-based semiconductor device according to claim 1 is characterized in that:
Described Ohmic electrode forms on the described nitride-based semiconductor layer of p type,
Described the first metal layer comprises at least one side among Pd and the Pt.
4. nitride-based semiconductor device according to claim 1 is characterized in that:
Described Ohmic electrode forms on the described nitride-based semiconductor layer of n type,
Described Ohmic electrode also comprises the Al layer that is configured between described silicon layer and the described the first metal layer.
5. nitride-based semiconductor device according to claim 1 is characterized in that:
Described Ohmic electrode forms on the described nitride-based semiconductor layer of n type,
Described Ohmic electrode comprises the either party in Pd layer and the Pt layer at least between described silicon layer and described the first metal layer.
6. nitride-based semiconductor device according to claim 1 is characterized in that:
Described silicon layer is made of amorphous silicon.
7. nitride-based semiconductor device according to claim 1 is characterized in that:
Also possesses second metal level that on described Ohmic electrode, forms.
8. nitride-based semiconductor device according to claim 1 is characterized in that:
Described silicon layer has the following thickness of the above 30nm of 0.5nm.
9. nitride-based semiconductor device is characterized in that:
Possess: the nitride-based semiconductor layer of p type; With the Ohmic electrode that on the nitride-based semiconductor layer of described p type, forms,
Described Ohmic electrode comprises: the silicon layer that forms on the nitride-based semiconductor layer of described p type; With the first metal layer that on described silicon layer, forms.
10. nitride-based semiconductor device according to claim 9 is characterized in that:
Between the nitride-based semiconductor layer and described silicon layer of described p type, be provided with can with the ohmic metal layer of the nitride-based semiconductor layer ohmic contact of described p type.
11. a nitride-based semiconductor device is characterized in that:
Possess: the nitride-based semiconductor layer of n type; With the Ohmic electrode that on the nitride-based semiconductor layer of described n type, forms,
Described Ohmic electrode comprises: the silicon layer that forms on the nitride-based semiconductor layer of described n type; With the first metal layer that on described silicon layer, forms,
Described the first metal layer comprise can with the material of the nitride-based semiconductor layer ohmic contact of described n type,
Described Ohmic electrode comprises the either party in Pd layer and the Pt layer at least between described silicon layer and described the first metal layer.
12. nitride-based semiconductor device according to claim 11 is characterized in that:
Described silicon layer is made of amorphous silicon.
CN 200610095956 2005-06-29 2006-06-29 Nitride semiconductor device Pending CN1893110A (en)

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