CN1892739A - Plasma display apparatus and method of driving the same - Google Patents

Abstract

A plasma display apparatus and a method of driving the plasma display apparatus are disclosed. The plasma display apparatus includes a plasma display panel including a scan electrode, a sustain voltage source, an inductor, an energy supply/recovery capacitor, and a maintenance capacitor. The inductor and the energy supply/recovery capacitor form a current path for supplying/recovering a sustain voltage to/from the plasma display panel, and for forming a current path for supplying/recovering one half of the sustain voltage to/from the plasma display panel. The maintenance capacitor forms a current path for maintaining a voltage of the plasma display panel at one half of the sustain voltage.

Description

Plasma display panel device and driving method thereof

Technical field

Presents relates to display device, and more specifically says, relates to plasma display panel device.

Background technology

Usually, our display device, plasma display panel device comprise Plasmia indicating panel and the driver that is used to drive Plasmia indicating panel.

Cathode-ray tube (CRT) exists heavy and bulky problem.Therefore, developed multiple flat panel display equipment.The example of flat panel display equipment comprises LCD (LCD), field-emitter display (FED), Plasmia indicating panel (PDP) and electroluminescence (EL) display device.This PDP using gases discharge, and have the advantage that is fabricated to large size panel easily.Recently, most of PDP have the three-electrode surface discharge type structure, wherein form scan electrode and keep electrode and form addressing electrode on meron on preceding substrate.

Drive three-electrode surface discharge type PDP by frame being divided into several height field.The proportional emission number of weighted value of generation and video data in each son field, thereby display image.Each son field comprises reset cycle, addressing period and keeps the cycle.

In the reset cycle, in discharge cell, evenly form the wall electric charge.In addressing period, produce selectivity address discharge according to the logical value of video data.In the cycle of keeping, in the discharge cell of selecting by the address discharge that produces, keep discharge.

In the three-electrode surface discharge type PDP that drives like this, when producing address discharge and keeping discharge, need the high pressure of several hectovolts.Therefore, apparatus for energy recovery is used among the three-electrode surface discharge type PDP to be reduced in driving voltage required when producing address discharge and keeping discharge.

Fig. 1 is the circuit diagram of apparatus for energy recovery of the plasma display panel device of prior art.

With reference to figure 1, has symmetrical structure at panel capacitor Cp two ends by the apparatus for energy recovery of the plasma display panel device of U.S. Patent No. 5,081, the 400 disclosed prior aries of Weber.

In Fig. 1, only be illustrated in the apparatus for energy recovery of installing among the scan electrode Y of PDP.The scan electrode Y that panel capacitor Cp indicates equivalently at PDP and keep the electric capacity that forms between the electrode Z.

The apparatus for energy recovery 2 of prior art plasma display panel device energy recovery/provide unit 4 is provided and keeps pulse provides unit 6.

Energy recovery/provide unit 4 during the cycle of keeping, to reclaim the quadergy of the PDP of the discharge that does not participate in PDP, and provide the energy of recovery to arrive panel capacitor Cp.

Energy recovery/provide unit 4 to comprise is used to store the capacitor Cs of the energy of recovery, inductor L, first switch SW 1 and the first diode D1.Inductor L is connected capacitor Cs and provides between the Section Point N2 of the common port that control module 8 and ground voltage provide control module 10 as keeping voltage.First switch SW 1 and the first diode D1 are connected in series between capacitor Cs and the inductor L, to be formed for being provided at the current path that the energy of storing among the capacitor Cs arrives panel capacitor Cp.

Energy recovery/provide unit 4 to comprise second switch SW2, the second diode D2, the 3rd diode D3 and the 4th diode D4.The second switch SW2 and the second diode D2 are connected in series between capacitor Cs and the first node N1 as the common port of the first diode D1 and inductor L, to be formed for reclaiming from panel capacitor Cp the current path of quadergy.The 3rd diode D3 and the 4th diode D4 are connected in series in and keep between voltage source (not shown) and the ground voltage source (not shown).

Capacitor Cs is recovered in the energy of storing among the panel capacitor Cp when discharge is kept in generation.Capacitor Cs is provided among the capacitor Cs stored voltage once more to panel capacitor Cp afterwards.

To be charged to capacitor Cs as half the voltage Vs/2 that keeps voltage Vs.Inductor L has fixed inductance value.Inductor L and panel capacitor Cp form resonant circuit.

For this reason, first to the 4th switch SW 1 flows to the SW4 Control current.Be formed for the internal body diodes that Control current flows in first to the 4th switch SW 1 to SW4.

When the voltage that is charged to capacitor Cs was provided to panel capacitor Cp, the first diode D1 prevented the inverse current from panel capacitor Cp.When capacitor Cs was recovered in the energy of storing among the panel capacitor Cp, the second diode D2 prevented the negative-phase sequence curent from capacitor Cs.

The 3rd diode D3 prevents from keeping the inverse current that voltage source flows to first node N1.The 4th diode D4 prevents to flow to from first node N1 the inverse current in ground voltage source.

Keep pulse provide unit 6 during the cycle of keeping, to provide to have keep voltage Vs and ground voltage level GND keep the scan electrode Y of pulse to PDP.Keeping pulse provides unit 6 to comprise to keep voltage and provides unit 8 and ground voltage that unit 10 is provided.

Keep to provide during voltage provides the cycle of setting up that unit 8 is controlled at the reset cycle and keeps the cycle and keep the scan electrode Y of voltage Vs to PDP.Keeping voltage provides unit 8 to comprise to be connected the 3rd switch SW of keeping between voltage source and the Section Point N2 3.

Ground voltage provides ground voltage level GND scan electrode Y to PDP during providing unit 10 to be controlled at the cycle of keeping.Ground voltage provides unit 10 to comprise to be connected the 4th switch SW 4 between ground voltage source and the Section Point N2.

Fig. 2 has illustrated the output waveform of panel capacitor of the apparatus for energy recovery of the ON/OFF sequential of switch of apparatus for energy recovery of Fig. 1 and Fig. 1.

With reference to figure 2, supposed before cycle t1, the voltage of storage 0V in panel capacitor Cp, and in capacitor Cs storage as half the voltage Vs/2 that keeps voltage Vs.

During cycle t1, connect first switch SW 1, make to form the current path that passes through capacitor Cs, first switch SW 1, the first diode D1, inductor L and panel capacitor Cp, and inductor L and panel capacitor Cp generation series resonance.The voltage Vp of panel capacitor Cp and electric current I Cp are by equation 1 expression.

[equation 1]

$V_p\left(t\right)=\frac{V_s}{2}(1-e^{-{\mathrm{sw}}_{n}t}{\cos w}_{d}t-\frac{{\mathrm{se}}^{{-\mathrm{sw}}_{n}t}}{\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2}}{\sin w}_{d}t)$

${\mathrm{IC}}_p\left(t\right)=\frac{V_s{e}^{{\mathrm{<figure-callout\; id="2"\; label="sw\; n\; t"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">sw</figure-callout>}}_{n}t}}{{2\mathrm{Lw}}_d}{\sin w}_{d}t$

Here, $w_n=1/\sqrt{{\mathrm{LC}}_p},s=R_{\mathrm{eq}}\sqrt{C_p/L},w_d=w_n\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2},$ R _EqBe illustrated in the total dead resistance that forms in the current path.

As a result, the voltage Vp of panel capacitor Cp rises to from ground voltage level GND in cycle t1 and keeps voltage Vs.The electric current I L that flows in inductor L rises to

And drop to 0 afterwards.

During cycle t2, connect first switch SW 1 and the 3rd switch SW 3, make to form by first current path of capacitor Cs, first switch SW 1, the first diode D1, inductor L and Section Point N2 with by keeping second current path of voltage source, the 3rd switch SW 3 and panel capacitor Cp.

As a result, the voltage of panel capacitor Cp is maintained at keeps voltage Vs, and gas-discharge current Igas is in the PDP internal flow.In cycle t2, the capacitor parasitics on inductor L and the current path produces spurious resonance, and making flows in inductor L has the inverse current of predetermined peak value Ir.The inverse current that flows in inductor L flows among inductor L and the 4th diode D4 in the 3rd switch SW 3.The amplitude of inverse current is by equation 2 expressions.

[equation 2]

$I_L\left(t\right)=-I_r+\frac{V_f}{L}t$

Here, V _jIndicate the forward voltage of the 4th diode D4 and have the voltage of about 0.7V.

Inverse current continuous flow in inductor L is 0 up to inverse current.This inverse current is called as freewheeling (freewheeling) electric current.This freewheeling electric current increases the current stress of the 3rd switch SW 3 and the 4th diode D4.

During cycle t3, disconnect first switch SW 1, make to form by keeping the current path of voltage source, the 3rd switch SW 3 and panel capacitor Cp.As a result, the voltage of panel capacitor Cp remains on and keeps voltage Vs.

During cycle t4, disconnect the 3rd switch SW 3 and connect second switch SW2, make and form by panel capacitor Cp inductor L, the second diode D2, the current path of second switch SW2 and capacitor Cs, and inductor L and panel capacitor Cp generation series resonance.The voltage Vp of panel capacitor Cp and electric current I Cp are by equation 3 expressions.

[equation 3]

$V_p\left(t\right)=\frac{V_s}{2}(1+e^{-{\mathrm{sw}}_{n}t}{\cos w}_{d}t+\frac{{\mathrm{se}}^{{-\mathrm{sw}}_{n}t}}{\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2}}{\sin w}_{d}t)$

${\mathrm{IC}}_p\left(t\right)=-\frac{V_s{e}^{{\mathrm{<figure-callout\; id="2"\; label="sw\; n\; t"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">sw</figure-callout>}}_{n}t}}{{2\mathrm{Lw}}_d}{\sin w}_{d}t$

As a result, the voltage Vp of panel capacitor Cp drops to ground voltage level GND from keeping voltage Vs in cycle t4.The electric current I L that flows in inductor L drops to

And rise to 0 afterwards.

In cycle t5, connect the 4th switch SW 4, and connect second switch SW2 afterwards.As a result, the voltage of panel capacitance Cp maintains ground voltage level GND.

Because stored voltage Vp drops to ground voltage level GND fast from keeping voltage Vs in panel capacitance Cp, undesired inductive current Ir flows in the 4th switch SW 4, inductor L and the 4th diode D4.The inverse current that flows in inductor L is by equation 4 expressions.

[equation 4]

$I_L\left(t\right)=I_r-\frac{V_f}{L}t$

This inverse current continues to flow in inductance L, is 0 up to inverse current.This inverse current is called as the freewheeling electric current.This freewheeling electric current increases the current stress of the 3rd switch SW 3 and the 4th diode D4.

As mentioned above, when rechargeable energy in the apparatus for energy recovery at plasma display panel device during to panel capacitance Cp or from panel capacitance Cp discharge energy, this freewheeling electric current causes very large current stress on the driving element of apparatus for energy recovery.Therefore, need to improve the tolerance condition (withstanding condition) of driving element.

In other words, because the apparatus for energy recovery of prior art plasma display panel device uses the driving element with extraordinary tolerance condition, thereby manufacturing cost increases.In addition, undesired freewheeling electric current has increased power consumption.

In addition, because use the series resonance of inductor L and panel capacitor Cp, be difficult to realize soft switching manipulation fully by the parasitic elements of circuit.Because do not control duration of charging and the discharge time of PDP, be difficult to guarantee simultaneously good flash-over characteristic and high organic efficiency.

Summary of the invention

Therefore, the objective of the invention is to solve at least prior art problems and shortcoming.

Embodiments of the invention provide a kind of plasma display panel device that can reduce manufacturing cost and improve energy recovery efficiency.

Embodiments of the invention also provide a kind of plasma display panel device that can reduce power consumption by the minimizing dead resistance.

According to an aspect, a kind of plasma display panel device is provided, it comprises: Plasmia indicating panel, it comprises scan electrode; Keep voltage source, it is used to provide keeps voltage to Plasmia indicating panel; Inductor, it is used for resonance by inductor and Plasmia indicating panel and is recovered in the Plasmia indicating panel stored voltage and is used for providing the voltage of recovery to Plasmia indicating panel by the resonance of inductor and Plasmia indicating panel; Energy provides/reclaims capacitor, it is used to form to be used to provide keeps voltage to Plasmia indicating panel/reclaim from the Plasmia indicating panel current path keep voltage, with be used to form be used to provide keep voltage half to Plasmia indicating panel/reclaim its current path from Plasmia indicating panel, inductor is used to form current path; And keep capacitor, it forms keeping between voltage source and the Plasmia indicating panel, is used to form the voltage of keeping Plasmia indicating panel and is keeping half current path of voltage.

According on the other hand, a kind of plasma display panel device is provided, it comprises: Plasmia indicating panel, it comprises scan electrode; First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source; Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode; Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode; The 3rd capacitor, it is connected keeps voltage and provides control module and ground voltage to provide between the control module; Energy provides control module, and it is connected between the common port and scan electrode of first capacitor and second capacitor, is used for controlling being provided at energy that second capacitor stores to scan electrode; Energy recovery control module, itself and energy provide control module to be connected in parallel, and are connected between the common port and scan electrode of first capacitor and second capacitor, and being used to control provides the energy that reclaims from the scan electrode of Plasmia indicating panel to second capacitor; With first inductor, it is connected energy and provides between the common port and scan electrode of control module and energy recovery control module.

According to another aspect, a kind of plasma display panel device is provided, it comprises: Plasmia indicating panel, it comprises scan electrode; First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source; Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode; Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode; The 3rd capacitor and the 4th capacitor, it is connected in series in keeps voltage and provides control module and ground voltage to provide between the control module; First inductor, it is connected between the common port of the common port of first capacitor and second capacitor and the 3rd capacitor and the 4th capacitor; The first energy recovery control module and second energy provide control module, and it is connected in parallel between the common port and first inductor of first capacitor and second capacitor; Second inductor, it is connected between the common port and scan electrode of the 3rd capacitor and the 4th capacitor; Provide the control module and the second energy recovery control module with first energy, it is connected in parallel between first inductor and second inductor.

According to another aspect, a kind of plasma display panel device is provided, it comprises: Plasmia indicating panel, it comprises scan electrode; First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source; Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode; Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode; The 3rd capacitor and the 4th capacitor, it is connected in series in keeps voltage and provides control module and ground voltage to provide between the control module; First energy provides the control module and the first energy recovery control module, and it is connected in parallel between the common port of the common port of first capacitor and second capacitor and the 3rd capacitor and the 4th capacitor; Provide the control module and the second energy recovery control module with second energy, it is connected in parallel between the common port and scan electrode of the 3rd capacitor and the 4th capacitor.

According to more on the one hand, a kind of method that drives plasma display panel device is provided, it comprises: the voltage of the scan electrode of Plasmia indicating panel is increased to half that keep voltage from ground voltage level; The voltage of keeping scan electrode is being kept half of voltage; The voltage of scan electrode is increased to from half that keep voltage keeps voltage; Keep the voltage of scan electrode and keeping the unit; The voltage of scan electrode is reduced to half that keep voltage from keeping voltage; With the voltage of scan electrode is reduced to ground voltage level from half that keep voltage.

Description of drawings

To represent that the accompanying drawing of similar elements describes the present invention in detail with reference to same numbers wherein.

Fig. 1 is the circuit diagram of apparatus for energy recovery of the plasma display panel device of prior art;

Fig. 2 has illustrated the output waveform of panel capacitor of the apparatus for energy recovery of the ON/OFF sequential of switch of apparatus for energy recovery of Fig. 1 and Fig. 1;

Fig. 3 is the skeleton view according to the Plasmia indicating panel of the plasma display panel device of first embodiment of the invention;

Fig. 4 is the circuit diagram according to the plasma display panel device of first embodiment of the invention;

Fig. 5 is the sequential chart according to the switch of the plasma display panel device of first embodiment of the invention;

Fig. 6 to 11 is the circuit diagrams according to the current path of the on/off switch operation formation of the switch of Fig. 5;

Figure 12 is the circuit diagram according to the plasma display panel device of second embodiment of the invention;

Figure 13 is the sequential chart according to the switch of the plasma display panel device of second embodiment of the invention;

Figure 14 to 21 is the circuit diagrams according to the current path of the on/off switch operation formation of the switch of Figure 13;

Figure 22 is the circuit diagram according to the plasma display panel device of third embodiment of the invention;

Figure 23 is the sequential chart according to the switch of the plasma display panel device of third embodiment of the invention;

Figure 24 to 32 is the circuit diagrams according to the current path of the on/off switch operation formation of the switch of Figure 23;

Embodiment

In more detailed mode the preferred embodiments of the present invention are described below with reference to the accompanying drawings.

Plasma display panel device according to the embodiment of the invention comprises: Plasmia indicating panel, and it comprises scan electrode; Keep voltage source, it is used to provide keeps voltage to Plasmia indicating panel; Inductor, it is used for resonance by inductor and Plasmia indicating panel and is recovered in the Plasmia indicating panel stored voltage and is used for providing the voltage of recovery to Plasmia indicating panel by the resonance of inductor and Plasmia indicating panel; Energy provides/reclaims capacitor, it is used to form to be used to provide keeps voltage to Plasmia indicating panel/reclaim from the Plasmia indicating panel current path keep voltage, with be used to form be used to provide keep voltage half to Plasmia indicating panel/reclaim its current path from Plasmia indicating panel, inductor is used to form current path; With keep capacitor, it forms keeping between voltage source and the Plasmia indicating panel, is used to form the voltage of keeping Plasmia indicating panel and is keeping half current path of voltage.

Energy provides/reclaims capacitor can comprise second capacitor and the 4th capacitor, second capacitor can be formed for providing keeps voltage to Plasmia indicating panel/reclaim the current path keep voltage from Plasmia indicating panel, and the 4th capacitor can be formed for providing keep voltage half to its current path of Plasmia indicating panel/reclaim from Plasmia indicating panel.

Energy provides/reclaims capacitor to comprise the 3rd capacitor, may be the 3rd capacitor and be used to form the voltage of keeping Plasmia indicating panel at half the capacitor of keeping of current path of keeping voltage.

This inductor comprises first inductor and second inductor, first inductor and second capacitor are formed for providing keeps voltage to Plasmia indicating panel/reclaim its current path from Plasmia indicating panel, and second inductor and the 4th capacitor can be formed for providing keep voltage half to its current path of Plasmia indicating panel/reclaim from Plasmia indicating panel.

Inductor can comprise first inductor, second inductor, the 3rd inductor and the 4th inductor, first inductor and second capacitor are formed for providing keeps the current path of voltage to Plasmia indicating panel, second inductor and the 4th capacitor can form from Plasmia indicating panel and reclaim half the current path keep voltage, the 3rd inductor and second capacitor can form from Plasmia indicating panel and reclaim the current path keep voltage, and the 4th inductor and the 4th capacitor are formed for providing half current path to Plasmia indicating panel of keeping voltage.

Provide keep voltage to the current path of Plasmia indicating panel may with provide half that keep voltage identical to the current path of Plasmia indicating panel, and be used for reclaiming the current path of keeping voltage from Plasmia indicating panel may be with reclaim half the current path of keeping voltage from Plasmia indicating panel identical.

This energy provides/reclaims capacitor can comprise the 3rd capacitor, and to be used to form the voltage of keeping Plasmia indicating panel be the 3rd capacitor at half the capacitor of keeping of current path of keeping voltage.

Plasma display panel device according to the embodiment of the invention comprises: Plasmia indicating panel, and it comprises scan electrode; First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source; Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode; Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode; The 3rd capacitor, it is connected keeps voltage and provides control module and ground voltage to provide between the control module; Energy provides control module, and it is connected between the common port and scan electrode of first capacitor and second capacitor, is used for controlling being provided at energy that second capacitor stores to scan electrode; Energy recovery control module, itself and energy provide between the common port and scan electrode that control module is connected in first capacitor and second capacitor in parallel, and being used to control provides the energy that reclaims from the scan electrode of Plasmia indicating panel to second capacitor; With first inductor, it is connected energy and provides between the common port and scan electrode of control module and energy recovery control module.

Keeping voltage provides control module can comprise first switch and the 3rd switch, it is connected in series in keeps between voltage source and the scan electrode, and ground voltage provides control module can comprise second switch and the 4th switch, and it is connected in series between ground voltage source and the scan electrode.

The 3rd capacitor is connected between the common port of the common port of first switch and the 3rd switch and second switch and the 4th switch.

Energy provides control module to comprise and is connected the common port of first capacitor and second capacitor and the 5th switch between the inductor.

The energy recovery control module comprises the common port that is connected first capacitor and second capacitor and the 6th switch between the inductor.

Plasma display panel device according to the embodiment of the invention comprises: Plasmia indicating panel, and it comprises scan electrode; First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source; Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode; Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode; The 3rd capacitor and the 4th capacitor, it is connected in series in keeps voltage and provides control module and ground voltage to provide between the control module; First inductor, it is connected between the common port of the common port of first capacitor and second capacitor and the 3rd capacitor and the 4th capacitor; The first energy recovery control module and second energy provide control module, and it is connected in parallel between the common port and first inductor of first capacitor and second capacitor; Second inductor, it is connected between the common port and scan electrode of the 3rd capacitor and the 4th capacitor; Provide the control module and the second energy recovery control module with first energy, it is connected in parallel between first inductor and second inductor.

Keeping voltage provides control module can comprise first switch and second switch, and be connected in series in and keep between voltage source and the scan electrode, and this ground voltage provides control module can comprise the 3rd switch and the 4th switch, and it is connected in series between ground voltage source and the scan electrode.

First energy provides control module can comprise the 5th switch and first diode, and it is connected between first inductor and second inductor.

Second energy provides control module can comprise the 6th switch and second diode, and it is connected between the common port and first inductor of first capacitor and second capacitor.

The first energy recovery control module can comprise minion pass and the 3rd diode, and it is connected between the common port and first inductor of first capacitor and second capacitor.

The second energy recovery control module comprises octavo pass and the 4th diode, and it is connected between first inductor and second inductor.

The voltage that is charged to first capacitor equals to keep 50% of voltage, the voltage that is charged to second capacitor equals to keep 50% of voltage, the voltage that is charged to the 3rd capacitor equals to keep 25% of voltage, and the voltage that is charged to the 4th capacitor equals to keep 25% of voltage.

Plasma display panel device according to the embodiment of the invention comprises: Plasmia indicating panel, and it comprises scan electrode; First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source; Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode; Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode; The 3rd capacitor and the 4th capacitor, it is connected in series in keeps voltage and provides control module and ground voltage to provide between the control module; First energy provides the control module and the first energy recovery control module, and it is connected in parallel between the common port of the common port of first capacitor and second capacitor and the 3rd capacitor and the 4th capacitor; Provide the control module and the second energy recovery control module with second energy, it is connected in parallel between the common port and scan electrode of the 3rd capacitor and the 4th capacitor.

Keeping voltage provides control module to comprise to be connected first switch of keeping between voltage source and the 3rd capacitor, and be connected second switch between the 3rd capacitor and the scan electrode, and ground voltage provides control module to comprise to be connected the 3rd switch between ground voltage source and the 4th capacitor, and is connected the 4th switch between the 4th capacitor and the scan electrode.

Second energy provides control module to comprise to be connected the 5th switch between the common port of the common port of the 3rd capacitor and the 4th capacitor and first switch and second switch, and is connected the common port of first capacitor and second capacitor and first inductor between the 5th switch.

The first energy recovery control module comprises the 6th switch between the common port of the common port that is connected the 3rd switch and the 4th switch and first capacitor and second capacitor, and is connected the common port of the 3rd capacitor and the 4th capacitor and the 3rd inductor between the 6th switch.

The second energy recovery control module comprises second inductor between the common port of the common port that is connected first switch and second switch and second switch and scan electrode, and the common port and the minion between second inductor that are connected the 3rd capacitor and the 4th capacitor are closed.

First energy provides control module to comprise to be connected the octavo between the common port of the common port of the 3rd capacitor and the 4th capacitor and the 3rd switch and the 4th switch to close, and is connected the common port of the 3rd switch and scan electrode and octavo the 4th inductor between closing.

The voltage that is charged to first capacitor equals to keep 50% of voltage, the voltage that is charged to second capacitor equals to keep 50% of voltage, the voltage that is charged to the 3rd capacitor equals to keep 25% of voltage, and the voltage that is charged to the 4th capacitor equals to keep 25% of voltage.

Method according to the driving plasma display panel device of the embodiment of the invention comprises: the voltage of the scan electrode of Plasmia indicating panel is increased to half that keep voltage from ground voltage level; The voltage of keeping scan electrode is being kept half of voltage; The voltage of scan electrode is increased to from half that keep voltage keeps voltage; Keep the voltage of scan electrode and keeping the unit; The voltage of scan electrode is reduced to half that keep voltage from keeping voltage; With the voltage of scan electrode is reduced to ground voltage level from half that keep voltage.

Hereinafter, will be described in detail with reference to the attached drawings exemplary embodiment of the present invention.

Fig. 3 is the skeleton view according to the Plasmia indicating panel of the plasma display panel device of first embodiment of the invention.

With reference to figure 3, be included in the scan electrode Y that forms on the preceding substrate 10 of discharge cell and keep electrode Z according to the Plasmia indicating panel of the plasma display panel device of first embodiment of the invention, and the addressing electrode X that on the meron 18 of discharge cell, forms.

Each comprises transparency electrode 12Y and 12Z and bus electrode 13Y and 13Z to scan electrode Y with keeping electrode Z.Bus electrode 13Y and 13Z have the line width less than the line width of transparency electrode 12Y and 12Z (linewidth), and form on the lateral edges of transparency electrode 12Y and 12Z.

Transparency electrode 12Y and 12Z are made by transparent indium-tin-oxide (ITO) material, and form on preceding substrate 10.Bus electrode 13Y and 13Z are made by the metal material such as Cr, and form on transparency electrode 12Y and 12Z.Bus electrode 13Y and 13Z reduce the voltage drop that is caused by transparency electrode 12Y with high impedance and 12Z.

Form dielectric layer 14 and protective seam 16 at scan electrode Y on the electrode Z with keeping.The wall electric charge that produces in plasma discharge is accumulated on last dielectric layer 14.

Protective seam 16 prevents that dielectric layer 14 from being damaged by the sputter that produces (sputtering) in plasma discharge, and increases the electronic secondary radiation efficiency.Protective seam 16 is formed by Mg.

Dielectric layer 22 and barrier rib 24 under forming on the addressing electrode X.At the surface of following dielectric layer 22 and the surface-coated fluorescent material layer 25 of barrier rib 24.

Formation addressing electrode X is with cross scan electrode Y and keep electrode Z.Be parallel to the addressing electrode X-shaped and become barrier rib 24, prevent from thus to leak into neighboring discharge cells by the ultraviolet ray and the visible light of discharge generation.

By the ultraviolet ray excited luminescent coating 26 of discharge generation, any one of feasible generation redness, green and blue visible light.Upper and lower substrate 12 and 18 and barrier rib 24 between the discharge space that is provided with have inert gas.

Drive plasma display panel device by a frame being divided into several height field that its emitting times differs from one another according to the first embodiment of the present invention.Each son field comprises reset cycle, addressing period and keeps the cycle.

In the reset cycle, in discharge cell, evenly form the wall electric charge.In addressing period, produce selectivity address discharge based on the logical value of video data, in the cycle of keeping, in the discharge cell of selecting by the generation of address discharge, keep discharge.

In the plasma display panel device that drives like this, when producing address discharge and keeping discharge, need the high pressure of several hectovolts.

Therefore, use apparatus for energy recovery to reduce address discharge and to keep driving voltage required in the discharge.Apparatus for energy recovery is recovered in scan electrode Y and keeps voltage between the electrode Z, makes the voltage that the reclaims driving voltage as next discharge.

Fig. 4 is the circuit diagram according to the plasma display panel device of first embodiment of the invention.

With reference to figure 4, has symmetrical structure at panel capacitor Cp two ends according to the apparatus for energy recovery 52 of the plasma display panel device of first embodiment of the invention.

Panel capacitor Cp is illustrated in the scan electrode Y of PDP equivalently and keeps the electric capacity that forms between the electrode Z.Apparatus for energy recovery with structure identical with the structure of the apparatus for energy recovery of installing in the scan electrode Y of panel capacitor Cp 52 is installed in keeping among the electrode Z of panel electrical equipment Cp.

Comprise the first capacitor C1, the second capacitor C2 and keep voltage according to the apparatus for energy recovery 52 of the plasma display panel device of first embodiment of the invention control module 54 is provided.The first capacitor C1 and the second capacitor C2 are connected and keep between voltage source (not shown) and the ground voltage source (not shown).Keeping voltage provides control module 54 to be connected to keep between the scan electrode Y of the common port of the voltage source and first capacitor and panel capacitor Cp.Keeping voltage provides control module 54 control to provide to keep the scan electrode Y of voltage Vs to panel capacitor Cp.

Apparatus for energy recovery 52 comprises that further ground voltage provides control module 56, and energy provides control module 58 and energy recovery control module 60.Ground voltage provides between the scan electrode Y that control module 56 is connected ground voltage source and panel capacitor Cp.Ground voltage provides control module 56 controls that ground voltage level GND is provided the scan electrode Y to panel capacitor Cp.Energy provides between the scan electrode Y of common port that control module 58 and energy recovery control module 60 be connected in the first capacitor C1 and the second capacitor C2 in parallel and panel capacitor Cp.

Apparatus for energy recovery 52 further comprises the first inductor L1, the 3rd capacitor C3, the first diode D1 and the 4th diode D4.First inductance L 1 is connected energy and provides between the scan electrode Y of the common port of control module 58 and energy recovery control module 60 and panel capacitor Cp.The 3rd capacitor C3 is connected and keeps voltage and provide control module 54 and ground voltage to provide between the control module 56.The first diode D1 is connected between ground voltage source and the energy recovery control module 60.The 4th diode D4 is connected energy and control module 58 is provided and keeps between the voltage source.

The second capacitor C2 is that energy provides/reclaim capacitor, and the 3rd capacitor C3 keeps capacitor.

The first capacitor C1 is connected and keeps between the voltage source and the second capacitor C2, and dividing potential drop this keep voltage Vs.Will be as being charged to the first capacitor C1 from half the voltage Vs/2 of voltage Vs that keeps that keeps that voltage source provides.

Provide/reclaim the second capacitor C2 of capacitor to be connected between the first capacitor C1 and the ground voltage source as energy.The second capacitor C2 reclaims the quadergy of the discharge that does not participate in PDP from PDP, and the scan electrode Y of the energy of this recovery to panel capacitor Cp is provided once more.To be charged to the second capacitor C2 as keeping half voltage Vs/2 of voltage Vs.

Keeping voltage provides control module 54 to be connected to keep the common port of voltage source, the first capacitor C1 and the 4th diode D4, and between the scan electrode Y of panel capacitance Cp.Keeping voltage provides control module 54 control to provide from what keep that voltage source provides to keep the scan electrode Y of voltage Vs to panel capacitor Cp.

Keeping voltage provides control module 54 to comprise first switch SW 1 and the 3rd switch SW 3, and it is connected in series in keeps between voltage source and the panel capacitor Cp.

First switch SW 1 is connected to be kept between voltage source and the 3rd switch SW 3.First switch SW 1 is electrically connected to an end of keeping voltage source, the 3rd switch SW 3 and an end of the 3rd capacitor C 3 in response to first switch controlling signal that provides from the time schedule controller (not shown).

As a result, the voltage of panel capacitor Cp maintains voltage Vs/2 (just, keep voltage Vs half) and keeps voltage Vs.This will be discussed in more detail below.

The 3rd switch SW 3 is connected between the scan electrode Y of first switch SW 1 and panel capacitor Cp.In response to the 3rd switch controlling signal that provides from time schedule controller, what the switching manipulation of the 3rd switch SW 3 provided the end that is provided to first switch SW 1 keeps the scan electrode Y of voltage Vs to panel capacitor Cp.

Ground voltage provides between the scan electrode Y of common port that control module 56 is connected ground voltage source, the second capacitor C2 and the first diode D1 and panel capacitor Cp.The ground voltage level GND that ground voltage provides control module 56 control to provide to provide from the ground voltage source is to the scan electrode Y of panel capacitor Cp.Ground voltage provides control module 56 to comprise second switch SW2 and the 4th switch SW 4, and it is connected in series between the scan electrode Y of ground voltage source and panel capacitor Cp.

Second switch SW2 is connected between ground voltage source and the 4th switch SW 4.Second switch SW2 is in response to the second switch control signal that provides from time schedule controller the be electrically connected other end of ground voltage supplies to the three capacitor C3 and an end of the 4th switch SW 4.As a result, ground voltage level GND is provided to the scan electrode Y of panel capacitor Cp.This will be discussed in more detail below.

The 4th switch SW 4 is connected between the scan electrode Y of second switch SW2 and panel capacitor Cp.The 4th switch SW 4 is electrically connected the common port of the other end of the end of second switch SW2 and the 3rd capacitor C 3 to the scan electrode Y of panel capacitor Cp in response to the 4th switch controlling signal that provides from time schedule controller.

As a result, the voltage of panel capacitor Cp is maintained at voltage Vs/2 (just, keep voltage Vs half) and keeps voltage Vs.This will be discussed in more detail below.

The common port that energy provides control module 58 to be connected the first capacitor C1 and the second capacitor C2, and between the 4th diode D4, the first inductor L1 and the energy recovery control module 60.Energy provides control module 58 controls to be provided at the scan electrode Y that the energy of storing among the second capacitor C2 arrives panel capacitor Cp.

Energy provides control module 58 to comprise the 3rd diode D3, and it is connected between the common port and the 4th diode D4 of the first capacitor C1 and the second capacitor C2, and the 5th switch SW 5, and it is connected between the 4th diode D4 and the first inductor L1.

The 3rd diode D3 is connected between the common port and the 4th diode D4 of the first capacitor C1, the second capacitor C2 and energy recovery control module 60.When the scan electrode Y that provides energy to panel capacitor Cp from the second capacitor C2, the 3rd diode D3 prevents the inverse current from the scan electrode Y of panel capacitor Cp.

In addition, when the voltage of panel capacitor Cp was maintained at voltage Vs/2, the 3rd diode D3 prevented the inverse current from the scan electrode Y of panel capacitor Cp.

The 5th switch SW 5 is connected the common port of the 3rd diode D3 and the 4th diode D4, between the common port of the first inductor L1 and energy recovery control module 60.The 5th switch SW 5 is in response to the 5th switch controlling signal that provides from time schedule controller, and control is provided at the scan electrode Y that the energy of storing among the second capacitor C2 arrives panel capacitor Cp.

Energy recovery control module 60 is connected the common port and the first diode D1 of the first capacitor C1 and the second capacitor C2, and the first inductor L1 and energy provide between the common port of control module 58.60 controls of energy recovery control module provide the quadergy of the discharge that does not participate in panel capacitor Cp to the second capacitor C2.

Energy recovery control module 60 comprises the common port that is connected the first capacitor C1 and the second capacitor C2 and the second diode D2 between the first diode D1, and is connected the 6th switch SW 6 between the first diode D 1 and the first inductor L1.

The second diode D2 is connected the common port that the first capacitor C1, the second capacitor C2 and energy provide control module 58, and between the first diode D1.When reclaiming quadergy from panel capacitor Cp, and the energy that recovery is provided afterwards is during to the second capacitor C2, and this second diode D2 prevents the inverse current from the second capacitor C2.

When the voltage of panel capacitor Cp was maintained at voltage Vs/2, the second diode D2 prevented the inverse current from the second capacitor C2.

The 6th switch SW 6 is connected the common port of the first diode D1 and the second diode D2, and the first inductor L1 and energy provide between the common port of control module 58.In response to the 6th switch controlling signal that provides from time schedule controller, the control of the 6th switch SW 6 provides the quadergy that reclaims from panel capacitor Cp to the second capacitor C2.

The first inductor L1 is connected the common port that energy provides control module 58 and energy recovery control module 60, and between the scan electrode Y of panel capacitor Cp.The first inductor L1 and panel capacitor Cp form resonance loop in response to the switch work of the 5th switch SW 5 and the 6th switch SW 6.

When connecting the 5th switch SW 5, the energy of storing in the second capacitor C2 is provided to the scan electrode Y of panel capacitor Cp by the LC resonance of the first inductor L1 and panel capacitor Cp.In addition, when connecting the 6th switch SW 6, the energy that reclaims from panel capacitor Cp is provided to the second capacitor C2 by the LC resonance of the first inductor L1 and panel capacitor Cp.

Be connected between first switch SW 1 and the second switch SW2 as the 3rd capacitor C3 that keeps capacitor.The voltage that is charged to the 3rd capacitor C3 equals voltage Vs/2.

The 4th diode D4 is connected the first capacitor C1, keeps the common port of the voltage source and first switch SW 1, and between the common port of the 3rd diode D3 and the 5th diode D5.The 4th diode D4 prevents from the inverse current of keeping voltage source.

As a result, prevented to be provided to the loss of energy of the scan electrode Y of panel capacitor Cp from the second capacitor C2.

The first diode D1 is connected the common port of the second capacitor C2, ground voltage source and second switch SW2, and between the common port of the second diode D2 and the 6th switch SW 6.The first diode D1 prevents to be recovered to from the scan electrode Y of panel capacitor Cp the loss of the energy of the second capacitor C2.

Can remove the first diode D1 and the 4th diode D4.

Fig. 5 is the sequential chart according to the switch of the plasma display panel device of first embodiment of the invention.Fig. 6 to 11 is the circuit diagrams that form current path according to the on/off switch operation of the switch of Fig. 5.Suppose voltage Vs/2 is charged to the first capacitor C1, the second capacitor C2 and the 3rd capacitor C3.

With reference to figure 5 to 11, between time point t1, connect second switch SW2 and the 4th switch SW 4 in response to the second switch control signal of the high state that provides from time schedule controller and the 4th switch controlling signal of high state.

As a result, as shown in Figure 6, form current path by the scan electrode Y of ground voltage source, second switch SW2, the 4th switch SW 4 and panel capacitor Cp.Therefore, the voltage of panel capacitor Cp maintains ground voltage level GND.

At time point t1, in response to the second switch control signal of the low state that provides from time schedule controller, the 4th switch controlling signal of low state and the 5th switch controlling signal of high state, second switch SW2 and the 4th switch SW 4 disconnect, and the 5th switch SW 5 is connected.

As a result, as shown in Figure 7, form current path by the scan electrode Y of the second capacitor C2, the 3rd diode D3, the 5th switch SW 5, the first inductor L1 and panel capacitor Cp, and the first inductor L1 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and the electric current I L1 that flows in the first inductor L1 are by equation 5 expressions.

[equation 5]

$V_p\left(t\right)=\frac{V_s}{2}(1-{\cos w}_{n}t),\mathrm{IL}1\left(t\right)=\frac{V_s}{{2Z}_n}{\sin w}_{n}t$

Here, $w_n=\frac{1}{\sqrt{L_1{C}_p}},Z_n=\sqrt{\frac{L_1}{C_p}}$

Therefore, at time point t1, the voltage of panel capacitor Cp (just, 0V) rise to voltage Vs/2, and the electric current I L1 that flows rises to Vs/2Z from ground voltage level in the first inductor L1 _n

At time point t2, first switch controlling signal in response to the high state that provides from time schedule controller, the 4th switch controlling signal of high state and the 5th switch controlling signal of high state, first switch SW 1 and the 4th switch SW 4 are connected, and the 5th switch SW 5 remains on the on-state of time point T1.

The result, as shown in Figure 8, form first current path by the scan electrode Y of the second capacitor C2, the 3rd diode D3, the 5th switch SW 5, the first inductor L1 and panel capacitor Cp, and second current path of the scan electrode Y by keeping voltage source, first switch SW 1, the 3rd capacitor C3, the 4th switch SW 4 and panel capacitor Cp.

Therefore, the voltage Vp of panel capacitor Cp is maintained at voltage Vs/2.Because the voltage between the two ends of the first inductor L1 is 0V, the electric current I L1 of the first inductor L1 is maintained at Vs/2Z _n

At time point t3, first switch controlling signal in response to the low state that provides from time schedule controller, the 4th switch controlling signal of low state and the 5th switch controlling signal of high state disconnect first switch SW 1 and the 4th switch SW 4, and the 5th switch SW 5 remain on the on-state of time point T2.

As a result, as shown in Figure 7, form current path by the scan electrode Y of the second capacitor C2, the 3rd diode D3, the 5th switch SW 5, the first inductor L1 and panel capacitor Cp, and the first inductor L1 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and the electric current I L1 that flows in the first inductor L1 are by equation 6 expressions.

[equation 6]

$V_p\left(t\right)=\frac{V_s}{2}(1+\sin w_{n}t),\mathrm{IL}1\left(t\right)=\frac{V_s}{{2Z}_n}{\cos w}_{n}t$

Therefore, at time point t3, the voltage Vp of panel capacitor Cp rises to from voltage Vs/2 and keeps voltage Vs, and the electric current I L1 that flows in the first inductor L1 is from Vs/2Z _nDrop to 0.

At time point t4, in response to first switch controlling signal of the high state that provides from time schedule controller, the 3rd switch controlling signal of high state and the 5th switch controlling signal of low state, connect first switch SW 1 and the 3rd switch SW 3, and disconnect the 5th switch SW 5.

As a result, as shown in Figure 9, form current path by the scan electrode Y of first switch SW 1, the 3rd switch SW 3 and panel capacitor Cp.Therefore, the voltage Vp of panel capacitor Cp is maintained at and keeps voltage Vs.

At time point t5, in response to first switch controlling signal of the low state that provides from time schedule controller, the 3rd switch controlling signal of low state and the 6th switch controlling signal of high state, disconnect first switch SW 1 and the 3rd switch SW 3, and connect the 6th switch SW 6.

As a result, as shown in figure 10, form current path by panel capacitor Cp, the first inductor L1, the 6th switch SW 6, the second diode D2 and the second capacitor C2, and the first inductor L1 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and the electric current I L1 that flows in the first inductor L1 are by 7 expressions of following equation.

[equation 7]

$V_p\left(t\right)=\frac{V_s}{2}(1+{\cos w}_{n}t),\mathrm{IL}1\left(t\right)=-\frac{V_s}{{2Z}_n}{\sin w}_{n}t$

Therefore, at time point t5, the voltage of panel capacitor Cp drops to voltage Vs/2 from keeping voltage Vs, and the electric current I L1 of the first inductor L1 drops to-(Vs/2Z from 0 _n).

At time point t6, in response to first switch controlling signal of the high state that provides from time schedule controller, the 4th switch controlling signal of high state and the 6th switch controlling signal of high state, connect first switch SW 1 and the 4th switch SW 4, and the 6th switch SW 6 remains on time point t5 on-state.

The result, as shown in figure 11, form first current path by panel capacitor Cp, the first inductor L1, the 6th switch SW 6, the second diode D2 and the second capacitor C2, and second current path of the scan electrode Y by keeping voltage source, first switch SW 1, the 3rd capacitor C3, the 4th switch SW 4 and panel capacitor Cp.

Therefore, the voltage Vp of panel capacitor Cp is maintained at voltage Vs/2.Because the voltage between the two ends of the first inductor L1 is 0V, the electric current I L1 of the first inductor L1 is by the value of keeping-(Vs/2Z _n).

At time point t7, first switch controlling signal in response to the low state that provides from time schedule controller, the 4th switch controlling signal of low state and the 6th switch controlling signal of high state disconnect first switch SW 1 and the 4th switch SW 4, and the 6th switch SW 6 remain on the on-state of time point t6.

As a result, as shown in figure 10, form current path by panel capacitor Cp, the first inductor L1, the 6th switch SW 6, the second diode D2 and the second capacitor C2, and the first inductor L1 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and the electric current I L1 that flows in the first inductor L1 are by equation 8 expressions.

[equation 8]

$V_p\left(t\right)=\frac{V_s}{2}(1-{\sin w}_{n}t),\mathrm{IL}1\left(t\right)=-\frac{V_s}{{2Z}_n}{\cos w}_{n}t$

Therefore, at time point t7, the voltage Vp of panel capacitor Cp drops to ground voltage level from voltage Vs/2, and (just, 0V), and the electric current I L1 among the first inductor L1 is from-(Vs/2Z _n) rise to 0.

When time point t8 and after repeat the switching manipulation of time point t1 to t7, keep the scan electrode Y that pulse is provided to panel capacitor Cp.

Figure 12 is the circuit diagram according to the plasma display panel device of second embodiment of the invention.

With reference to Figure 12, has symmetrical structure at panel capacitor Cp two ends according to the apparatus for energy recovery 62 of the plasma display panel device of second embodiment of the invention.

Panel capacitor Cp is illustrated in the scan electrode Y of PDP equivalently and keeps the electric capacity that forms between the electrode Z.Apparatus for energy recovery with structure identical with the structure of the apparatus for energy recovery of installing in the scan electrode Y of panel capacitor Cp 62 is installed in keeping among the electrode Z of panel capacitor Cp.

Apparatus for energy recovery 62 according to the plasma display panel device of second embodiment of the invention comprises: panel capacitor Cp; Be used to provide keep voltage Vs keep the voltage source (not shown); The first capacitor C1 and the second capacitor C2, it is connected in series in keeps between voltage source and the ground voltage source (not shown), is formed on the first node N1 between the first capacitor C1 and the second capacitor C2; Be connected the voltage of keeping between voltage source and the panel capacitor Cp of keeping control module 64 is provided.

Apparatus for energy recovery 62 comprises that further ground voltage provides control module 66, the 3rd capacitor C3 and the 4th capacitor C4, Section Point N2, the first inductor L1, the first energy recovery control module 70A, second energy provides control module 68B, the second inductor L2, first energy provides the control module 68A and the second energy recovery control module 70B.Ground voltage provides control module 66 to be connected between ground voltage source and the panel capacitor Cp.The 3rd capacitor C3 and the 4th capacitor C4 are connected in series in and keep voltage and provide control module 64 and ground voltage to provide between the control module 66.Between the 3rd capacitor C3 and the 4th capacitor C4, form Section Point N2.The first inductor L1 is connected between first node N1 and the Section Point N2.The first energy recovery control module 70A and second energy provide control module 68B to be connected in parallel between the first node N1 and the first inductor L1.The second inductor L2 is connected between the scan electrode Y of Section Point N2 and panel capacitor Cp.First energy provides the control module 68A and the second energy recovery control module 70B to be connected in parallel between the Section Point N2 and the second inductor L2.

The second capacitor C2 and the 4th capacitor C4 are that energy provides/reclaim capacitor, and the 3rd capacitor C3 keeps capacitor.

The first capacitor C1 is connected and keeps between the voltage source and the second capacitor C2, and dividing potential drop this keep voltage Vs.As being charged to the first capacitor C1 from half the voltage Vs/2 that keeps voltage Vs that keeps that voltage source provides.

Provide/reclaim the second capacitor C2 of capacitor to be connected between the first capacitor C1 and the ground voltage source as energy.The second capacitor C2 reclaims and does not participate in the quadergy of the discharge among the PDP, and the scan electrode Y of the energy of recovery to panel capacitor Cp is provided once more.To be charged to the second capacitor C2 as half the voltage Vs/2 that keeps voltage Vs.

Keeping voltage provides control module 64 to be connected to keep voltage source, the first capacitor C1 and the 3rd capacitor C3, and between the scan electrode Y of panel capacitor Cp.Keeping voltage provides control module 64 control to provide from what keep that voltage source provides to keep the scan electrode Y of voltage Vs to panel capacitor Cp.

Keeping voltage provides control module 64 to comprise to be connected in series in first switch SW 1 and the second switch SW2 that keeps between voltage source and the panel capacitor Cp.

First switch SW 1 is connected the first capacitor C1 and keeps the common port of voltage source, and between the common port of the 3rd capacitor C3 and second switch SW2.First switch SW 1 is electrically connected and keeps the end of voltage source, second switch SW2 and the end of the 3rd capacitor C3 in response to first switch controlling signal that provides from the time schedule controller (not shown).

As a result, the voltage of panel capacitor Cp is maintained at voltage Vs/2 (just, keep voltage Vs half) and keeps voltage Vs.This will be discussed in more detail below.

Second switch SW2 is connected between the scan electrode Y of first switch SW 1 and panel capacitor Cp.In response to the second switch control signal that provides from time schedule controller, what the switching manipulation of second switch SW2 provided the end that is provided to first switch SW 1 keeps the scan electrode Y of voltage Vs to panel capacitor Cp.

Ground voltage provides between the scan electrode Y that control module 66 is connected ground voltage source, the second capacitor C2 and the 4th capacitor C4 and panel capacitor Cp.Ground voltage provides control module 66 controls that ground voltage level GND is provided the scan electrode Y to panel capacitor Cp.

Ground voltage provides control module 66 to comprise the 3rd switch SW 3 and the 4th switch SW 4, and it is connected in series between the scan electrode Y of ground voltage source and panel capacitor Cp.

The 3rd switch SW 3 is connected the common port in the second capacitor C2 and ground voltage source, and between the common port of the 4th capacitor C4 and the 4th switch SW 4.The 3rd switch SW 3 is in response to the 3rd switch controlling signal that provides from time schedule controller the be electrically connected end of ground voltage supplies to the four capacitor C4 and an end of the 4th switch SW 4.As a result, ground voltage level GND is provided to the scan electrode Y of panel capacitor Cp.This will be discussed in more detail below.

The 4th switch SW 4 is connected between the scan electrode Y of the 3rd switch SW 3 and panel capacitor Cp.The 4th switch SW 4 is electrically connected the common port of an end of end of the 3rd switch SW 3 and the 4th capacitor C4 to the scan electrode Y of panel capacitor Cp in response to the 4th switch controlling signal that provides from time schedule controller.As a result, the voltage of panel capacitor Cp is maintained at voltage Vs/2 (just, keep voltage Vs half) and ground voltage level GND.This will be discussed in more detail below.

First energy provides control module 68A to be connected between the Section Point N2 and the second inductor L2.First energy provides control module 68A control to be provided at the scan electrode Y that the energy of storing among the 4th capacitor C4 arrives panel capacitor Cp.

First energy provides control module 68A to comprise the 5th switch SW 5 and the first diode D1, and they are connected between the Section Point N2 and the second inductor L2.First energy provides control module 68A to be provided at the scan electrode Y of stored voltage Vs/4 among the 4th capacitor C4 (just, keep voltage Vs 1/4th) to panel capacitor Cp.

In response to the 5th switch controlling signal that provides from time schedule controller, 5 controls of the 5th switch SW are provided at the scan electrode Y that the energy of storing among the 4th capacitor C4 arrives panel capacitor Cp.

When panel capacitor Cp recovers energy, the first diode D1 prevents that the energy that reclaims from flowing into the 5th switch SW 5.

Second energy provides control module 68B to be connected between the first node N1 and the first inductor L1.Second energy provides control module 68B control to be provided at the scan electrode Y that the energy of storing among the second capacitor C2 arrives panel capacitor Cp.

Second energy provides control module 68B to comprise the 6th switch SW 6 and the second diode D2, and they are connected between the first node N1 and the first inductor L1.

Second energy provides control module 68B will equal first energy to provide the voltage of panel capacitor Cp of the voltage Vs/2 of control module 68A to be elevated to and approximately keeps voltage Vs.

In response to the 6th switch controlling signal that provides from time schedule controller, 6 controls of the 6th switch SW are provided at the scan electrode Y that the energy of storing among the second capacitor C2 arrives panel capacitor Cp.

When panel capacitor Cp recovers energy, the second diode D2 prevents that the energy that reclaims from flowing into the 6th switch SW 6.

The first energy recovery control module 70A is connected between the first node N1 and the first inductor L1.First energy recovery control module 70A control provides the quadergy that does not participate in the discharge among the panel capacitor Cp to the second capacitor C2.The first energy recovery control module 70A comprises minion pass SW7 and the 3rd diode D3, and they are connected between the first node N1 and the first inductor L1.

Close control signal in response to the minion that provides from time schedule controller, minion is closed SW7 control provides the quadergy that reclaims from panel capacitor Cp to the second capacitor C2.

When reclaiming quadergy from panel capacitor Cp and this quadergy is provided to the second capacitor C2, the 3rd diode D3 prevents the inverse current from the second capacitor C2.

The second energy recovery control module 70B is connected between the Section Point N2 and the second inductor L2.Second energy recovery control module 70B control provides quadergy to the four capacitor C4 that reclaim from panel capacitor Cp.

The second energy recovery control module 70B comprises octavo pass SW8 and the 4th diode D4, and it is connected between the Section Point N2 and the second inductor L2.

Close control signal in response to the octavo that provides from time schedule controller, octavo is closed SW8 control provides the quadergy to that does not participate in the discharge among the panel capacitor Cp four capacitor C4.

When reclaiming from panel capacitor Cp when not participating in the quadergy of the discharge the panel capacitor Cp and this quadergy to the four capacitor C4 being provided, the 4th diode D4 prevents the inverse current from the 4th capacitor C4.

The first inductor L1 and panel capacitor Cp close the switching manipulation of SW7 and form resonance loop in response to the 6th switch SW 6 and the minion that are connected between first node N1 and the Section Point N2.

When connecting the 6th switch SW 6, the energy of storing in the second capacitor C2 is provided to the scan electrode Y of panel capacitor Cp by the LC resonance of the first inductor L1 and panel capacitor Cp.In addition, when connecting minion and close SW7, the energy that reclaims from panel capacitor Cp is provided to the second capacitor C2 by the LC resonance of the first inductor L1 and panel capacitor Cp.

In response to the switch work of the 5th switch SW 5 between the scan electrode Y that is connected Section Point N2 and panel capacitor Cp and octavo pass SW8, the second inductor L2 and panel capacitor Cp form resonance loop.

When connecting the 5th switch SW 5, the energy of storing in the 4th capacitor C4 is provided to the scan electrode Y of panel capacitor Cp by the LC resonance of the second inductor L2 and panel capacitor Cp.In addition, when connecting octavo and close SW8, the energy that reclaims from panel capacitor Cp is provided to the 4th capacitor C4 by the LC resonance of the second inductor L2 and panel capacitor Cp.Certainly can remove the first capacitor C1.

Figure 13 is the sequential chart according to the switch of the plasma display panel device of second embodiment of the invention.Figure 14 to 21 is the circuit diagrams according to the current path of the on/off switch operation formation of the switch of Figure 13.

Suppose that each the voltage at two ends at the first capacitor C1 and the second capacitor C2 is set to voltage Vs/2, and be set to keep 1/4th the Vs/4 of voltage Vs at each the voltage at two ends of the 3rd capacitor C3 and the 4th capacitor C4.

Referring to figs. 13 through 21,, connect the 3rd switch SW 3 and the 5th switch SW 5 in response to the 3rd switch controlling signal of the high state that provides from time schedule controller and the 5th switch controlling signal of high state at time point t1.

The result, as shown in figure 14, form current path by the scan electrode Y of the 3rd switch SW 3, the 4th capacitor C4, Section Point N2, the 5th switch SW 5, the first diode D1, the second inductor L2 and panel capacitor Cp, and the second inductor L2 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and the electric current I p2 (t) that flows in the second inductor L2 are by equation 9 expressions.

[equation 9]

$V_p\left(t\right)=\frac{\mathrm{Vs}}{4}(1-e^{-{\mathrm{\&zeta;\&omega;}}_{n}t}{\cos \mathrm{\&omega;}}_{d}t-\frac{{\mathrm{\&zeta;e}}^{{-\mathrm{\&zeta;\&omega;}}_{n}t}}{\sqrt{1-{\mathrm{\&zeta;}}^2}}{\sin \mathrm{\&omega;}}_{d}t)$

$i_{p2}\left(t\right)=\frac{V{\mathrm{se}}^{{-\mathrm{\&zeta;\&omega;}}_{n}t}}{{4\mathrm{L\&omega;}}_d}{\sin \mathrm{\&omega;}}_{d}t$

Here, ${\mathrm{\&omega;}}_n=\frac{1}{\sqrt{{\mathrm{LC}}_p}},\mathrm{\&zeta;}=R_{\mathrm{eq}}\sqrt{\frac{C_p}{L}},$

${\mathrm{\&omega;}}_d={\mathrm{\&omega;}}_n\sqrt{1-{\mathrm{\&zeta;}}^2}$

R _EqBe illustrated in the summation of the dead resistance shown in the current path.Therefore, time point t1, the voltage Vp of panel capacitor Cp (just, 0V) rises to voltage Vs/2 from ground voltage level.

At time point t2, connect second switch SW2 in response to the second switch control signal of the high state that provides from time schedule controller and the 3rd switch controlling signal of high state, and the 3rd switch SW 3 remains on the on-state of time point t1.

As a result, as shown in figure 15, form current path by the scan electrode Y of the 3rd switch SW 3, the 4th capacitor C4, the 3rd capacitor C3, second switch SW2 and panel capacitor Cp.Therefore, the voltage Vp of panel capacitor Cp keeps voltage Vs/2

At time point t3, disconnect the 3rd switch SW 3.In addition, connect second switch SW2 and the 6th switch SW 6 in response to the second switch control signal of the high state that provides from time schedule controller and the 6th switch controlling signal of high state.

The result, as shown in figure 16, form current path by the scan electrode Y of the second capacitor C2, first node N1, the 6th switch SW 6, the second diode D2, the first inductor L1, second switch SW2 and panel capacitor Cp, and the first inductor L1 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and the current i p1 (t) that flows in the first inductor L1 are by equation 10 expressions.

[equation 10]

$V_p\left(t\right)=\frac{3\mathrm{Vs}}{4}(1-e^{-{\mathrm{\&zeta;\&omega;}}_{n}t}{\cos \mathrm{\&omega;}}_{d}t-\frac{{\mathrm{\&zeta;e}}^{{-\mathrm{\&zeta;\&omega;}}_{n}t}}{\sqrt{1-{\mathrm{\&zeta;}}^2}}{\sin \mathrm{\&omega;}}_{d}t)$

$i_{p1}\left(t\right)=\frac{{\mathrm{Vse}}^{-\mathrm{\&zeta;}{\mathrm{\&omega;}}_{n}t}}{4{\mathrm{L\&omega;}}_d}\sin {\mathrm{\&omega;}}_{d}t$

Therefore, the voltage Vp of panel capacitor Cp rises near the voltage of keeping voltage Vs from voltage Vs/2.

At time point t4, connect first switch SW 1 and second switch SW2 in response to first switch controlling signal of the high state that provides from time schedule controller and the second switch control signal of high state.

As a result, as shown in figure 17, form current path by the scan electrode Y that keeps voltage source, first switch SW 1, second switch SW2 and panel capacitor Cp.Therefore, the voltage Vp of panel capacitor Cp is maintained at and keeps voltage Vs.

At time point t5, close control signal connection second switch SW2 and minion pass SW7 in response to the second switch control signal of the high state that provides from time schedule controller and the minion of high state.

The result, as shown in figure 18, form the current path of scan electrode Y, second switch SW2, the 3rd capacitor C3, the first inductor L1, the 3rd diode D3, minion pass SW7 and the second capacitor C2 by panel capacitor Cp, and the first inductor L1 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and in the first inductor L1 streaming current ip1 (t) by equation 11 expression.

[equation 11]

$V_p\left(t\right)=\frac{3\mathrm{Vs}}{4}(1+e^{-{\mathrm{\&zeta;\&omega;}}_{n}t}{\cos \mathrm{\&omega;}}_{d}t+\frac{{\mathrm{\&zeta;e}}^{{-\mathrm{\&zeta;\&omega;}}_{n}t}}{\sqrt{1-{\mathrm{\&zeta;}}^2}}{\sin \mathrm{\&omega;}}_{d}t)$

$i_{p1}\left(t\right)=\frac{V{\mathrm{se}}^{{-\mathrm{\&zeta;\&omega;}}_{n}t}}{{4\mathrm{L\&omega;}}_d}{\sin \mathrm{\&omega;}}_{d}t$

Therefore, the voltage Vp of panel capacitor Cp drops to voltage Vs/2, and the energy that storage is reclaimed from panel capacitor Cp in the second capacitor C2.

At time point t6, connect second switch SW2 and the 3rd switch SW 3 in response to the second switch control signal of the high state that provides from time schedule controller and the 3rd switch controlling signal of high state.

As shown in figure 19, form the current path of scan electrode Y, second switch SW2, the 3rd capacitor C3, the 4th capacitor C4 and the 3rd switch SW 3 of passing through panel capacitor Cp.Therefore, the voltage Vp of panel capacitor Cp is maintained at voltage Vs/2.

At time point t7, disconnect second switch SW2, in addition, connect the 3rd switch SW 3 and octavo pass SW8 in response to the 3rd switch controlling signal of the high state that provides from time schedule controller and the octavo pass control signal of high state.

The result, as shown in figure 20, form scan electrode Y, the second inductor L2, the 4th diode D4, the octavo of passing through panel capacitor Cp and close the current path of SW8, Section Point N2, the 4th capacitor C4 and the 3rd switch SW 3, and the second inductor L2 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and the current i p2 (t) that flows in second inductance L 2 are by equation 12 expressions.

[equation 12]

$V_p\left(t\right)=\frac{\mathrm{Vs}}{4}(1+e^{-{\mathrm{\&zeta;\&omega;}}_{n}t}{\cos \mathrm{\&omega;}}_{d}t+\frac{{\mathrm{\&zeta;e}}^{{-\mathrm{\&zeta;\&omega;}}_{n}t}}{\sqrt{1-{\mathrm{\&zeta;}}^2}}{\sin \mathrm{\&omega;}}_{d}t)$

$i_{p2}\left(t\right)=-\frac{V{\mathrm{se}}^{{-\mathrm{\&zeta;\&omega;}}_{n}t}}{{4\mathrm{L\&omega;}}_d}{\sin \mathrm{\&omega;}}_{d}t$

Therefore, the voltage Vp of panel capacitor Cp drops to ground voltage level (just, 0V) from voltage Vs/2.The energy that storage is reclaimed from panel capacitor Cp in the 4th capacitor C4.

At time point t8, connect the 3rd switch SW 3 and the 4th switch SW 4 in response to the 3rd switch controlling signal of the high state that provides from time schedule controller and the 4th switch controlling signal of high state.

As a result, as shown in figure 21, form current path by the scan electrode Y of ground voltage source, the 4th switch SW 4, the 3rd switch SW 3 and panel capacitor Cp.Therefore, the voltage Vp of panel capacitor Cp is maintained at ground voltage level GND.

Figure 22 is the circuit diagram according to the plasma display panel device of third embodiment of the invention.

With reference to Figure 22, has symmetrical result at panel capacitor Cp two ends according to the apparatus for energy recovery 72 of the plasma display panel device of third embodiment of the invention.

Panel capacitor Cp is illustrated in the scan electrode Y of PDP equivalently and keeps the electric capacity that forms between the electrode Z.Apparatus for energy recovery with structure identical with the structure of the apparatus for energy recovery of installing in the scan electrode Y of panel capacitor Cp 72 is installed in keeping among the electrode Z of panel capacitor Cp.

Comprise according to the apparatus for energy recovery 72 of the plasma display panel device of third embodiment of the invention being connected in series in the first capacitor C1 and the second capacitor C2 that keeps between voltage source (not shown) and the ground voltage source (not shown), and the voltage of keeping that is connected between the scan electrode Y that keeps voltage source and panel capacitor Cp provides control module 74.

Apparatus for energy recovery 72 further comprises: ground voltage provides control module 76, the 3rd capacitor C3 and the 4th capacitor C4, second energy provides control module 80, the first energy recovery control modules 82, the first energy that the control module 78 and the second energy recovery control module 84 are provided.Ground voltage provides between the scan electrode Y that control module 76 is connected ground voltage source and panel capacitor Cp.The 3rd capacitor C3 and the 4th capacitor C4 are connected in series in and keep voltage and provide control module 74 and ground voltage to provide between the control module 76.Second energy provides between the common port of common port that the control module 80 and the first energy recovery control module 82 be connected in the first capacitor C1 and the second capacitor C2 in parallel and the 3rd capacitor C3 and the 4th capacitor C4.First energy provides between the scan electrode Y of common port that the control module 78 and the second energy recovery control module 84 be connected the 3rd capacitor C3 and the 4th capacitor C4 and panel capacitor Cp.

Apparatus for energy recovery 72 further comprises the first diode D1 and the second diode D2, and it is connected in parallel keeps voltage and provide the control module 74 and second energy to provide between the control module 80.

Apparatus for energy recovery 72 further comprises the 6th diode D6, the 7th diode D7, the 5th diode D5, the tenth diode D10 and the 11 diode D11.The 6th diode D6 and the 7th diode D7 are connected in parallel and keep voltage and provide between the control module 74 and the second energy recovery control module 84.The 5th diode D5 is connected ground voltage and provides between the control module 76 and the first energy recovery control module 82.The tenth diode D10 and the 11 diode D11 are connected in ground voltage in parallel provides the control module 76 and first energy to provide between the control module 78.

The first capacitor C1 is connected and keeps between the voltage source and the second capacitor C2.This keeps voltage Vs the first capacitor C1 and the second capacitor C2 dividing potential drop.The voltage that is charged to the first capacitor C1 equals as half the voltage Vs/2 that keeps voltage Vs from keeping that voltage source provides.

The second capacitor C2 is connected between the first capacitor C1 and the ground voltage source.The second capacitor C2 reclaims from PDP and does not participate in the quadergy of the discharge the PDP, and the scan electrode Y of the energy of recovery to panel capacitor Cp is provided once more.The voltage that is charged to the second capacitor C2 equals as half the voltage Vs/2 that keeps voltage Vs.

Keeping voltage provides control module 74 to be connected to keep the common port of the voltage source and the first capacitor C1, and between the scan electrode Y of panel capacitor Cp.Keeping voltage provides control module 74 control to provide from what keep that voltage source provides to keep the scan electrode Y of voltage Vs to panel capacitor Cp.

Keeping voltage provides control module 74 to comprise first switch SW 1 and second switch SW2, and it is connected in series in keeps between voltage source and the panel capacitor Cp.

First switch SW 1 is connected to be kept between voltage source and the second switch SW2.First switch SW 1 is in response to first switch controlling signal from the time schedule controller (not shown), and control is provided at keeping voltage Vs or keeping the end of voltage Vs to second switch SW2 from what keep that voltage source provides of storing among the first capacitor C1 and the second capacitor C2.

As a result, when connecting second switch SW2, the scan electrode Y that voltage Vs is provided to panel capacitor Cp will be kept in response to the second switch control signal that provides from time schedule controller.

Second switch SW2 is connected between the scan electrode Y of first switch SW 1 and panel capacitor Cp.What second switch SW2 provided the end that is provided to second switch SW2 in response to second switch control signal control keeps voltage Vs and the voltage Vs/2 scan electrode Y to panel capacitor Cp.As a result, when connecting second switch SW2, the voltage of panel capacitor Cp is maintained at voltage Vs/2 and keeps voltage Vs.

The common port that ground voltage provides control module 76 to be connected the ground voltage source and the second capacitor C2, and between the scan electrode Y of panel capacitor Cp.Ground voltage provides control module 76 controls that ground voltage level GND is provided the scan electrode Y to panel capacitor Cp.

Ground voltage provides control module 76 to comprise the 3rd switch SW 3 and the 4th switch SW 4, and it is connected in series between the scan electrode Y of ground voltage source and panel capacitor Cp.

The 3rd switch SW 3 is connected between the scan electrode Y of the 4th switch SW 4 and panel capacitor Cp.The 3rd switch SW 3 is in response to the 3rd switch controlling signal that provides from time schedule controller, and control provides the ground voltage level GND of an end that is provided to the 3rd switch SW 3 scan electrode Y to panel capacitor Cp.

As a result, when connecting the 3rd switch SW 3, ground voltage level GND is provided to the scan electrode Y of panel capacitor Cp.

The 4th switch SW 4 is connected between the 3rd switch SW 3 and the ground voltage source.The 4th switch SW 4 is in response to the 4th switch controlling signal that provides from time schedule controller, and an end that is electrically connected end of the 3rd switch SW 3 and the 4th capacitor C4 is to the ground voltage source.

As a result, the energy of emitting from panel capacitor Cp is stored in the 4th capacitor C4.In addition, panel capacitor Cp emits the energy of storing in panel capacitor Cp, and the voltage of keeping panel capacitor Cp is at ground voltage level GND.This will be discussed in more detail below.

The 3rd capacitor C3 is connected the common port of the second diode D2 and the 6th diode D6, and the first energy recovery control module 82, the second energy recovery control module 84, first energy provide between the common port that control module 78, second energy provide control module 80 and the 4th capacitor C4.The scan electrode Y that the 3rd capacitor C3 and the second capacitor C2 or the 3rd capacitor C3 and the 4th capacitor C4 provide energy to arrive panel capacitor Cp, and also reclaim the energy that does not participate in the discharge among the panel capacitor Cp.The voltage that is charged to the 3rd capacitor C3 equals as 1/4th the voltage Vs/4 that keeps voltage Vs.

The 4th capacitor C4 is connected the common port of the 5th diode D5 and the tenth diode D10, and the first energy recovery control module 82, the second energy recovery control module 84, first energy provide between the common port that control module 78, second energy provide control module 80 and the 3rd capacitor C3.The scan electrode Y that the 4th capacitor C4 and the 3rd capacitor C3 provide energy to arrive panel capacitor Cp, and also reclaim the quadergy that does not participate in the discharge among the panel capacitor Cp.Voltage charging to the four capacitor C4 with Vs/4.

First energy provides control module 78 to be connected between the second energy recovery control module 84, the tenth diode D10 and the 11 diode D11.First energy provides control module 78 controls to be provided at the scan electrode Y that the energy of storing among the 4th capacitor C4 arrives panel capacitor Cp.First energy provides control module 78 to comprise octavo pass SW8, the 9th diode D9 and the 4th inductor L4.

Octavo is closed the common port that SW8 is connected the 3rd capacitor C3, the 4th capacitor C4 and the second energy recovery control module 84, and between the tenth diode D10.Octavo is closed SW8 and is closed control signal in response to the octavo that provides from time schedule controller, and control is provided at the scan electrode Y that the energy of storing among the 4th capacitor C4 arrives panel capacitor Cp.

The 9th diode D9 is connected the common port of the scan electrode Y of the second energy recovery control module 84 and panel capacitor Cp, and between the 11 diode D11.When the energy of storing in being provided at the 4th capacitor C4 arrived the scan electrode Y of panel capacitor Cp, the 9th diode D9 prevented the inverse current from the scan electrode Y of panel capacitor Cp.

The 4th inductor L4 is connected the common port that octavo is closed SW8 and the tenth diode D10, and between the common port of the 9th diode D9 and the 11 diode D11.When connecting the 4th switch SW 4 and octavo pass SW8, the 4th inductor L4 and panel capacitor Cp form the series resonance loop.

More specifically, when connecting the 4th switch SW 4 and octavo pass SW8, the energy that will store in the 4th capacitor C4 is provided to the scan electrode Y of panel capacitor Cp by the series resonance loop of the 4th inductor L4 and panel capacitor Cp.

Second energy provides control module 80 to be connected between the first energy recovery control module 82, the first diode D1 and the second diode D2.Second energy provides control module 80 controls to be provided at the scan electrode Y that the energy of storing among the second capacitor C2 and the 3rd capacitor C3 arrives panel capacitor Cp.Second energy provides control module 80 to comprise the 3rd diode D3, the 5th switch SW 5 and the first inductor L1.

The 3rd diode D3 is connected the common port of the first capacitor C1, the second capacitor C2 and the first energy recovery control module 82, and between the common port of the first diode D1 and the first inductor L1.When the energy of storing in being provided at the second capacitor C2 and the 3rd capacitor C3 arrived the scan electrode Y of panel capacitor Cp, the 3rd diode D3 prevented that inverse current from flowing to the second capacitor C2 from the scan electrode Y of panel capacitor Cp.

The 5th switch SW 5 is connected the common port of the 3rd capacitor C3, the 4th capacitor C4 and the first energy recovery control module 82, and between the second diode D2.The 5th switch SW 5 is in response to the 5th switch controlling signal that provides from time schedule controller, and control is provided at the scan electrode Y that the energy of storing among the second capacitor C2 and the 3rd capacitor C3 arrives panel capacitor Cp.

The first inductor L1 is connected the common port of the first diode D1 and the 3rd diode D3, and between the common port of the 5th switch SW 5 and the second diode D2.When connecting second switch SW2 and the 5th switch SW 5, the first inductor L1 and panel capacitor Cp form the series resonance loop.More specifically, when connecting second switch SW2 and the 5th switch SW 5, the series resonance loop by the first inductor L1 and panel capacitor Cp is provided at the energy stored among the second capacitor C2 and the 3rd capacitor C3 scan electrode Y to panel capacitor Cp.

The first energy recovery control module 82 is connected second energy and provides between control module 80 and the 5th diode D5.82 controls of the first energy recovery control module provide the quadergy that does not participate in the discharge among the panel capacitor Cp to the second capacitor C2 and the 3rd capacitor C3.The first energy recovery control module 82 comprises the 6th switch SW 6, the 4th diode D4 and the 3rd inductor L3.

The 6th switch SW 6 is connected the common port of the first capacitor C1, the second capacitor C2 and the 3rd diode D3, and between the 4th diode D4.The 6th switch SW 6 is in response to the 6th switch controlling signal that provides from time schedule controller, and control provides the quadergy that reclaims from panel capacitor Cp to the second capacitor C2 and the 3rd capacitor C3.

The 4th diode D4 is connected the common port of the 5th diode D5 and the 3rd inductor L3, and between the 6th switch SW 6.The 4th diode D4 during to the second capacitor C2 and the 3rd capacitor C3, prevents the inverse current from the second capacitor C2 and the 3rd capacitor C3 at the energy that recovers energy from panel capacitor Cp and recovery is provided.

The 3rd inductor L3 is connected the common port of the 3rd capacitor C3, the 4th capacitor C4 and the 5th switch SW 5, and between the 5th diode D5.When connecting second switch SW2 and the 6th switch SW 6, the 3rd inductor L3 and panel capacitor Cp form the series resonance loop.More specifically, when connecting second switch SW2 and the 6th switch SW 6, the series resonance loop by the 3rd inductor L3 and panel capacitor Cp provides the energy of emitting from panel capacitor Cp to the second capacitor C2.

The second energy recovery control module 84 is connected first energy and provides between control module 78, the 6th diode D6 and the 7th diode D7.84 controls of the second energy recovery control module provide the quadergy to that does not participate in the discharge among the panel capacitor Cp four capacitor C4.The second energy recovery control module 84 comprises minion pass SW7, the 8th diode D8 and the second inductor L2.

Minion is closed the common port that SW7 is connected the 3rd capacitor C3, the 4th capacitor C4 and octavo pass SW8, and between the 6th diode D6.Minion is closed SW7 and is closed control signal in response to the minion that provides from time schedule controller, and control provides quadergy to the four capacitor C4 that reclaim from panel capacitor Cp.

The energy of storing in the 4th capacitor C4 is less than the energy of storing in the second capacitor C2 and the 3rd capacitor C3.

The 8th diode D8 is connected the scan electrode Y of second switch SW2, the 3rd switch SW 3, panel capacitor Cp and the common port of the 9th diode D9, and between the 7th diode D7.The 8th diode D8 prevents the inverse current from the 4th capacitor C4 when recovering energy from panel capacitor Cp and store the energy that reclaims among the 4th capacitor C4.

The second inductor L2 is connected the common port of the 6th diode D6 and minion pass SW7, and between the common port of the 7th diode D7 and the 8th diode D8.When connecting the 4th switch SW 4 and minion pass SW7, the second inductor L2 and panel capacitor Cp form the series resonance loop.More specifically, when connecting the 4th switch SW 4 and minion and close SW7, the series resonance loop by the second inductor L2 and panel capacitor Cp provides energy to the four capacitor C4 that emit from panel capacitor Cp.

The first diode D1 is connected between first switch SW 1 and the 3rd diode D3.The first diode D1 prevents that inverse current from flowing to second energy from the scan electrode Y that keeps voltage source and panel capacitor Cp control module 80 is provided.

The second diode D2 is connected between first switch SW 1 and the 5th switch SW 5.The first diode D1 and the second diode D2 are connected in parallel.The second diode D2 prevents that inverse current from flowing to second energy from the scan electrode Y that keeps voltage source and panel capacitor Cp control module 80 is provided.

The 5th diode D5 is connected the common port of the 3rd inductor L3 and the 4th diode D4, and between the common port of the 4th switch SW 4 and the 4th capacitor C4.The 5th diode D5 prevents that inverse current from flowing to the 4th capacitor C4 from the first energy recovery control module 82.

The 6th diode D6 is connected the common port of second switch SW2 and the 3rd capacitor C3, and between the common port of the second inductor L2 and minion pass SW7.The 6th diode D6 prevents that inverse current from flowing to the second energy recovery control module 84 from the scan electrode Y that keeps voltage source and panel capacitor Cp.

The 7th diode D7 is connected the common port of second switch SW2 and the 3rd capacitor C3, and between the common port of the second inductor L2 and minion pass SW7.The 6th diode D6 and the 7th diode D7 are connected in parallel.The 7th diode D7 prevents that inverse current from flowing to the second energy recovery control module 84 from the scan electrode Y that keeps voltage source and panel capacitor Cp.

The tenth diode D10 is connected the common port of the 4th inductor L4 and octavo pass SW8, and between the common port of the 3rd switch SW 3 and the 4th capacitor C4.The tenth diode D10 prevents that inverse current from flowing to the 4th capacitor C4 from the first energy recovery control module 82.

The 11 diode D11 is connected the common port of the 4th inductor L4 and the 9th diode D9, and between the common port of the 3rd switch SW 3 and the 4th capacitor C4.The 11 diode D11 prevents that inverse current from flowing to the 4th capacitor C4 from the first energy recovery control module 82.

Can remove the first diode D1, the second diode D2, the 5th diode D5, the 6th diode D6, the 7th diode D7, the tenth diode D10 and the 11 diode D11.

Figure 23 is the sequential chart according to the switch of the plasma display panel device of third embodiment of the invention.Figure 24 to 32 is the circuit diagrams according to the current path of the on/off switch operation formation of the switch of Figure 23.Suppose that voltage is set to voltage Vs/2 between each two ends of the first capacitor C1 and the second capacitor C2, and the voltage between each the two ends of the 3rd capacitor C3 and the 4th capacitor C4 is set to voltage Vs/4.

With reference to Figure 23 to 32, before time point t1, in response to connecting the 3rd switch SW 3 and the 4th switch SW 4 from the 3rd switch controlling signal of the high state of time schedule controller and the 4th switch controlling signal of high state.

As a result, as shown in figure 24, form current path by the scan electrode Y of ground voltage source, the 4th switch SW 4, the 3rd switch SW 3 and panel capacitor Cp.Therefore, the voltage of panel capacitor Cp is kept ground voltage level GND.

At time point t1, in response to closing control signal from the 3rd switch controlling signal of the low state of time schedule controller, the 4th switch controlling signal of high state and the octavo of high state, disconnect the 3rd switch SW 3, keep the on-state of the 4th switch SW 4 before time point t1, connect octavo and close SW8.

The result, as shown in figure 25, form the current path that closes the scan electrode Y of SW8, the 4th inductor L4, the 9th diode D9 and panel capacitor Cp by ground voltage source, the 4th switch SW 4, the 4th capacitor C4, octavo, and the 4th inductor L4 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and electric current I Cp are by equation 13 expressions.

[equation 13]

$V_p\left(t\right)=\frac{V_s}{4}(1-e^{-{\mathrm{sw}}_{n}t}{\cos w}_{d}t-\frac{{\mathrm{se}}^{{-\mathrm{sw}}_{n}t}}{\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2}}{\sin w}_{d}t)$

${\mathrm{IC}}_p\left(t\right)=\frac{V_s{e}^{{\mathrm{sw}}_{n}t}}{{4\mathrm{Lw}}_d}{\sin w}_{d}t$

Here, $w_n=1/\sqrt{{\mathrm{LC}}_p},s=R_{\mathrm{eq}}\sqrt{C_p/L},w_d=w_n\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2},$ R _EqTotal dead resistance that indication forms in current path.

As a result, at time point t1, the voltage Vp of panel capacitor Cp rises to voltage Vs/2 from ground voltage level GND (0V just).The electric current I L that flows in the 4th inductor L4 rises to And drop to 0 afterwards.

At time point t2, in response to closing control signal from the second switch control signal of the high state of time schedule controller, the 4th switch controlling signal of high state and the octavo of high state, connect second switch SW2, and the 4th switch SW 4 and octavo are closed the on-state that SW8 remains on time point t1.

As a result, as shown in figure 26, form current path by the scan electrode Y of ground voltage source, the 4th switch SW 4, the 4th capacitor C4, the 3rd capacitor C3, second switch SW2 and panel capacitor Cp.

Therefore, the voltage of panel capacitor Cp is maintained on the voltage of Vs/2.Have of the reverse recovery characteristic generation of the reciprocal inductance electric current of predetermined peak value Ir by the 9th diode D9.

This reciprocal inductance electric current closes among SW8, the 4th capacitor C4 and the 11 diode D11 in octavo and flows.The amplitude of reciprocal inductance electric current is represented by equation.

[equation 14]

$I_L\left(t\right)=-I_r+\frac{V_s}{4L}t$

The reciprocal inductance electric current increases with the slope of Vs/4L.The reciprocal inductance electric current descends fast, and does not produce the freewheeling electric current.

At time point t3, in response to closing control signal, the second switch control signal of high state and the 5th switch controlling signal of high state from the 4th switch controlling signal of the low state of time schedule controller, the octavo of low state, second switch SW2 remains on the on-state of time point t2, disconnect the 4th switch SW 4 and octavo and close SW8, connect the 5th switch SW 5.

The result, as shown in figure 27, form current path by the scan electrode Y of ground voltage source, the second capacitor C2, the 3rd diode D3, the first inductor L1, the 5th switch SW 5, the 3rd capacitor C3, second switch SW2 and panel capacitor Cp, and the first inductor L1 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and electric current I Cp are represented by equation.

[equation 15]

$V_p\left(t\right)=\frac{3V_s}{4}(1-e^{-{\mathrm{sw}}_{n}t}{\cos w}_{d}t-\frac{{\mathrm{se}}^{{-\mathrm{sw}}_{n}t}}{\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2}}{\sin w}_{d}t)$

${\mathrm{IC}}_p\left(t\right)=\frac{V_s{e}^{{\mathrm{sw}}_{n}t}}{{4\mathrm{Lw}}_d}{\sin w}_{d}t$

As a result, at time point t3, the voltage Vp of panel capacitor Cp rises to from voltage Vs/2 and keeps voltage Vs.The electric current I L that flows in the first inductor L1 rises to

And drop to 0 afterwards.

At time point t4, in response to first switch controlling signal, the second switch control signal of high state and the 5th switch controlling signal of high state from the high state of time schedule controller, second switch SW2 and the 5th switch SW 5 remain on the on-state of time point t3, and connect first switch SW 1.

As a result, as shown in figure 28, form current path by the scan electrode Y of ground voltage source, the second capacitor C2, the first capacitor C1, first switch SW 1, second switch SW2 and panel capacitor Cp.

Therefore, at time point t4, the voltage of panel capacitor Cp is maintained at keeps voltage Vs.Reciprocal inductance electric current with predetermined peak value Ir is produced by the reverse recovery characteristic of the 3rd diode D3.

The reciprocal inductance electric current flows in the first diode D1, the 3rd capacitor C3 and the 5th switch SW 5.The amplitude of reciprocal inductance electric current is by above-mentioned equation 14 expressions.The reciprocal inductance electric current descends fast, is different from the apparatus for energy recovery of the PDP of prior art, and does not produce the freewheeling electric current.

At time point t5, in response to the 5th switch controlling signal, first switch controlling signal of high state and the second switch control signal of high state from the low state of time schedule controller, the on-state of first switch SW 1 and second switch SW2 retention time point t4, and disconnect the 5th switch SW 5.

As a result, as shown in figure 28, form current path by the scan electrode Y of ground voltage source, the second capacitor C2, the first capacitor C1, first switch SW 1, second switch SW2 and panel capacitor Cp.Therefore, the voltage of panel capacitor Cp is maintained at and keeps voltage Vs.

At time point t6, in response to first switch controlling signal, the second switch control signal of high state and the 6th switch controlling signal of high state from the low state of time schedule controller, the on-state of second switch SW2 retention time point t5 disconnects first switch SW 1, and connects the 6th switch SW 6.

The result, as shown in figure 29, form current path by scan electrode Y, second switch SW2, the 3rd capacitor C3, the 3rd inductor L3, the 4th diode D4, the 6th switch SW 6 and the second capacitor C2 of panel capacitor Cp, and the 3rd inductor L3 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and electric current I Cp are by equation 16 expressions.

[equation 16]

$V_p\left(t\right)=\frac{{3V}_s}{4}(1+e^{-{\mathrm{sw}}_{n}t}{\cos w}_{d}t+\frac{{\mathrm{se}}^{{-\mathrm{sw}}_{n}t}}{\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2}}{\sin w}_{d}t)$

${\mathrm{IC}}_p\left(t\right)=-\frac{V_s{e}^{{\mathrm{sw}}_{n}t}}{{4\mathrm{Lw}}_d}{\sin w}_{d}t$

As a result, at time point t6, the voltage of panel capacitor Cp drops to voltage Vs/2 from keeping voltage Vs.The electric current that flows in the 3rd inductor L3 drops to

And rise to 0 afterwards.

In other words, at time point t6, panel capacitor is emitted voltage Vs/2 keeping among the voltage Vs (it equals the voltage of panel capacitor Cp at time point t4 and t5).The second capacitor C2 reclaims the energy of emitting from panel capacitor Cp.

At time point t7, in response to the 6th switch controlling signal, the second switch control signal of high state and the 4th switch controlling signal of high state from the low state of time schedule controller, second switch SW2 remains on the on-state on the time point t6, disconnects the 6th switch SW 6 and connects the 4th switch SW 4.

As a result, as shown in figure 30, form current path by scan electrode Y, second switch SW2, the 3rd capacitor C3, the 4th capacitor C4, the 4th switch SW 4 and the ground voltage source of panel capacitor Cp.

Therefore, at time point t7, the voltage of panel capacitor Cp is maintained at voltage Vs/2.Have of the reverse recovery characteristic generation of the reciprocal inductance electric current of predetermined peak value Ir by the 4th diode D4.

The reciprocal inductance electric current flows in the 4th capacitor C4 and the 5th diode D5.The amplitude of reciprocal inductance electric current is by above-mentioned equation 14 expressions.The apparatus for energy recovery that is different from prior art PDP, this reciprocal inductance electric current descends fast, and does not produce the freewheeling electric current.

At time point t8, in response to closing control signal from the second switch control signal of the low state of time schedule controller, the 4th switch controlling signal of high state and the minion of high state, the 4th switch SW 4 remains on the on-state on the time point t6, disconnects second switch SW2 and connect minion closing SW7.

The result, as shown in figure 31, form scan electrode Y, the 8th diode D8, the second inductor L2, the minion of passing through panel capacitor Cp and close the current path in SW7, the 4th capacitor C4, the 4th switch SW 4 and ground voltage source, and the second inductor L2 and panel capacitor Cp generation series resonance.At this moment, the voltage Vp of panel capacitor Cp and electric current I Cp are by equation 17 expressions.

[equation 17]

$V_p\left(t\right)=\frac{3V_s}{4}(1-e^{-{\mathrm{sw}}_{n}t}{\cos w}_{d}t-\frac{{\mathrm{se}}^{{-\mathrm{sw}}_{n}t}}{\sqrt{1-{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="A20061010038100631.png,A20061010038100691.png"\; state="\{\{state\}\}">s</figure-callout>}}^2}}{\sin w}_{d}t)$

${\mathrm{IC}}_p\left(t\right)=-\frac{V_s{e}^{{\mathrm{sw}}_{n}t}}{{4\mathrm{Lw}}_d}{\sin w}_{d}t$

As a result, at time point t8, the voltage Vp of panel capacitor Cp drops to ground voltage level GND from voltage Vs/2.The electric current I L that flows in the second inductor L2 drops to

And rise to 0 afterwards.

In other words, at time point t8, panel capacitor Cp discharges and equals the voltage Vs/2 of panel capacitor Cp at the voltage of time point t6.The 4th capacitor C4 reclaims from the energy of panel capacitor Cp discharge.

At time point t9, in response to closing control signal from the 3rd switch controlling signal of the high state of time schedule controller, the 4th switch controlling signal of high state and the minion of high state, the 4th switch SW 4 and minion pass SW7 remain on the on-state on the time point t8, and connect the 3rd switch SW 3.

As a result, shown in figure 32, form current path by scan electrode Y, the 3rd switch SW 3, the 4th switch SW 4 and the ground voltage source of panel capacitor Cp.Therefore, the voltage of panel capacitor Cp is maintained at the ground voltage level of time point t9.

In addition, at time point t9, has the reciprocal inductance electric current of predetermined peak value Ir by the reverse recovery characteristic generation of the 8th diode D8.This reciprocal inductance electric current closes among the SW7 mobile at the 7th diode D7, the 3rd capacitor C3 and minion.The amplitude of reciprocal inductance electric current is by above-mentioned equation 14 expressions.The apparatus for energy recovery that is different from prior art PDP, this reciprocal inductance electric current descends fast, and does not produce the freewheeling electric current.

Afterwards, the switching manipulation of carrying out to t9 at time point t1 of the apparatus for energy recovery of installing among the scan electrode Y that repeats in the apparatus for energy recovery of installing among the electrode Z at PDP keeping of PDP.Therefore, keep electrode Z with what keep that pulse is provided to PDP.

According to embodiments of the invention, reduce current stress on the driving element of apparatus for energy recovery by preventing to produce the freewheeling electric current, reduce power consumption thus.

In addition, because use driving element, reduced the manufacturing cost of plasma display panel device with low withstand voltage condition and low parasitic capacitance.

Describe the present invention like this, clearly can make multiple modification.This modification should not be considered to break away from the spirit and scope of the present invention, and all changes that it will be apparent to those skilled in the art that all are intended to be included among the scope of following claim.

Claims (27)

1. plasma display panel device, it comprises:

Plasmia indicating panel, it comprises scan electrode;

Keep voltage source, be used to provide and keep voltage to Plasmia indicating panel;

Inductor is used for being recovered in the Plasmia indicating panel stored voltage by the resonance of inductor and Plasmia indicating panel, and is used for providing the voltage of recovery to Plasmia indicating panel by the resonance of inductor and Plasmia indicating panel;

Energy provides/reclaims capacitor, be used to form to be used to provide and keep voltage to Plasmia indicating panel/the reclaim current path keep voltage from Plasmia indicating panel, with be used to form be used to provide keep voltage half to Plasmia indicating panel/reclaim its current path from Plasmia indicating panel, this inductor is used to form current path; And

Keep capacitor, it forms keeping between voltage source and the Plasmia indicating panel, is used to form the voltage of keeping Plasmia indicating panel and is keeping half current path of voltage.

2. plasma display panel device as claimed in claim 1, wherein, this energy provides/reclaims capacitor to comprise second capacitor and the 4th capacitor,

Second capacitor is formed for providing keeps voltage to Plasmia indicating panel/reclaim the current path keep voltage from Plasmia indicating panel, and

The 4th capacitor be formed for providing keep voltage half to its current path of Plasmia indicating panel/reclaim from Plasmia indicating panel.

3. plasma display panel device as claimed in claim 1, wherein, this energy provides/reclaims capacitor to comprise the 3rd capacitor, and

Being used to form the voltage of keeping Plasmia indicating panel is the 3rd capacitor at half the capacitor of keeping of current path of keeping voltage.

4. plasma display panel device as claimed in claim 2, wherein, this inductor comprises first inductor and second inductor,

First inductor and second capacitor are formed for providing keeps voltage to Plasmia indicating panel/reclaim its current path from Plasmia indicating panel, and

Second inductor and the 4th capacitor be formed for providing keep voltage half to its current path of Plasmia indicating panel/reclaim from Plasmia indicating panel.

5. plasma display panel device as claimed in claim 2, wherein, this inductor comprises first inductor, second inductor, the 3rd inductor and the 4th inductor,

First inductor and second capacitor are formed for providing keeps the current path of voltage to Plasmia indicating panel,

Second inductor and the 4th capacitor are formed for reclaiming half the current path keep voltage from Plasmia indicating panel,

The 3rd inductor and second capacitor are formed for reclaiming the current path of keeping voltage from Plasmia indicating panel, and

The 4th inductor and the 4th capacitor are formed for providing half current path to Plasmia indicating panel of keeping voltage.

6. plasma display panel device as claimed in claim 1, wherein, this be used to provide keep voltage to the current path of Plasmia indicating panel be used to provide half that keep voltage identical to the current path of Plasmia indicating panel, and

Reclaim the current path keep voltage from Plasmia indicating panel identical with half the current path of keeping voltage from the Plasmia indicating panel recovery.

7. plasma display panel device as claimed in claim 6, wherein, this energy provides/reclaims capacitor to comprise the 3rd capacitor, and

Being used to form the voltage of keeping Plasmia indicating panel is the 3rd capacitor at half the capacitor of keeping of current path of keeping voltage.

8. plasma display panel device comprises:

Plasmia indicating panel, it comprises scan electrode;

First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source;

Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode;

Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode;

The 3rd capacitor, it is connected keeps voltage and provides control module and ground voltage to provide between the control module;

Energy provides control module, and it is connected between the common port and scan electrode of first capacitor and second capacitor, is used for controlling being provided at energy that second capacitor stores to scan electrode;

Energy recovery control module, itself and energy provide between the common port and scan electrode that control module is connected in first capacitor and second capacitor in parallel, and being used to control provides the energy that reclaims from the scan electrode of Plasmia indicating panel to second capacitor; With

First inductor, it is connected energy and provides between the common port and scan electrode of control module and energy recovery control module.

9. plasma display panel device as claimed in claim 8, wherein, this keeps voltage provides control module to comprise first switch and the 3rd switch, and it is connected in series in keeps between voltage source and the scan electrode, and

Ground voltage provides control module to comprise second switch and the 4th switch, and it is connected in series between ground voltage source and the scan electrode.

10. plasma display panel device as claimed in claim 9, wherein, the 3rd capacitor is connected between the common port of the common port of first switch and the 3rd switch and second switch and the 4th switch.

11. plasma display panel device as claimed in claim 8, wherein, this energy provides control module to comprise and is connected the common port of first capacitor and second capacitor and the 5th switch between the inductor.

12. plasma display panel device as claimed in claim 8, wherein, this energy recovery control module comprises the common port that is connected first capacitor and second capacitor and the 6th switch between the inductor.

13. a plasma display panel device comprises:

Plasmia indicating panel, it comprises scan electrode;

First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source;

Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode;

Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode;

The 3rd capacitor and the 4th capacitor, it is connected in series in keeps voltage and provides control module and ground voltage to provide between the control module;

First inductor, it is connected between the common port of the common port of first capacitor and second capacitor and the 3rd capacitor and the 4th capacitor;

The first energy recovery control module and second energy provide control module, and it is connected in parallel between the common port and first inductor of first capacitor and second capacitor;

Second inductor, it is connected between the common port and scan electrode of the 3rd capacitor and the 4th capacitor; With

First energy provides the control module and the second energy recovery control module, and it is connected in parallel between first inductor and second inductor.

14. plasma display panel device as claimed in claim 13, wherein, this keeps voltage provides control module to comprise first switch and second switch, and it is connected in series in keeps between voltage source and the scan electrode, and

Ground voltage provides control module to comprise the 3rd switch and the 4th switch, and it is connected in series between ground voltage source and the scan electrode.

15. plasma display panel device as claimed in claim 13, wherein, this first energy provides control module to comprise the 5th switch and first diode, and it is connected between first inductor and second inductor.

16. plasma display panel device as claimed in claim 13, wherein, this second energy provides control module to comprise the 6th switch and second diode, and it is connected between the common port and first inductor of first capacitor and second capacitor.

17. plasma display panel device as claimed in claim 13, wherein, this first energy recovery control module comprises minion pass and the 3rd diode, and it is connected between the common port and first inductor of first capacitor and second capacitor.

18. plasma display panel device as claimed in claim 13, wherein, this second energy recovery control module comprises octavo pass and the 4th diode, and it is connected between first inductor and second inductor.

19. plasma display panel device as claimed in claim 13, wherein, this voltage that is charged to first capacitor equals to keep 50% of voltage, and the voltage that is charged to second capacitor equals to keep 50% of voltage, and

The voltage that is charged to the 3rd capacitor equals to keep 25% of voltage, and the voltage that is charged to the 4th capacitor equals to keep 25% of voltage.

20. a plasma display panel device comprises:

Plasmia indicating panel, it comprises scan electrode;

First capacitor and second capacitor, it is connected keeps between voltage source and the ground voltage source;

Keep voltage control module is provided, it is connected keeps between voltage source and the scan electrode, is used for controlling to provide keeping voltage to scan electrode;

Ground voltage provides control module, and it is connected between ground voltage source and the scan electrode, and being used for control provides ground voltage level to arrive scan electrode;

The 3rd capacitor and the 4th capacitor, it is connected in series in keeps voltage and provides control module and ground voltage to provide between the control module;

First energy provides the control module and the first energy recovery control module, and it is connected in parallel between the common port of the common port of first capacitor and second capacitor and the 3rd capacitor and the 4th capacitor; With

Second energy provides the control module and the second energy recovery control module, and it is connected in parallel between the common port and scan electrode of the 3rd capacitor and the 4th capacitor.

21. plasma display panel device as claimed in claim 20, wherein, this is kept voltage and provides control module to comprise to be connected first switch of keeping between voltage source and the 3rd capacitor, and is connected the second switch between the 3rd capacitor and the scan electrode, and

This ground voltage provides control module to comprise to be connected the 3rd switch between ground voltage source and the 4th capacitor, and is connected the 4th switch between the 4th capacitor and the scan electrode.

22. plasma display panel device as claimed in claim 21, wherein, this second energy provides control module to comprise to be connected the 5th switch between the common port of the common port of the 3rd capacitor and the 4th capacitor and first switch and second switch, and is connected the common port of first capacitor and second capacitor and first inductor between the 5th switch.

23. plasma display panel device as claimed in claim 21, wherein, this first energy recovery control module comprises the 6th switch between the common port of the common port that is connected the 3rd switch and the 4th switch and first capacitor and second capacitor, and is connected the common port of the 3rd capacitor and the 4th capacitor and the 3rd inductor between the 6th switch.

24. plasma display panel device as claimed in claim 21, wherein, this second energy recovery control module comprises second inductor between the common port of the common port that is connected first switch and second switch and second switch and scan electrode, and the common port and the minion between second inductor that are connected the 3rd capacitor and the 4th capacitor are closed.

25. plasma display panel device as claimed in claim 21, wherein, this first energy provides control module to comprise to be connected the octavo between the common port of the common port of the 3rd capacitor and the 4th capacitor and the 3rd switch and the 4th switch to close, and is connected the common port of the 3rd switch and scan electrode and octavo the 4th inductor between closing.

26. plasma display panel device as claimed in claim 20, wherein, this voltage that is charged to first capacitor equals to keep 50% of voltage, and the voltage that is charged to second capacitor equals to keep 50% of voltage, and

The voltage that is charged to the 3rd capacitor equals to keep 25% of voltage, and the voltage that is charged to the 4th capacitor equals to keep 25% of voltage.

27. a method that drives plasma display panel device comprises:

The voltage of the scan electrode of Plasmia indicating panel is increased to half that keep voltage from ground voltage level;

The voltage of keeping this scan electrode is being kept half of voltage;

The voltage of scan electrode is increased to from half that keep voltage keeps voltage;

Keep the voltage of this scan electrode and keeping voltage;

The voltage of scan electrode is reduced to half that keep voltage from keeping voltage; With

The voltage of scan electrode is reduced to ground voltage level from half that keep voltage.

Images