CN1889272A - Display device panel structure and producing method thereof - Google Patents
Display device panel structure and producing method thereof Download PDFInfo
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- CN1889272A CN1889272A CN 200610103758 CN200610103758A CN1889272A CN 1889272 A CN1889272 A CN 1889272A CN 200610103758 CN200610103758 CN 200610103758 CN 200610103758 A CN200610103758 A CN 200610103758A CN 1889272 A CN1889272 A CN 1889272A
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- 238000000034 method Methods 0.000 title claims description 32
- 239000000463 material Substances 0.000 claims abstract description 92
- 239000010949 copper Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 229910052802 copper Inorganic materials 0.000 claims abstract description 59
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000000203 mixture Substances 0.000 claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000376 reactant Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 289
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 117
- 239000006104 solid solution Substances 0.000 claims description 80
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 45
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- 239000007789 gas Substances 0.000 claims description 31
- 230000004888 barrier function Effects 0.000 claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000002344 surface layer Substances 0.000 claims description 25
- 229910052757 nitrogen Inorganic materials 0.000 claims description 24
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- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
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- ZXOBQYMIGLRFOL-UHFFFAOYSA-N [Cu].O=[N] Chemical compound [Cu].O=[N] ZXOBQYMIGLRFOL-UHFFFAOYSA-N 0.000 claims description 13
- CMPNPRUFRJFQIB-UHFFFAOYSA-N [N].[Cu] Chemical compound [N].[Cu] CMPNPRUFRJFQIB-UHFFFAOYSA-N 0.000 claims description 13
- XYQGTTDSDCKKFV-UHFFFAOYSA-N [O].[N].[Cu] Chemical compound [O].[N].[Cu] XYQGTTDSDCKKFV-UHFFFAOYSA-N 0.000 claims description 13
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- 239000004332 silver Substances 0.000 claims description 12
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 11
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- 229910052738 indium Inorganic materials 0.000 claims description 11
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- 229910052741 iridium Inorganic materials 0.000 claims description 11
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- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims description 11
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- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides display unit panel and circuit component structure and manufacturing method. Display unit panel mainly includes substrate and circuit component formed on substrate, wherein said circuit component including first boundary layer and first conducting layer, all formed from copper containing material, the first boundary layer material at least including first conducting layer formed material's reactant or mixture. Said Manufacturing method mainly includes: firstly forming first boundary layer on substrate, forming first conducting layer on first boundary layer, and etching first conducting layer and first boundary layer for forming pattern. Through setting first boundary layer, it can reduce diffusing infiltration substrate status in forming first conducting layer, capable of raising first conducting layer with substrate adhesion strength.
Description
Technical field
The present invention relates to a kind of display device panel structure and manufacture method thereof; Particularly, the present invention relates to the structure and the manufacture method of a kind of display device panel and last circuit element thereof.
Background technology
Along with the epoch transition, common people increase day by day to the requirement of enjoying in the audiovisual.Especially because of the fast development of science and technology, various display unit is there's no one who doesn't or isn't exported the emphasis of the area of picture as research and development with increase.Particularly in the panel display field, the size that how to increase display floater always is the target that all big enterprises make great efforts.
Along with the increase of size of display panels, the resistance of the aluminum or aluminum alloy electrode of Shi Yonging has not been inconsistent demand traditionally.For asking the reduction of electrode resistance, essential in design silver or the copper of adopting is as the material that replaces.Owing to use the cost of silver-colored material as an alternative too expensive, make the product of making lack the market competitiveness, as if copper becomes does not make second preferred material of selecting.Yet use copper material as an alternative still has its restriction and problem to exist.At first,, make the copper film that is formed on the substrate peel off easily because the adhesive force between copper and glass substrate or plastic material substrate is relatively poor, can't be by the test of adhesive force.In addition,, cause when being deposited on the plastic material substrate and easily invade in the substrate, influence the quality of finished product because the diffusion coefficient of copper is bigger.
Above-mentioned adhesive force test mainly comprises adhesive tape test and tensile test.In so-called adhesive tape test, at first need to be divided into 100 tiny grids with blade being formed on the film of substrate, then use specific adhesive tape sticking that industry generally acknowledges on it, and pull-up fast.Test result is calculated the grade of adhesive force between film and substrate with the frame counter that glued by adhesive tape, and generally speaking, the lattice number that is pulled up needs comparatively desirable below 5% at total lattice number.So-called tensile test then is that the probe that will have certain contact area is adhered on the film that is formed on substrate.Follow fixing base, and film is imposed pulling force by probe.Test result then be pulling force when destroy taking place as the amount of commenting, generally speaking reach 200 newton when above destroying pulling force, the adhesive force of film and substrate is ideal comparatively.
As shown in Figure 1, for overcoming the shortcoming of above-mentioned use copper film, generate separator 20 at substrate 10 and 30 of copper films traditionally.The setting of separator 20 can increase the adhesive force of 10 of copper film 30 and substrates really, makes it to test by adhesive force.When depositing, separator 20 also can effectively reduce the diffusion velocity of copper.Yet the technology of separator 20 often makes whole process complications, causes the increase of time and money cost.In addition, when carrying out etch process, because the otherness of separator 20 and 30 materials of copper film, need the in addition etching of the different etching condition of employing, and easily cause residual and so on etch issues, increased the fraction defective of product.
Summary of the invention
The object of the present invention is to provide a kind of display device panel structure and on circuit element, have lower grid conducting layer resistance value.
Another object of the present invention is to provide a kind of display device panel structure and on circuit element, have good copper film adhesive force.
Another object of the present invention is to provide a kind of display device panel structure manufacture method, have the processing step of simplifying.
Display device panel structure of the present invention mainly comprises substrate and circuit element.Circuit element comprises first boundary layer and first conductive layer.In a preferred embodiment, first boundary layer is formed directly on the inner surface of substrate; Yet in different embodiment, first boundary layer also can be formed on other metal or non-metallic layer on the substrate inner surface.The material of first boundary layer comprise following composition one of them: copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide and copper alloy nitrogen oxide.
First conductive layer is formed on first boundary layer, and its material then is fine copper, copper alloy or its mixture.In addition, the material that forms first boundary layer need comprise reactant or the mixture that forms first conductive at least.Because the material of first boundary layer and first conductive layer has above-mentioned intercommunity, therefore be able in single etching step, simultaneously first boundary layer and first conductive layer be carried out etching.By the setting of first boundary layer, reduced the situation that substrate is infiltrated in the diffusion when forming of first conductive layer.In addition, first boundary layer have an adhesive strength that helps improve first conductive layer and substrate, reduce the possibility of first conductive layer from strippable substrate.
In a preferred embodiment, circuit element forms the amorphous silicon thin-film transistor, and also comprises insulating barrier, semiconductor layer, ohmic contact layer, source electrode and drain electrode.Insulating barrier covers the grid that is made of first conductive layer and first boundary layer, and covers the substrate inner surface that expose to the open air the first boundary layer both sides.Semiconductor layer covers insulating barrier, and relative with the common grid that forms of first boundary layer with first conductive layer.Ohmic contact layer comprises source electrode ohmic contact layer and drain electrode ohmic contact layer.The source electrode ohmic contact layer is connected the two ends of semiconductor layer respectively with the drain electrode ohmic contact layer.Source electrode covers the source electrode ohmic contact layer, and drain electrode then covers the drain electrode ohmic contact layer.
Manufacture method of the present invention mainly may further comprise the steps: at first form first boundary layer on substrate, wherein the material of first boundary layer is copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide, copper alloy nitrogen oxide or its composition.Then form first conductive layer on first boundary layer.The material of first conductive layer is copper, copper alloy or its mixture, and the material of first boundary layer comprise at least the reactant of first conductive or mixture one of them.Be that etching first conductive layer and first boundary layer are to form etched pattern at last.Because the material of first boundary layer mainly comprises reactant or the mixture that forms first conductive, therefore be able in single etching step, simultaneously first boundary layer and first conductive layer be carried out etching with the same etch condition.
In a preferred embodiment, first boundary layer forms step can be divided into several steps, and comprising: excite base material to produce free base material in reative cell, wherein base material is copper or copper alloy; Importing and provocative reaction gas are to produce free gas in reative cell, and wherein reacting gas is nitrogen, oxygen or nitrogen oxygen mixed gas; And attract the composition of free base material and free gas to be deposited on the substrate, to form first boundary layer.First conductive layer forms step then can be divided into following two steps: stop to import reacting gas and enter reative cell to stop the generation of first boundary layer; And attract the composition of free base material to be deposited on the substrate, to form first conductive layer.
Description of drawings
Fig. 1 is the schematic diagram of display device panel and thin-film transistor in the prior art;
Fig. 2 is the schematic diagram of the embodiment of display device panel structure of the present invention;
Fig. 3 a is the schematic diagram that is applied to the embodiment of amorphous silicon thin-film transistor;
Fig. 3 b is the schematic diagram that is applied to another embodiment of amorphous silicon thin-film transistor;
Fig. 3 c is depicted as another amorphous silicon thin-film transistor embodiment that adopts the bottom gate design.
Fig. 4 a is the schematic diagram of embodiment that is applied to the amorphous silicon thin-film transistor of top gate design;
Fig. 4 b is the schematic diagram of another embodiment that is applied to the amorphous silicon thin-film transistor of top gate design;
Fig. 4 c is the schematic diagram that is applied to another embodiment of amorphous silicon thin-film transistor;
Fig. 5 is the flow chart of the embodiment of display device panel structure manufacture method of the present invention;
Fig. 6 is the flow chart of another embodiment of display device panel structure manufacture method of the present invention;
Fig. 7 is the schematic diagram of the equipment of display device panel structure manufacture method of the present invention.
The simple symbol explanation
10 substrates, 20 separators
30 copper films, 100 substrates
110 inner surfaces, 300 circuit elements
310 first boundary layers, 311 sidewalls
330 first conductive layers, 331 sidewalls
340 insulating barriers, 350 semiconductor layers
360 ohmic contact layers, 361 source electrode ohmic contact layers
363 drain electrode ohmic contact layers, 370 source electrodes
380 drain electrodes, 390 grids
410 second contact surface layers, 430 second conductive layer
450 the 3rd boundary layers, 700 reative cells
710 base materials, 730 device for generating voltage
751 mechanical pumps, 753 diffusion pumps
Embodiment
The invention provides a kind of display device panel structure and manufacture method thereof.In a preferred embodiment, this display device panel structure comprises the display floater of liquid crystal indicator; Yet display device panel structure also can comprise the panel structure of organic LED display device or other display unit in different embodiment.
Figure 2 shows that the embodiment of display device panel structure of the present invention.In this embodiment, display device panel structure mainly comprises substrate 100 and circuit element 300.Substrate 100 is preferably the formed glass substrate of glass; Yet in different embodiment, substrate 100 also can adopt by the formed polymeric substrates of polymer, for example plastic base.In addition, circuit element 300 preferably includes transistor, for example amorphous silicon thin-film transistor (a-Si Thin-Film-Transistor, a-Si TFT) or many silicon thin film transistors (p-SiTFT).Yet in different embodiment, circuit element 300 also can be MIM-TFD circuit or other different circuit element.
In a preferred embodiment, the thickness of first boundary layer 310 between 1 nanometer (nm) between 100 nanometers (nm).Yet in different embodiment, further the thickness of limit first boundary layer 310 between 3 nanometers (nm) between 50 nanometers (nm).The material of first boundary layer 310 comprise following composition one of them: copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide and copper alloy nitrogen oxide.First boundary layer 310 also can be combined by above-mentioned composition.In addition, in a preferred embodiment, one of them is synthesized at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal for above-mentioned copper alloy.The cupric ratio of copper alloy is preferably greater than 50 moles of % (mol%); Yet in a particular embodiment, the cupric ratio of copper alloy is preferably greater than 90 moles of %.Look what of the difference that forms material and copper content, first boundary layer 310 can be for having conductivity or insulating properties.
As shown in Figure 2, first conductive layer 330 is formed directly on first boundary layer 310, and forms etched patterns jointly with first boundary layer 310.In other words, the sidewall 311 that forms after sidewall 331 that forms after 330 etchings of first conductive layer and 310 etchings of first boundary layer is continuous.In a preferred embodiment, first conductive layer 330 can the physical vapor deposition (PVD) mode, and for example sputtering technology is formed on first boundary layer 310; Yet in different embodiment, first conductive layer 330 also can chemical vapor deposition (CVD) or alternate manner be formed on first boundary layer 310.
In a preferred embodiment, the material of first conductive layer 330 is fine copper, copper alloy or its mixture.The material that forms first boundary layer 310 need comprise reactant or the mixture that forms first conductive layer, 330 materials at least.In other words, form the material of first boundary layer 310 by forming first conductive layer, 330 materials and other element reaction or mixing.For example when first conductive layer 330 is formed by fine copper, 310 of first boundary layers are mixed or react formed material with oxonium ion, nitrogen ion or nitrogen oxonium ion by copper and constituted.Because the material of first boundary layer 310 and first conductive layer 330 has above-mentioned intercommunity, therefore be able in single etching step, simultaneously first boundary layer 310 and first conductive layer 330 be carried out etching.In addition, in a preferred embodiment, one of them is synthesized at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal for above-mentioned copper alloy.The cupric ratio of copper alloy is preferably greater than 50 moles of % (mol%); Yet in a particular embodiment, the cupric ratio of copper alloy is preferably greater than 90 moles of %.
In the embodiment shown in Fig. 3 a, circuit element 300 is the amorphous silicon thin-film transistor, and adopts the bottom gate design.In this embodiment, first boundary layer 310 and first conductive layer, the 330 common etched patterns that form form the grid in the circuit element 300.Circuit element 300 also comprises insulating barrier 340, semiconductor layer 350, ohmic contact layer 360, source electrode 370 and drains 380.The grid that insulating barrier 340 covering first conductive layers 330 and first boundary layer 310 are constituted, and cover substrate 100 inner surfaces 110 that expose to the open air first boundary layer, 310 both sides.In a preferred embodiment, insulating barrier 340 is preferably formed by oxygen silicon compound or nitrogen silicon compound.
By the setting of first boundary layer 310, reduced the situation that substrate 100 is infiltrated in the diffusion when forming of first conductive layer 330.In addition, the adhesive strength that the having of first boundary layer 310 helps to improve first conductive layer 330 and substrate reduces the possibility that first conductive layer 330 is peeled off from substrate 100.
Fig. 3 b adopts the amorphous silicon thin-film transistor embodiment of bottom gate design for another.In this embodiment, source electrode 370 and drain electrode 380 comprise the second contact surface layer 410 and second conductive layer 430 respectively.Second contact surface layer 410 is positioned at the bottom surface of source electrode 370 and drain electrode 380, and is formed on the ohmic contact layer 360.The material of second contact surface layer 410 comprise following composition one of them: copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide and copper alloy nitrogen oxide.Second contact surface layer 410 also can be combined by above-mentioned composition.In addition, in a preferred embodiment, one of them is synthesized at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal for above-mentioned copper alloy.The cupric ratio of copper alloy is preferably greater than 50 moles of % (mol%); Yet in a particular embodiment, the cupric ratio of copper alloy is preferably greater than 90 moles of %.Look what of the difference that forms material and copper content, second contact surface layer 410 can be for having conductivity or insulating properties.In addition, the thickness limits scope of the thickness limits scope of second contact surface layer 410 and first boundary layer 310 is approximate.
Second conductive layer 430 is formed directly on the second contact surface layer 410, and forms etched patterns jointly with second contact surface layer 410.In a preferred embodiment, second conductive layer 430 can the physical vapor deposition (PVD) mode, and for example sputtering technology is formed on the second contact surface layer 410; Yet in different embodiment, second conductive layer 430 also can chemical vapor deposition (CVD) or alternate manner be formed on the second contact surface layer 410.
In a preferred embodiment, the material of second conductive layer 430 is fine copper, copper alloy or its mixture.The material that forms second contact surface layer 410 need comprise reactant or the mixture that forms second conductive layer, 430 materials at least.In other words, form the material of second contact surface layer 410 by forming second conductive layer, 430 materials and other element reaction or mixing.For example when second conductive layer 430 is formed by fine copper, 410 on second contact surface layer is mixed or reacts formed material with oxonium ion, nitrogen ion or nitrogen oxonium ion by copper and constituted.Because the material of the second contact surface layer 410 and second conductive layer 430 has above-mentioned intercommunity, therefore be able in single etching step, simultaneously the second contact surface layer 410 and second conductive layer 430 be carried out etching.In addition, in a preferred embodiment, one of them is synthesized at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal for above-mentioned copper alloy.The cupric ratio of copper alloy is preferably greater than 50 moles of % (mo1%); Yet in a particular embodiment, the cupric ratio of copper alloy is preferably greater than 90 moles of %.
Fig. 3 c is depicted as another amorphous silicon thin-film transistor embodiment that adopts the bottom gate design.In this embodiment, 340 of first conductive layer 330 and insulating barriers are provided with the 3rd boundary layer 450.The 3rd boundary layer 450 preferably is formed directly on first conductive layer 330.Its generation type comprises physical gas-phase deposition, chemical vapor deposition method or other different technology mode.Insulating barrier 340 directly overlays on the 3rd boundary layer 450, makes the end face of the 3rd boundary layer 450 be connected the insulating barrier 340 and first conductive layer 330 respectively with the bottom surface.By the setting of the 3rd boundary layer 450, can increase the bond strength of 340 of first conductive layer 330 and insulating barriers.
The material of the 3rd boundary layer 450 comprise following composition one of them: copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide and copper alloy nitrogen oxide.The 3rd boundary layer 450 also can be combined by above-mentioned composition.In addition, in a preferred embodiment, one of them is synthesized at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal for above-mentioned copper alloy.Must it should be noted that the material that forms the 3rd boundary layer 450 need comprise reactant or the mixture that forms first conductive layer, 330 materials at least.In other words, form the material of the 3rd boundary layer 450 by forming first conductive layer, 330 materials and other element reaction or mixing.
Fig. 4 a is depicted as another embodiment of the present invention, and amorphous silicon thin-film transistor in this embodiment is to adopt the top gate design.Shown in Fig. 4 a, first boundary layer 310 and first conductive layer 330 are formed directly on the inner surface 110 of substrate 100 with as source electrode 370 and drain electrode 380.Through behind the etch process, source electrode 370 and 380 of drain electrodes are formed with at interval.Ohmic contact layer 360 comprises source electrode ohmic contact layer 361 and drain electrode ohmic contact layer 363, and part covers source electrode 370 and drain electrode 380 respectively.In a preferred embodiment, ohmic contact layer 360 is phosphorus amorphous silicon (n+a-Si) layer.Semiconductor layer 350 covers source electrode ohmic contact layer 361 and drain electrode ohmic contact layer 363.Semiconductor layer 350 covers source electrode 370 and 380 substrate that exposes to the open air 100 inner surfaces 110 of drain electrode.In this preferred embodiment, semiconductor layer 350 is amorphous silicon (a-Si) layer.Insulating barrier 340 covers on the semiconductor layer 350.Insulating barrier 340 is preferably formed by oxygen silicon compound or nitrogen silicon compound.Grid 390 is formed directly on the insulating barrier 340, and is preferably the depositing metal layers after the etching.
Fig. 4 b adopts the amorphous silicon thin-film transistor embodiment of top gate design for another.In this embodiment, grid 390 comprises the second contact surface layer 410 and second conductive layer 430 respectively.Second contact surface layer 410 is formed on the insulating barrier 340, and its main material comprises copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide or copper alloy nitrogen oxide.Second conductive layer 430 is formed directly on the second contact surface layer 410, and its material mainly comprises copper or copper alloy.
In another embodiment, shown in Fig. 4 c, be provided with semiconductor layer 350 between the substrate 100 and first boundary layer 310.Semiconductor layer 350 is formed on the substrate 100, and its material is preferably amorphous silicon (a-Si) layer.Source electrode ohmic contact layer 361 is formed on the semiconductor layer 350 with drain electrode ohmic contact layer 363, and respectively between semiconductor layer 350 and source electrode 370 and drain electrode 380.In a preferred embodiment, source electrode ohmic contact layer 361 is phosphorus amorphous silicon (n+a-Si) layer with drain electrode ohmic contact layer 363.Insulating barrier 340 parts cover first conductive layer 330; In other words, insulating barrier 340 parts cover the upper surface of source electrode 370 and drain electrode 380.390 of grids are formed on insulating barrier 340 tops, and are positioned at the centre of source electrode 370 and drain electrode 380.
Figure 5 shows that the flow chart of the manufacture method embodiment of display device panel structure and last circuit element thereof.As shown in Figure 5, step 501 comprises that formation first boundary layer 310 is on substrate 100.In this step, preferably use the physical vapor deposition (PVD) mode, for example sputtering technology forms first boundary layer 310 on substrate 100; Yet in different embodiment, first boundary layer 310 also can chemical vapor deposition (CVD) or alternate manner be formed on the substrate 100.In addition, also comprise in the step 501 control first boundary layer 310 thickness between 1 nanometer (nm) between 100 nanometers (nm).Yet in different embodiment, the thickness that can further control first boundary layer 310 between 3 nanometers (nm) between 50 nanometers (nm).
The material of first boundary layer 310 comprise following composition one of them: copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide and copper alloy nitrogen oxide.First boundary layer 310 also can be combined by above-mentioned composition.In addition, in a preferred embodiment, one of them is synthesized at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal for above-mentioned copper alloy.The cupric ratio of copper alloy is preferably greater than 50 moles of % (mol%); Yet in a particular embodiment, the cupric ratio of copper alloy is preferably greater than 90 moles of %.
Step 503 comprises that formation first conductive layer 330 is on first boundary layer 310.In this step, preferably use the physical vapor deposition (PVD) mode, for example sputtering technology is formed on first conductive layer 330 on first boundary layer 310; Yet in different embodiment, first conductive layer, 330 first boundary layers 310 also can chemical vapor deposition (CVD) or alternate manner be formed on first boundary layer 310.In addition, the employed technology mode of step 503 is preferably identical with the technology mode that step 501 is used, to simplify overall flow.
The material of first conductive layer 330 is fine copper, copper alloy or its mixture.The material that forms first boundary layer 310 need comprise reactant or the mixture that forms first conductive layer, 330 materials at least.In other words, form the material of first boundary layer 310 by forming first conductive layer, 330 materials and other element reaction or mixing.For example when first conductive layer 330 is formed by fine copper, 310 of first boundary layers are mixed or react formed material with oxonium ion, nitrogen ion or nitrogen oxonium ion by copper and constituted.In addition, in a preferred embodiment, one of them is synthesized at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal for above-mentioned copper alloy.The cupric ratio of copper alloy is preferably greater than 50 moles of % (mol%); Yet in a particular embodiment, the cupric ratio of copper alloy is preferably greater than 90 moles of %.
Step 505 comprises that etching first conductive layer 330 and first boundary layer 310 are to form etched pattern.Because the material of first boundary layer 310 mainly comprises reactant or the mixture that forms first conductive layer, 330 materials, step 505 is able to simultaneously first boundary layer 310 and first conductive layer 330 be carried out etching with the same etch condition in single etching step.
Figure 6 shows that the flow chart of another embodiment of manufacture method of the present invention.In this embodiment, first boundary layer forms step 501 and includes several steps: step 5011 is to excite base material to produce free base material in reative cell, and wherein base material is copper or copper alloy.In a preferred embodiment, one of them is synthesized copper alloy at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal.The cupric ratio of copper alloy is preferably greater than 50 moles of % (mol%); Yet in a particular embodiment, the cupric ratio of copper alloy is preferably greater than 90 moles of %.
With the sputtering technology is example, as shown in Figure 7, is to clash into base material 710 to produce free base material with the energetic ion group in reative cell 700.In the embodiment shown in fig. 7, be in reative cell 700, to import argon gas, in reative cell 700, produce electric field with device for generating voltage 730 again, and with the argon gas ionization that imports to form the energetic ion group.For reaction is carried out smoothly, reative cell 700 also uses mechanical pump 751 and the state of diffusion pump 753 manufacturing near vacuum.Yet in different embodiment, for example when using chemical vapor deposition method or plasma fortified chemical vapor deposition method, this step 5011 also can be utilized and apply heat energy or electric energy is free base material to excite base material.
In the embodiment shown in fig. 6, first conductive layer formation step can be divided into following two steps: step 5031 comprises that stopping to import reacting gas enters reative cell 700.In a preferred embodiment, this step is that the deposit thickness at first boundary layer 310 reaches expection and carries out when requiring, with the generation that stops first boundary layer 310 and the increase of deposit thickness.Step 5033 item comprises and to attract the composition of free base material to be deposited on first boundary layer 310, to form first conductive layer 330.In this step, owing to stopped the importing of reacting gas, therefore the free base material that is excited can't react with reacting gas or mix, and be deposited on the substrate 100 to generate first conductive layer 330 by the electric field guiding.
In addition, if when wanting to increase the adhesion of first conductive layer 330 and other layer materials, also can above first conductive layer 330, form inferior boundary layer.With regard to the embodiment of Fig. 6, when step 5033 proceeds to first conductive layer 330 that forms adequate thickness, import reacting gas once more and enter reative cell 700 and excited.The free gas cognition that be excited this moment is reacted with the base material that dissociates or is mixed.Then attract the composition of free base material and free gas to be deposited on first conductive layer 330, to form time boundary layer.
By the embodiment flow chart of Fig. 6 as can be known, generating first boundary layer 310 or generating in the technology of first conductive layer 330, in reative cell 700, all using single base material 710 no matter be.So can reduce because of using the process complexity and the loss of time that different substrate materials 710 increases instead.In addition, when the importing pressure of oxygen preferably approximately greater than the importing pressure of 1.3mTorr or nitrogen during preferably approximately greater than 3mTorr, 100 adhesive force of first conductive layer 330 and substrate can reach the above tension intensity of 220 newton.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present invention.Must be pointed out that the embodiment that has disclosed does not limit the scope of the invention.On the contrary, modification and impartial setting that is included in the spirit and scope of claim includes within the scope of the invention.
Claims (27)
1, a kind of display device panel structure comprises:
Substrate;
First boundary layer, be arranged on this substrate top, and the material of this first boundary layer comprises copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide or copper alloy nitrogen oxide; With
First conductive layer be formed on this first boundary layer, and the material of this first conductive layer comprises copper or copper alloy.
2, display device panel structure as claimed in claim 1, wherein this first boundary layer and this first conductive layer form grid jointly.
3, display device panel structure as claimed in claim 2 also comprises:
Insulating barrier covers this grid;
Semiconductor layer covers this insulating barrier, and corresponding to this grid;
Ohmic contact layer comprises source electrode ohmic contact layer and drain electrode ohmic contact layer, connects the two ends of this semiconductor layer respectively;
Source electrode covers this source electrode ohmic contact layer; With
Drain electrode covers this drain electrode ohmic contact layer.
4, display device panel structure as claimed in claim 3, wherein this source electrode and this drain electrode comprise respectively:
The second contact surface layer, be formed on this ohmic contact layer, and the material of this second contact surface layer comprises copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide or copper alloy nitrogen oxide; With
Second conductive layer be formed on this second contact surface layer, and the material of this second conductive layer comprises copper or copper alloy.
5, display device panel structure as claimed in claim 3 also comprises the 3rd boundary layer, and the 3rd boundary layer and connects this first conductive layer and this insulating barrier respectively between this first conductive layer and this insulating barrier; Wherein the material of the 3rd boundary layer comprises copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide or copper alloy nitrogen oxide.
6, display device panel structure as claimed in claim 1, wherein this first boundary layer and this first conductive layer form source electrode and drain electrode jointly.
7, display device panel structure as claimed in claim 6 also comprises:
The source electrode ohmic contact layer, part covers this source electrode;
The drain electrode ohmic contact layer, part covers this drain electrode;
Semiconductor layer covers this source electrode ohmic contact layer and this drain electrode ohmic contact layer;
Insulating barrier covers this semiconductor layer; With
Grid is formed on this insulating barrier top.
8, display device panel structure as claimed in claim 7, wherein this grid comprises:
The second contact surface layer, be formed on this insulating barrier, and the material of this second contact surface layer comprises copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide or copper alloy nitrogen oxide; With
Second conductive layer be formed on this second contact surface layer, and the material of this second conductive layer comprises copper or copper alloy.
9, display device panel structure as claimed in claim 6 also comprises:
Semiconductor layer is formed on this substrate, and between this substrate and this first boundary layer;
The source electrode ohmic contact layer is formed on this semiconductor layer, and between this semiconductor layer and this source electrode;
The drain electrode ohmic contact layer is formed on this semiconductor layer, and between this semiconductor layer and this drain electrode;
Insulating barrier, part covers this first conductive layer; With
Grid is formed on this insulating barrier top.
10, display device panel structure as claimed in claim 1, wherein this first boundary layer has conductivity.
11, display device panel structure as claimed in claim 1, wherein this first boundary layer is an insulating barrier.
12, display device panel structure as claimed in claim 1, wherein this substrate comprises glass substrate or polymeric substrates.
13, display device panel structure as claimed in claim 1, wherein the thickness of this first boundary layer is between 1 nanometer to 100 nanometer.
14, display device panel structure as claimed in claim 13, wherein the thickness of this first boundary layer is between 3 nanometer to 50 nanometers.
15, display device panel structure as claimed in claim 1, wherein one of them is synthesized this copper alloy at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal.
16, display device panel structure as claimed in claim 1, wherein the cupric ratio of this copper alloy is greater than 50 moles of %.
17, display device panel structure as claimed in claim 16, wherein the cupric ratio of this copper alloy is greater than 90 moles of %.
18, a kind of manufacture method of display device panel structure comprises the following steps:
Form boundary layer on substrate, wherein the material of this boundary layer comprise at least copper oxygen solid solution, copper nitrogen solid solution, copper nitrogen oxygen solid solution, copper alloy oxygen solid solution, copper alloy nitrogen solid solution, copper alloy nitrogen oxygen solid solution, Cu oxide, copper alloy oxide, copper nitride, copper alloy nitride, copper nitrogen oxide and copper alloy nitrogen oxide one of them;
Form conductive layer on this boundary layer, wherein the material of this conductive layer comprise at least copper and copper alloy one of them, and the material of this boundary layer comprise at least the reactant of this conductive and mixture one of them; And
This conductive layer of etching and this boundary layer are to form etched pattern.
19, the manufacture method of display device panel structure as claimed in claim 18, wherein this boundary layer formation step also comprises the following steps:
In reative cell, excite base material to produce free base material, wherein this base material comprise copper and copper alloy one of them;
In this reative cell, import and provocative reaction gas to produce free gas, wherein this reacting gas comprise at least nitrogen, oxygen and nitrogen oxygen mixed gas one of them; And
Attract the composition of this free base material and this free gas to be deposited on this substrate, to form this boundary layer; Wherein said composition comprise at least solid solution that this free base material and this free gas are formed and compound one of them.
20, the manufacture method of display device panel structure as claimed in claim 19, wherein in this reacting gas exciting step, the importing pressure of oxygen is approximately greater than 1.3mTorr.
21, display device panel structure manufacture method as claimed in claim 19, wherein in this reacting gas exciting step, the importing pressure of nitrogen is approximately greater than 3mTorr.
22, the manufacture method of display device panel structure as claimed in claim 18, wherein this boundary layer formation step comprises that also use physical gas-phase deposition or chemical vapor deposition method form this boundary layer on this substrate.
23, display device panel structure manufacture method as claimed in claim 18, wherein this conductive layer formation step comprises that also use physical gas-phase deposition or chemical vapor deposition method form this conductive layer on this substrate.
24, the manufacture method of display device panel structure as claimed in claim 18, wherein this boundary layer formation step comprises that also the thickness of controlling this boundary layer is between 1 nanometer to 100 nanometer.
25, display device panel structure manufacture method as claimed in claim 24, wherein this boundary layer formation step comprises that also the thickness of controlling this boundary layer is between 3 nanometer to 50 nanometers.
26, the manufacture method of display device panel structure as claimed in claim 18, wherein one of them is synthesized this copper alloy at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal.
27, the manufacture method of display device panel structure as claimed in claim 19, wherein one of them is synthesized this base material at least: magnesium, chromium, titanium, calcium, niobium, manganese, tantalum, nickel, vanadium, hafnium, boron, aluminium, gallium, germanium, tin, molybdenum, tungsten, palladium, zinc, indium, silver, cobalt, iridium and iron by copper and following metal.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7625788B2 (en) | 2007-08-29 | 2009-12-01 | Au Optronics Corp. | Display element and method of manufacturing the same |
| CN102956505A (en) * | 2012-11-19 | 2013-03-06 | 深圳市华星光电技术有限公司 | Manufacture method for switching tube and array substrate |
| CN108573980A (en) * | 2017-03-09 | 2018-09-25 | 群创光电股份有限公司 | Conductor structure and panel device |
-
2006
- 2006-07-28 CN CNB2006101037583A patent/CN100495722C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7625788B2 (en) | 2007-08-29 | 2009-12-01 | Au Optronics Corp. | Display element and method of manufacturing the same |
| US7875885B2 (en) | 2007-08-29 | 2011-01-25 | Au Optronics Corp. | Display element and method of manufacturing the same |
| CN102956505A (en) * | 2012-11-19 | 2013-03-06 | 深圳市华星光电技术有限公司 | Manufacture method for switching tube and array substrate |
| CN102956505B (en) * | 2012-11-19 | 2015-06-17 | 深圳市华星光电技术有限公司 | Manufacture method for switching tube and array substrate |
| CN108573980A (en) * | 2017-03-09 | 2018-09-25 | 群创光电股份有限公司 | Conductor structure and panel device |
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| CN100495722C (en) | 2009-06-03 |
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