CN1885498A - Method for restricting poly-silicon pattern - Google Patents
Method for restricting poly-silicon pattern Download PDFInfo
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- CN1885498A CN1885498A CN 200510079423 CN200510079423A CN1885498A CN 1885498 A CN1885498 A CN 1885498A CN 200510079423 CN200510079423 CN 200510079423 CN 200510079423 A CN200510079423 A CN 200510079423A CN 1885498 A CN1885498 A CN 1885498A
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- polysilicon layer
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Abstract
The provided method to limit polysilicon pattern comprises: forming a polysilicon on a substrate, and a pattern screen layer on top; taking the first etching for the exposed polysilicon layer to form multiple concave holes, stripping the screen layer with gas without O2; finally, etching secondly to let the holes up to substrate surface.
Description
Technical field
The present invention relates to a kind of method of restricting poly-silicon pattern, particularly relate to a kind of method of etching polysilicon layer.
Background technology
Along with the progress of semiconductor process techniques, obtaining having different electrical grid structures, and then the different demands that satisfy semiconductor element have been present trend with the process integration of N type polysilicon and P type polysilicon.Owing to the alloy that N type polysilicon and P type polysilicon are required is different, the two also has different results in the technology performance, for instance, along with the live width of semiconductor element is constantly dwindled, the uniformity of remaining gate oxide all has been developed to the situation of bottleneck after (after-etch-inspectioncritical dimension, AEI CD) live width critical after the profile (profile) of the N type in the semiconductor technology/P type polysilicon layer, the etching and the etching.Therefore, how to provide a desirable method to limit the pattern of N type/P type polysilicon layer, critical live width is close after making the profile of N type/P type polysilicon layer and etching, and makes the gate oxide after the etching that enough residual thickness be arranged, and has become the big problem of one in the present technical field of semiconductors.
Please refer to Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are the method schematic diagram of an existing restricting poly-silicon pattern.As shown in Figure 1, existing method provides a substrate 10 earlier, and in substrate 10, form the screen 16 of a gate oxide 12, a polysilicon layer 14 and a patterning in regular turn, wherein polysilicon layer 14 comprises that one is used for limiting the 14a of doped polysilicon layer of a N type polysilicon layer, and a undoped polycrystalline silicon layer 14b who is used for limiting a P type polysilicon layer.As for 16 of screens is a photoresist layer or a hard screen.
As shown in Figure 2, then carry out an etch process, part polysilicon layer 14 ablations that conductively-closed layer not 16 is covered.When carrying out etch process, because the etching speed of doped polysilicon layer 14a is much larger than undoped polycrystalline silicon layer 14b, cause the dual side-edge of doped polysilicon layer 14a to produce lateral erosion 18 phenomenons, so critical live width is close after can't making the profile of N type/P type polysilicon layer and etching.
Refer again to Fig. 3 and Fig. 4, Fig. 3 and Fig. 4 are the method schematic diagram of existing another restricting poly-silicon pattern.As shown in Figure 3, existing method provides a substrate 30 earlier, and in substrate 30, form the screen 36 of a gate oxide 32, a polysilicon layer 34 and a patterning in regular turn, wherein polysilicon layer 34 comprises the zones of different (not being shown among the figure) that is used for limiting N type/P type polysilicon layer, and polysilicon layer 34 comprises a undoped polycrystalline silicon layer 34a, and one doped polysilicon layer 34b be located at the top of undoped polycrystalline silicon layer 34a.As for 36 of screens is a photoresist layer or a hard screen.
As shown in Figure 4, then carry out an etch process, part polysilicon layer 34 ablations that conductively-closed layer not 36 is covered.When carrying out etch process, because of the etching speed of doped polysilicon layer 34b greater than undoped polycrystalline silicon layer 34a, the dual side-edge of doped polysilicon layer 34b produces the phenomenon of lateral erosion 38 and make.
In view of this, the applicant proposes a kind of method of restricting poly-silicon pattern, especially can make after the profile of N type/P type polysilicon layer of the following technology of 90 nanometers and the etching critical live width close and bigger gate oxide window is arranged, with effective uniformity of improving poly-silicon pattern.
Summary of the invention
Main purpose of the present invention is to provide a kind of method of restricting poly-silicon pattern, so that poly-silicon pattern has uniform profile and live width.
According to claim of the present invention, this method is included in and forms a polysilicon layer in the substrate, and the screen that on polysilicon layer, forms a patterning, then carry out one first etch process, etching is the part polysilicon layer of conductively-closed layer covering not, to form a plurality of potholes in the polysilicon layer surface, carry out a divesting technology then, use oxygen-free gas to divest screen, carry out one second etch process at last, continue the polysilicon layer of etching part, so that a plurality of pothole is sensible to substrate surface.
Because the present invention utilizes the etch process of two-stage to come the pattern of restricting poly-silicon layer, it comprises and utilizes the photoresist screen as etch shield earlier, with polysilicon layer ablation with part, make the polysilicon layer critical live width all similar after appearance profile and etching that is used for limiting zones such as N type doped polysilicon layer and P type doped polysilicon layer, then after removing the photoresist screen, continue again to carry out the etching of polysilicon layer until substrate surface with hard screen, finish the qualification of poly-silicon pattern, therefore critical live width was more close after the present invention can make the outward appearance of N type/P type polysilicon layer of poly-silicon pattern and etching, effectively improved the uniformity of poly-silicon pattern.
Description of drawings
Fig. 1 to Fig. 4 is the existing method that limits a poly-silicon pattern.
Fig. 5 to Fig. 8 limits the method for a poly-silicon pattern for the present invention.
The simple symbol explanation
10 substrates, 12 gate oxides
14 polysilicon layer 14a are doped polysilicon layer
14b undoped polycrystalline silicon layer 16 screen
18 lateral erosion, 30 substrates
32 gate oxides, 34 polysilicon layers
34a undoped polycrystalline silicon layer 34b be doped polysilicon layer
38 lateral erosion of 36 screens
50 substrates, 52 gate oxides
54 polysilicon layer 54a undoped polycrystalline silicon layers
54b is doped polysilicon layer 56 hard screens
58 bottom anti-reflection layer, 60 photoresist screens
62 potholes
Embodiment
Please refer to Fig. 5 to Fig. 8, Fig. 5 to Fig. 8 limits the method for a poly-silicon pattern for the present invention.As shown in Figure 5, the invention provides a substrate 50, silicon base for example then forms the photoresist screen 60 of a gate oxide 52, a polysilicon layer 54 and a patterning, for example the photoresist layer in regular turn in substrate 50.In addition, the present invention needs to form a hard screen 56 between photoresist screen 60 and polysilicon layer 54, and selectivity is used a bottom reflector 58 and/or other material layer, to form the shielding material layer of a plyability, and the equal patterning of shielding material layer that comprises the plyability of hard screen 56 and bottom reflector 58 is to limit the position of a plurality of potholes in polysilicon layer 54 surfaces.
Polysilicon layer 54 comprises the zones of different (not being shown among the figure) that is used for limiting N type/P type polysilicon layer, and polysilicon layer 54 comprises a undoped polycrystalline silicon layer 54a, and one doped polysilicon layer 54b be located at the top of undoped polycrystalline silicon layer 54a.Wherein doped polysilicon layer 54b can mix for the N type, utilizes atoms such as nitrogen or phosphorus as alloy.The material of hard screen 56 can be selected from least a in the following material: dielectric material (dielectrics), silicon dioxide (silica dioxide, SiO
2), silicon nitride (siliconnitride, Si
3N
4), silicon oxynitride (silicon-oxy-nitride, SiO
xN
y), phosphorosilicate glass (phosphosilicate, PSG), boron-phosphorosilicate glass (borophospho-silicate, BPSG), Si oxide (siloxanes) or carbon compound (α-C) etc.Can be a silica layer as for bottom reflector 58, for example silicon oxynitride, organic compound (hydrocarbon) or tetraethoxysilane (tetra-ethyl-ortho-silicate, TEOS).
Then, as shown in Figure 6, carry out one first etch process,, and form a plurality of potholes 62 in the surface of polysilicon layer 54 part polysilicon layer 54 ablations that do not covered by photoresist screen 60.In a preferred embodiment of the invention, ablation partly is approximately the 54b of doped polysilicon layer that is not covered by photoresist screen 60 in this etching step, and exposes the surface of the undoped polycrystalline silicon layer 54a of part.In etching process; because the plasma (plasmer) that etching gas generates can react with photoresist screen 60; and provide abundant macromolecule (polymer) to be deposited on the side of polysilicon layer 54; therefore can protect the side of doped polysilicon layer 54b, avoid causing side to produce the phenomenon of depression or lateral erosion because of etching speed is too fast.
Then, as shown in Figure 7, carry out a divesting technology, utilize oxygen-free (O
2) gas, hydrogen (H for example
2), nitrogen, argon gas, helium or other diluent gas, photoresist screen 60 and bottom anti-reflection layer 58 are divested, and make hard screen 56 residue in the surface of polysilicon layer 54, to be used for being used as the shielding of subsequent etch technology.Wherein, because when using oxygen stripping gas to remove photoresist, oxygen surface easy and polysilicon layer generates oxide, cause the problem of subsequent etch to produce on the contrary, therefore the present invention uses hydrogen, nitrogen, argon gas, helium or other diluent gas to divest photoresist, can avoid oxide to result from the surface of polysilicon layer.
At last, as shown in Figure 8, carry out one second etch process, with exposed portions undoped polycrystalline silicon layer 54a ablation, so that a plurality of pothole 62 sensible upper surfaces to gate oxide 52, the pattern of finishing a plurality of polysilicon gates limits.Wherein, visual demand of second etch process and divesting technology carry out in same reative cell (in-situ), and perhaps second etch process also can carry out in different reative cells with divesting technology.
Because the present invention utilizes the etch process of two-stage to come the pattern of restricting poly-silicon layer, it comprises and utilizes photoresist screen 60 as etch shield earlier, with the 54b of doped polysilicon layer ablation with part, can provide abundant macromolecule to make and be used for limiting the regional 54b of doped polysilicon layer critical live width all similar after appearance profile and etching such as N type doped polysilicon layer and P type doped polysilicon layer, then after removing screen such as photoresist and bottom anti-reflection layer, utilize of the shielding of hard screen 56 again when second etch process, proceed the etching of polysilicon layer, to obtain good polysilicon profile outward appearance.
Moreover, the problem that the present invention is derived when utilizing screen (photoresist layer) 60 and hard screen 56 to come the pattern of restricting poly-silicon layer also can avoid existing method to use single screens such as photoresist layer or hard screen to come restricting poly-silicon pattern simultaneously.For instance, when only using the photoresist layer to come the method for restricting poly-silicon pattern, because the photoresist layer can form the macromolecule deposition in the polysilicon layer side with the etching gas reaction, and the easy residual fluorine activation base of photoresist layer and macromolecule layer (F), and then the doubt that causes gate oxide to be increased by the possibility of eating thrown.In addition; though can improve gate oxide by the problem of eating thrown when only using the method that hard screen comes restricting poly-silicon pattern; yet lose the macromolecule sedimentation mechanism that photoresist reaction generates and protect doped polycrystalline silicon (N type polysilicon) side, will cause the profile of N type/P type polysilicon layer and etching after critical live width have than big-difference.
Comprehensively above-mentioned, the method of restricting poly-silicon layer of the present invention utilizes photoresist layer and hard screen to be used as the shielding of second etch technology and to use oxygen-free gas to carry out divesting of photoresist layer, therefore not only having photoresist layer restricting poly-silicon pattern can have the advantage of critical live width after the appearance profile of close N type and P type polysilicon layer and the etching, utilize hard screen restricting poly-silicon pattern can access the technology of littler live width but also have, and gate oxide is difficult for by eating thrown, so the present invention can improve the production quality and the rate of finished products of semiconductor element.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (23)
1. the method for a restricting poly-silicon pattern, this method comprises:
One substrate is provided;
In this substrate, form a polysilicon layer, and the screen that on this polysilicon layer, forms a patterning;
Carry out one first etch process, this polysilicon layer of part that etching is not covered by this screen is to form a plurality of potholes in this polysilicon layer surface;
Carry out a divesting technology, use oxygen-free gas to divest this screen; And
Carry out one second etch process, continue this polysilicon layer of etching part, so that these a plurality of potholes are sensible to this substrate surface.
2. the method for claim 1, wherein this screen comprises a photoresist layer.
3. the method for claim 1, it also is included in this polysilicon layer surface and forms a hard screen, with the etch shield as this second etch process.
4. method as claimed in claim 3, wherein this hard screen is selected from least a in the following material: dielectric material, silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass, boron-phosphorosilicate glass, Si oxide or carbide.
5. the method for claim 1, wherein this substrate comprises that also a gate oxide is located at this polysilicon layer below.
6. the method for claim 1, wherein this substrate is a silicon base.
7. the method for claim 1, wherein this polysilicon layer comprises one doped polysilicon layer and a undoped polycrystalline silicon layer has been located at this doped polysilicon layer below.
8. method as claimed in claim 7, wherein this doped polysilicon layer be N type doped polysilicon layer.
9. method as claimed in claim 7, this first etch process this doped polysilicon layer of removing that screen limits wherein is to form these a plurality of potholes.
10. method as claimed in claim 7, wherein this second etch process is removed this undoped polycrystalline silicon layer, so that these a plurality of potholes are sensible to this substrate surface.
11. the method for claim 1, this gas that wherein divests photoresist technology comprises hydrogen, nitrogen, argon gas, helium or other diluent gas.
12. the method for claim 1, wherein this divesting technology and this second etch process carry out in same reative cell.
13. the method for claim 1, wherein this divesting technology and this second etch process carry out in the differential responses chamber.
14. the method for a restricting poly-silicon pattern, this method comprises:
One substrate is provided;
Form a gate oxide on this basalis, a polysilicon layer on this gate oxide, a hard screen is located on this polysilicon layer, a bottom anti-reflection layer is located on this hard screen and a photoresist layer is located on this bottom anti-reflection layer;
Carry out one first etch process, this polysilicon layer of part that etching is not covered by this photoresist layer;
Carry out a divesting technology, use oxygen-free gas to divest this photoresist layer and this bottom reflector, and make this hard screen residue in this polysilicon layer surface; And
Carry out one second etch process, this polysilicon layer of part that etching is not covered by this hard screen.
15. method as claimed in claim 14, wherein this hard screen is selected from least a in the following material: dielectric material, silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass, boron-phosphorosilicate glass, Si oxide or carbide.
16. method as claimed in claim 14, wherein this substrate is a silicon base.
17. method as claimed in claim 14, wherein this polysilicon layer comprises one doped polysilicon layer and a undoped polycrystalline silicon layer has been located at this doped polysilicon layer below.
18. method as claimed in claim 17, wherein this doped polysilicon layer be N type doped polysilicon layer.
19. method as claimed in claim 17, wherein this first etch process this doped polysilicon layer of removing that photoresist layer limits.
20. method as claimed in claim 17, wherein this second etch process is removed this undoped polycrystalline silicon layer.
21. method as claimed in claim 14, wherein this gas is hydrogen, nitrogen, argon gas, helium or other diluent gas.
22. method as claimed in claim 14, wherein this divesting technology and this second etch process carry out in same reative cell.
23. method as claimed in claim 14, wherein this divesting technology and this second etch process carry out in the differential responses chamber.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100794238A CN100392822C (en) | 2005-06-21 | 2005-06-21 | Method for restricting poly-silicon pattern |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100794238A CN100392822C (en) | 2005-06-21 | 2005-06-21 | Method for restricting poly-silicon pattern |
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| Publication Number | Publication Date |
|---|---|
| CN1885498A true CN1885498A (en) | 2006-12-27 |
| CN100392822C CN100392822C (en) | 2008-06-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100794238A Active CN100392822C (en) | 2005-06-21 | 2005-06-21 | Method for restricting poly-silicon pattern |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107785247A (en) * | 2016-08-24 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of metal gates and semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW428226B (en) * | 1998-02-06 | 2001-04-01 | United Microelectronics Corp | Method for defining polysilicon pattern |
| KR100280622B1 (en) * | 1998-04-02 | 2001-03-02 | 윤종용 | Contact Forming Method of Semiconductor Device |
| US6509228B1 (en) * | 2000-08-29 | 2003-01-21 | United Microelectronics Corp. | Etching procedure for floating gate formation of a flash memory device |
| US6680262B2 (en) * | 2001-10-25 | 2004-01-20 | Intel Corporation | Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface |
| US20040018739A1 (en) * | 2002-07-26 | 2004-01-29 | Applied Materials, Inc. | Methods for etching using building blocks |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107785247A (en) * | 2016-08-24 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of metal gates and semiconductor devices |
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| CN100392822C (en) | 2008-06-04 |
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