CN1885498A - Method of Defining Polysilicon Patterns - Google Patents
Method of Defining Polysilicon Patterns Download PDFInfo
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- CN1885498A CN1885498A CN 200510079423 CN200510079423A CN1885498A CN 1885498 A CN1885498 A CN 1885498A CN 200510079423 CN200510079423 CN 200510079423 CN 200510079423 A CN200510079423 A CN 200510079423A CN 1885498 A CN1885498 A CN 1885498A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 143
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 136
- 238000000034 method Methods 0.000 title claims abstract description 81
- 238000005530 etching Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000007789 gas Substances 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000003085 diluting agent Substances 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims 4
- 238000000059 patterning Methods 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 230000000873 masking effect Effects 0.000 description 21
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- 230000003628 erosive effect Effects 0.000 description 4
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
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- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
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- 125000004429 atom Chemical group 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
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- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
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Abstract
Description
技术领域technical field
本发明涉及一种限定多晶硅图案的方法，特别是涉及一种蚀刻多晶硅层的方法。The present invention relates to a method for defining a polysilicon pattern, in particular to a method for etching a polysilicon layer.
背景技术Background technique
随着半导体工艺技术的进步，将N型多晶硅与P型多晶硅的工艺整合以获得具有不同电性的栅极结构，进而满足半导体元件的不同需求已是目前的趋势。由于N型多晶硅与P型多晶硅所需的掺杂物不同，二者在工艺表现上亦有不同的结果，举例来说，随着半导体元件的线宽不断缩小，半导体工艺中的N型/P型多晶硅层的轮廓(profile)、蚀刻后临界(after-etch-inspectioncritical dimension，AEI CD)线宽以及蚀刻后剩余的栅氧化层的均匀度均已发展至瓶颈的情况。因此，如何提供一理想的方法来限定N型/P型多晶硅层的图案，使N型/P型多晶硅层的轮廓与蚀刻后临界线宽相近，并且使蚀刻后的栅氧化层有足够的剩余厚度，已成为目前半导体技术领域中的一大课题。With the advancement of semiconductor process technology, it is a current trend to integrate N-type polysilicon and P-type polysilicon processes to obtain gate structures with different electrical properties, thereby satisfying different requirements of semiconductor devices. Since the dopants required for N-type polysilicon and P-type polysilicon are different, the two also have different results in terms of process performance. For example, as the line width of semiconductor devices continues to shrink, the N-type/P The profile of the type polysilicon layer, the after-etch-inspection critical dimension (AEI CD) line width, and the uniformity of the gate oxide layer remaining after etching have all developed to bottlenecks. Therefore, how to provide an ideal method to define the pattern of the N-type/P-type polysilicon layer, so that the outline of the N-type/P-type polysilicon layer is close to the critical line width after etching, and the gate oxide layer after etching has enough remaining Thickness has become a major issue in the field of semiconductor technology.
请参考图1与图2，图1与图2为现有一限定多晶硅图案的方法示意图。如图1所示，现有方法先提供一基底10，并于基底10上依序形成一栅氧化层12、一多晶硅层14以及一图案化的屏蔽层16，其中多晶硅层14包括一用来限定一N型多晶硅层的已掺杂多晶硅层14a，以及一用来限定一P型多晶硅层的未掺杂多晶硅层14b。至于屏蔽层16则为一光致抗蚀剂层或一硬屏蔽层。Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic diagrams of a conventional method for defining polysilicon patterns. As shown in Figure 1, the existing method first provides a
如图2所示，接着进行一蚀刻工艺，将未被屏蔽层16覆盖的部分多晶硅层14蚀除。在进行蚀刻工艺时，由于已掺杂多晶硅层14a的蚀刻速度远大于未掺杂多晶硅层14b，造成已掺杂多晶硅层14a的二侧边产生侧蚀18现象，所以无法使N型/P型多晶硅层的轮廓与蚀刻后临界线宽相近。As shown in FIG. 2 , an etching process is then performed to etch away part of the polysilicon layer 14 not covered by the
请再参考图3与图4，图3与图4为现有另一限定多晶硅图案的方法示意图。如图3所示，现有方法先提供一基底30，并于基底30上依序形成一栅氧化层32、一多晶硅层34以及一图案化的屏蔽层36，其中多晶硅层34包括用来限定N型/P型多晶硅层的不同区域(未显示于图中)，且多晶硅层34包括一未掺杂多晶硅层34a，以及一已掺杂多晶硅层34b设于未掺杂多晶硅层34a的上方。至于屏蔽层36则为一光致抗蚀剂层或一硬屏蔽层。Please refer to FIG. 3 and FIG. 4 again. FIG. 3 and FIG. 4 are schematic diagrams of another conventional method for defining polysilicon patterns. As shown in FIG. 3 , the existing method first provides a substrate 30, and sequentially forms a gate oxide layer 32, a polysilicon layer 34, and a patterned shielding layer 36 on the substrate 30, wherein the polysilicon layer 34 includes Different regions of the N-type/P-type polysilicon layer (not shown in the figure), and the polysilicon layer 34 includes an undoped polysilicon layer 34a, and a doped polysilicon layer 34b disposed on the undoped polysilicon layer 34a. As for the masking layer 36, it is a photoresist layer or a hard masking layer.
如图4所示，接着进行一蚀刻工艺，将未被屏蔽层36覆盖的部分多晶硅层34蚀除。当进行蚀刻工艺时，因已掺杂多晶硅层34b的蚀刻速度大于未掺杂多晶硅层34a，而使已掺杂多晶硅层34b的二侧边产生侧蚀38的现象。As shown in FIG. 4 , an etching process is then performed to etch away the portion of the polysilicon layer 34 not covered by the shielding layer 36 . During the etching process, since the etching rate of the doped polysilicon layer 34b is higher than that of the undoped polysilicon layer 34a, side erosion 38 occurs on two sides of the doped polysilicon layer 34b.
有鉴于此，申请人提出一种限定多晶硅图案的方法，尤其可使90纳米以下的工艺的N型/P型多晶硅层的轮廓与蚀刻后临界线宽相近并有较大的栅氧化层窗口，以有效改善多晶硅图案的均匀度。In view of this, the applicant proposes a method for defining a polysilicon pattern, especially to make the outline of the N-type/P-type polysilicon layer of a process below 90 nanometers close to the critical line width after etching and have a larger gate oxide layer window, To effectively improve the uniformity of the polysilicon pattern.
发明内容Contents of the invention
本发明的主要目的在于提供一种限定多晶硅图案的方法，以使多晶硅图案具有均匀的轮廓与线宽。The main objective of the present invention is to provide a method for defining a polysilicon pattern so that the polysilicon pattern has a uniform profile and line width.
根据本发明的权利要求，该方法包括于一基底上形成一多晶硅层，以及于多晶硅层上形成一图案化的屏蔽层，接着进行一第一蚀刻工艺，蚀刻未被屏蔽层覆盖的部分多晶硅层，以于多晶硅层表面形成多个凹洞，然后进行一剥除工艺，使用不含氧的气体剥除屏蔽层，最后进行一第二蚀刻工艺，继续蚀刻部分的多晶硅层，以使多个凹洞通达至基底表面。According to the claims of the present invention, the method includes forming a polysilicon layer on a substrate, and forming a patterned masking layer on the polysilicon layer, and then performing a first etching process to etch a part of the polysilicon layer not covered by the masking layer , to form a plurality of cavities on the surface of the polysilicon layer, then perform a stripping process, use an oxygen-free gas to strip the shielding layer, and finally perform a second etching process to continue etching part of the polysilicon layer, so that the multiple cavities The holes reach to the substrate surface.
由于本发明是利用二阶段的蚀刻工艺来限定多晶硅层的图案，其包括先利用光致抗蚀剂屏蔽层作为蚀刻屏蔽，以将部分的多晶硅层蚀除，使用来限定N型掺杂多晶硅层与P型掺杂多晶硅层等区域的多晶硅层在外观轮廓以及蚀刻后临界线宽均相似，接着在去除光致抗蚀剂屏蔽层后，再继续以硬屏蔽层进行多晶硅层的蚀刻直至基底表面，完成多晶硅图案的限定，因此本发明可以使多晶硅图案的N型/P型多晶硅层的外观和蚀刻后临界线宽更为相近，有效改善多晶硅图案的均匀度。Since the present invention utilizes a two-stage etching process to define the pattern of the polysilicon layer, it includes utilizing the photoresist masking layer as an etching mask earlier to remove part of the polysilicon layer and use it to define the N-type doped polysilicon layer The polysilicon layer is similar to the P-type doped polysilicon layer in appearance profile and critical line width after etching. After removing the photoresist shielding layer, continue to etch the polysilicon layer with a hard masking layer until the surface of the substrate , to complete the definition of the polysilicon pattern, so the present invention can make the appearance of the N-type/P-type polysilicon layer of the polysilicon pattern closer to the critical line width after etching, and effectively improve the uniformity of the polysilicon pattern.
附图说明Description of drawings
图1至图4为现有限定一多晶硅图案的方法。1 to 4 illustrate a conventional method for defining a polysilicon pattern.
图5至图8为本发明限定一多晶硅图案的方法。5 to 8 illustrate the method of defining a polysilicon pattern according to the present invention.
简单符号说明simple notation
10 基底 12 栅氧化层10
14 多晶硅层 14a 已掺杂多晶硅层14 Polysilicon
14b 未掺杂多晶硅层 16 屏蔽层14b undoped
18 侧蚀 30 基底18 side erosion 30 base
32 栅氧化层 34 多晶硅层32 Gate oxide layer 34 Polysilicon layer
34a 未掺杂多晶硅层 34b 已掺杂多晶硅层34a undoped polysilicon layer 34b doped polysilicon layer
36 屏蔽层 38 侧蚀36 Shielding layer 38 Side erosion
50 基底 52 栅氧化层50 Base 52 Gate Oxide
54 多晶硅层 54a 未掺杂多晶硅层54 Polysilicon layer 54a Undoped polysilicon layer
54b 已掺杂多晶硅层 56 硬屏蔽层54b Doped Polysilicon Layer 56 Hard Shield
58 底部抗反射层 60 光致抗蚀剂屏蔽层58 Bottom anti-reflection layer 60 Photoresist shielding layer
62 凹洞62 pits
具体实施方式Detailed ways
请参考图5至图8，图5至图8为本发明限定一多晶硅图案的方法。如图5所示，本发明提供一基底50，例如硅基底，接着于基底50上依序形成一栅氧化层52、一多晶硅层54、以及一图案化的光致抗蚀剂屏蔽层60，例如光致抗蚀剂层。此外，本发明于光致抗蚀剂屏蔽层60以及多晶硅层54之间需形成一硬屏蔽层56，并选择性使用一底部反射层58及/或其它材料层，以形成一复合性的屏蔽材料层，且包括硬屏蔽层56及底部反射层58在内的复合性的屏蔽材料层均已图案化，以于多晶硅层54表面限定出多个凹洞的位置。Please refer to FIG. 5 to FIG. 8 . FIG. 5 to FIG. 8 illustrate a method for defining a polysilicon pattern according to the present invention. As shown in FIG. 5, the present invention provides a substrate 50, such as a silicon substrate, and then sequentially form a gate oxide layer 52, a polysilicon layer 54, and a patterned photoresist masking layer 60 on the substrate 50, For example photoresist layer. In addition, the present invention needs to form a hard mask layer 56 between the photoresist mask layer 60 and the polysilicon layer 54, and optionally uses a bottom reflective layer 58 and/or other material layers to form a composite mask The material layer, and the composite masking material layer including the hard masking layer 56 and the bottom reflective layer 58 have been patterned to define a plurality of cavities on the surface of the polysilicon layer 54 .
多晶硅层54包括用来限定N型/P型多晶硅层的不同区域(未显示于图中)，且多晶硅层54包括一未掺杂多晶硅层54a，以及一已掺杂多晶硅层54b设于未掺杂多晶硅层54a的上方。其中已掺杂多晶硅层54b可以为N型掺杂，利用氮或磷等原子作为掺杂物。硬屏蔽层56的材料可选自下列材料中的至少一种：介电材料(dielectrics)、二氧化硅(silica dioxide，SiO2)、氮化硅(siliconnitride，Si3N4)、氮氧化硅(silicon-oxy-nitride，SiOxNy)、磷硅玻璃(phosphosilicate，PSG)、硼磷硅玻璃(borophospho-silicate，BPSG)、硅氧化物(siloxanes)或碳化合物(α-C)等。至于底部反射层58可以为一硅氧层，例如氮氧化硅、有机化合物(碳氢化合物)或四乙氧基硅烷(tetra-ethyl-ortho-silicate，TEOS)。The polysilicon layer 54 includes different regions (not shown) used to define N-type/P-type polysilicon layers, and the polysilicon layer 54 includes an undoped polysilicon layer 54a, and a doped polysilicon layer 54b located on the undoped polysilicon layer. heteropolysilicon layer 54a. The doped polysilicon layer 54b can be N-type doped, using atoms such as nitrogen or phosphorus as dopants. The material of the hard mask layer 56 can be selected from at least one of the following materials: dielectric materials (dielectrics), silicon dioxide (silica dioxide, SiO 2 ), silicon nitride (siliconnitride, Si 3 N 4 ), silicon oxynitride (silicon-oxy-nitride, SiO x N y ), phosphosilicate glass (phosphosilicate, PSG), borophospho-silicate glass (borophospho-silicate, BPSG), silicon oxide (siloxanes) or carbon compound (α-C), etc. The bottom reflective layer 58 can be a silicon oxide layer, such as silicon oxynitride, organic compound (hydrocarbon) or tetra-ethyl-ortho-silicate (TEOS).
接着，如图6所示，进行一第一蚀刻工艺，将未被光致抗蚀剂屏蔽层60所覆盖的部分多晶硅层54蚀除，并于多晶硅层54的表面形成多个凹洞62。在本发明的优选实施例中，此蚀刻步骤中蚀除部分大约为未被光致抗蚀剂屏蔽层60覆盖的已掺杂多晶硅层54b，并且暴露出部分的未掺杂多晶硅层54a的表面。在蚀刻过程中，由于蚀刻气体生成的等离子(plasmer)可与光致抗蚀剂屏蔽层60反应，并提供丰富的高分子(polymer)沉积于多晶硅层54的侧边，因此可以保护已掺杂多晶硅层54b的侧边，避免因蚀刻速度过快造成侧边产生凹陷或侧蚀的现象。Next, as shown in FIG. 6 , a first etching process is performed to etch away a portion of the polysilicon layer 54 not covered by the photoresist masking layer 60 and form a plurality of cavities 62 on the surface of the polysilicon layer 54 . In a preferred embodiment of the present invention, in this etching step, the etched portion is approximately the doped polysilicon layer 54b not covered by the photoresist masking layer 60, and exposes a portion of the surface of the undoped polysilicon layer 54a. . During the etching process, since the plasma (plasmer) generated by the etching gas can react with the photoresist masking layer 60, and provide abundant macromolecule (polymer) to be deposited on the side of the polysilicon layer 54, it can protect the doped The side of the polysilicon layer 54b avoids the phenomenon that the side is recessed or side-etched due to too fast etching speed.
然后，如图7所示，进行一剥除工艺，利用不含氧(O2)的气体，例如氢气(H2)、氮气、氩气、氦气或其它稀释气体，将光致抗蚀剂屏蔽层60以及底部抗反射层58剥除，并使硬屏蔽层56残留于多晶硅层54的表面，以用来当作后续蚀刻工艺的屏蔽。其中，由于使用氧气剥除光致抗蚀剂时，氧气容易与多晶硅层的表面生成氧化物，反而造成后续蚀刻的问题产生，因此本发明使用氢气、氮气、氩气、氦气或其它稀释气体来剥除光致抗蚀剂，可避免氧化物产生于多晶硅层的表面上。Then, as shown in FIG. 7, a stripping process is carried out , and the photoresist The masking layer 60 and the bottom anti-reflective layer 58 are stripped off, and the hard masking layer 56 remains on the surface of the polysilicon layer 54 to be used as a masking for the subsequent etching process. Among them, when oxygen is used to strip the photoresist, oxygen is easy to form oxides with the surface of the polysilicon layer, which causes subsequent etching problems instead, so the present invention uses hydrogen, nitrogen, argon, helium or other diluent gases To strip the photoresist, it is possible to avoid oxide generation on the surface of the polysilicon layer.
最后，如图8所示，进行一第二蚀刻工艺，将暴露的部分未掺杂多晶硅层54a蚀除，以使多个凹洞62通达至栅氧化层52的上表面，完成多个多晶硅栅极的图案限定。其中，第二蚀刻工艺可视需求与剥除工艺于同一反应室(in-situ)进行，或者第二蚀刻工艺亦可与剥除工艺于不同的反应室中进行。Finally, as shown in FIG. 8, a second etching process is performed to remove the exposed part of the undoped polysilicon layer 54a, so that a plurality of cavities 62 reach the upper surface of the gate oxide layer 52, and a plurality of polysilicon gates are completed. Pole patterns are limited. Wherein, the second etching process and the stripping process may be performed in the same reaction chamber (in-situ) as required, or the second etching process may be performed in a different reaction chamber from the stripping process.
由于本发明是利用二阶段的蚀刻工艺来限定多晶硅层的图案，其包括先利用光致抗蚀剂屏蔽层60作为蚀刻屏蔽，以将部分的已掺杂多晶硅层54b蚀除，可提供丰富的高分子使用来限定N型掺杂多晶硅层与P型掺杂多晶硅层等区域的已掺杂多晶硅层54b在外观轮廓以及蚀刻后临界线宽均相似，接着在去除光致抗蚀剂等屏蔽层以及底部抗反射层后，再利用硬屏蔽层56当第二蚀刻工艺的屏蔽，继续进行多晶硅层的蚀刻，以得到良好的多晶硅轮廓外观。Since the present invention uses a two-stage etching process to define the pattern of the polysilicon layer, which includes first using the photoresist mask layer 60 as an etching mask to etch away part of the doped polysilicon layer 54b, it can provide abundant The doped polysilicon layer 54b used by the polymer to define the regions of the N-type doped polysilicon layer and the P-type doped polysilicon layer has similar appearance profiles and critical line widths after etching, and then removes the photoresist and other shielding layers After the bottom anti-reflection layer is removed, the hard mask layer 56 is used as the mask of the second etching process to continue etching the polysilicon layer to obtain a good polysilicon outline appearance.
再者，本发明同时利用屏蔽层(光致抗蚀剂层)60以及硬屏蔽层56来限定多晶硅层的图案也可以避免现有方法使用光致抗蚀剂层或硬屏蔽层等单一屏蔽层来限定多晶硅图案时所衍生的问题。举例来说，仅使用光致抗蚀剂层来限定多晶硅图案的方法时，由于光致抗蚀剂层会与蚀刻气体反应而于多晶硅层侧边形成高分子沉积，而光致抗蚀剂层与高分子层易残留氟活化基(F□)，进而造成栅氧化层被蚀穿的可能性增加的疑虑。另外，仅使用硬屏蔽层来限定多晶硅图案的方法时虽能改善栅氧化层被蚀穿的问题，然而失去光致抗蚀剂反应生成的高分子沉积机制来保护已掺杂多晶硅(N型多晶硅)侧边，将导致N型/P型多晶硅层的轮廓及蚀刻后临界线宽具有较大差异。Furthermore, the present invention utilizes the masking layer (photoresist layer) 60 and the hard masking layer 56 to define the pattern of the polysilicon layer and can also avoid the use of a single masking layer such as a photoresist layer or a hard masking layer in the existing method. The problems derived from defining the polysilicon pattern. For example, when only using the photoresist layer to define the polysilicon pattern method, since the photoresist layer will react with the etching gas to form polymer deposits on the side of the polysilicon layer, and the photoresist layer The fluorine active group (F□) is likely to remain in the polymer layer, which may increase the possibility of the gate oxide layer being etched through. In addition, although the method of only using a hard mask layer to define the polysilicon pattern can improve the problem of the gate oxide layer being etched through, it loses the polymer deposition mechanism generated by the photoresist reaction to protect the doped polysilicon (N-type polysilicon) ) side, which will lead to a large difference in the outline of the N-type/P-type polysilicon layer and the critical line width after etching.
综合上述，本发明的限定多晶硅层的方法利用光致抗蚀剂层与硬屏蔽层来当作二次蚀刻工艺的屏蔽以及使用不含氧的气体来进行光致抗蚀剂层的剥除，因此不但拥有光致抗蚀剂层限定多晶硅图案能够有相近的N型与P型多晶硅层的外观轮廓和蚀刻后临界线宽的优点，而且还有利用硬屏蔽层限定多晶硅图案能够得到更小线宽的工艺，且栅氧化层不易被蚀穿，因此本发明可以提高半导体元件的生产品质与成品率。In summary, the method for limiting the polysilicon layer of the present invention utilizes the photoresist layer and the hard mask layer as a shield for the secondary etching process and uses an oxygen-free gas to strip the photoresist layer, Therefore, not only the photoresist layer defines the polysilicon pattern can have the advantages of similar appearance profile and critical line width after etching of the N-type and P-type polysilicon layer, but also uses the hard mask layer to define the polysilicon pattern to obtain smaller lines. Wide process, and the gate oxide layer is not easy to be etched through, so the invention can improve the production quality and yield of semiconductor elements.
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.
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